CN115483284A - 一种改进型sg igbt的制备方法及应用 - Google Patents

一种改进型sg igbt的制备方法及应用 Download PDF

Info

Publication number
CN115483284A
CN115483284A CN202210861671.1A CN202210861671A CN115483284A CN 115483284 A CN115483284 A CN 115483284A CN 202210861671 A CN202210861671 A CN 202210861671A CN 115483284 A CN115483284 A CN 115483284A
Authority
CN
China
Prior art keywords
layer
poly
igbt
etching
improved
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210861671.1A
Other languages
English (en)
Inventor
王波
张庆雷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Linzhong Electronic Technology Co ltd
Original Assignee
Shanghai Linzhong Electronic Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Linzhong Electronic Technology Co ltd filed Critical Shanghai Linzhong Electronic Technology Co ltd
Priority to CN202210861671.1A priority Critical patent/CN115483284A/zh
Publication of CN115483284A publication Critical patent/CN115483284A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

本发明涉及H01L29/00技术领域，具体涉及一种改进型SG IGBT的制备方法及应用。一种改进型SG IGBT的制备方法，包括以下步骤：S1.通过在晶圆底层上进行刻蚀形成沟槽；S2.通过在沟槽处的硅层表面进行氧化形成Gate Oxide，或进行氮化硅的沉积，形成SiN层；S3.在Gate Oxide上进行多晶硅的沉积形成Poly层；S4.在Poly层上进行蚀形成Poly层；S5.经过离子注入硼，进行表面沉积形成氧化层，通过对接触孔刻蚀，经过离子注入含硼化合物，在高温热过程退火处理后形成P+区，并通过金属淀积形成金属层。通过本发明提供的制备方法可以获得具有提升SG IGBT的击穿电压，并降低了开通损耗和栅极‑集电极电容的改进型SG IGBT的结构。

Description

一种改进型SG IGBT的制备方法及应用
技术领域
本发明涉及H01L29/00技术领域，具体涉及一种改进型SG IGBT的制备方法及应用。
背景技术
绝缘栅双极型晶体管(IGBT，Insulated Gate Bipolar Transistor)，目前已成为现代电力电子电路中的核心元器件之一，被广泛应用于交通、能源、工业、家用电器等领域；传统的SG(Side Gate)IGBT能减小栅极-集电极电容，减小开通损耗，但存在击穿电压不足的问题。
目前在文献“A comparative study of oxidized spacer trench and micro-pattern trench concepts for 1200V IGBTs”中公开了SG IGBT中存在击穿电压不足的问题。因此，提供一种能减小栅极-集电极电容及开通损耗，并能提升击穿电压的绝缘栅双极型晶体管技术是目前需要解决的主要技术问题。
发明内容
为了解决上面问题，本发明第一方面提供了一种改进型SG IGBT的制备方法，包括以下步骤：
S1.通过在晶圆底层上进行刻蚀形成沟槽；
S2.通过在沟槽处的硅层表面进行氧化形成Gate Oxide，或进行氮化硅的沉积，形成SiN层；
S3.在Gate Oxide上进行多晶硅的沉积形成Poly层，或在SiN层上通过各向异性刻蚀形成SiN Spacer；
S4.在Poly层上进行蚀形成Poly层或Poly Spacer；
S5.经过离子注入硼，进行表面沉积形成氧化层，通过对接触孔刻蚀，经过离子注入含硼化合物，在高温热过程退火处理后形成P+区，并通过金属淀积形成金属层。
优选地，所述S1中在晶圆底层上通过离子注入硼，通过推阱处理形成Pbody 区，通过离子注入砷，经过退火处理形成N+区，通过在形成N+区的基底层上进行刻蚀形成沟槽。
Gate Oxide：栅极氧化层的沉积。
SiN层：氮化硅层。
Poly层：栅极层。
SiN Spacer：氮化硅侧墙。
Poly Spacer：多晶硅的侧墙。
P+区：P区。
Pbody区：向硅晶内注入掺杂硼形成Pbody区。
N+区：N区。
优选地，所述S2中在沟槽处的硅层表面进行氧化形成Gate Oxide，在Gate Oxide上进行多晶硅的沉积形成Poly层。
优选地，所述S4中通过各向异性刻蚀成Poly层或Poly Spacer。
优选地，所述S5中经过离子注入硼，经过推阱处理形成P型掺杂层，并在 P型掺杂层上进行表面沉积形成氧化层，通过对接触孔刻蚀，经过离子注入硼，在高温热过程退火处理后形成P+区，并通过金属淀积形成金属层。
进一步地，所述改进的SG IGBT结构为P-layer SG IGBT结构，所述P-layer SGIGBT结构的制造工艺，包括以下步骤：
S1.在晶圆底层上通过离子注入硼，通过推阱处理形成Pbody区，通过离子注入砷，经过退火处理形成N+区；
S2.通过在形成N+区的基底层上进行刻蚀形成沟槽；
S3.在沟槽处的硅层表面进行氧化形成Gate Oxide，在Gate Oxide上进行多晶硅的沉积形成Poly层；
S4.在Poly层上通过各向异性刻蚀形成Poly层作为Gate；
S5.经过离子注入硼，经过推阱处理形成P型掺杂层；
S6.在P型掺杂层上进行表面沉积形成氧化层，通过对接触孔刻蚀，经过离子注入硼，在高温热过程退火处理后形成P+区，并通过金属淀积形成金属层。
P-layer SG IGBT：P层型SG IGBT。
通过本发明中限定P-layer SG IGBT结构的类型，与传统的SG IGBT结构相比，在沟槽底部增加了P型掺杂层，用于保护沟槽栅的底部，从而提升了SG IGBT 的击穿电压，并降低了开通损耗。
优选地，所述S2中在沟槽处的硅层表面进行氧化形成第一Gate Oxide；所述S3中在第一Gate Oxide上进行多晶硅的沉积形成第一Poly层；所述S4中在第一Poly层上通过各向异性刻蚀形成Poly层；并在Poly层上进行表面氧化形成第二Gate Oxide，在第二GateOxide上进行多晶硅的沉积形成第二Poly层。
优选地，所述第二Poly层上进行刻蚀形成Poly Gate。
优选地，所述形成Poly Gate后进行表面沉积形成氧化层，通过对接触孔刻蚀，经过离子注入二氟化硼，在高温热过程中退火形成P+区，并通过金属淀积形成金属层。
进一步地，所述改进的SG IGBT结构为SSG(Split Side Gate)IGBT结构，所述SSG(Split Side Gate)IGBT结构的制造工艺，包括以下步骤：
S1.在晶圆底层上通过离子注入硼，通过推阱处理形成Pbody区，通过离子注入磷，经过退火处理形成N+区；
S2.通过在形成N+区的基底层上进行刻蚀形成沟槽；
S3.在沟槽处的硅层表面进行氧化形成第一Gate Oxide，在第一Gate Oxide 上进行多晶硅的沉积形成第一Poly层；
S4.在第一Poly层上通过各向异性刻蚀形成Poly层；通过各向同性刻蚀去除裸露的第一Gate Oxide。
S5.在Poly层上进行表面氧化形成第二Gate Oxide，在第二Gate Oxide上进行多晶硅的沉积形成第二Poly层；
S6.在第二Poly层上进行刻蚀形成Poly Gate；
S7.进行表面沉积形成氧化层，通过对接触孔刻蚀，经过离子注入二氟化硼，在高温热过程中退火形成P+区，并通过金属淀积形成金属层。
Poly Gate：栅极。
SSG(Split Side Gate)IGBT：分体式侧门型IGBT。
通过本发明中限定SSG(Split Side Gate)IGBT结构的类型，与传统的SG IGBT结构相比，在沟槽底部增加了Poly层，形成分栅，用于保护沟槽栅的底部，从而提升了SG IGBT的击穿电压，并降低了开通损耗和栅极-集电极电容。
优选地，所述S3中形成SiN侧墙后通过热氧化形成厚氧化物层，通过各向同性刻蚀去除SiN侧墙，然后热氧化形成栅氧层，在栅氧层上进行多晶硅的沉积形成Poly层。
进一步地，所述改进的SG IGBT结构为TO(Thick Oxide)SG IGBT结构，所述TO(Thick Oxide)SG IGBT结构的制造工艺，包括以下步骤：
S1.在晶圆底层进行刻蚀形成沟槽；
S2.在沟槽处的硅层表面进行氮化硅的沉积，形成SiN层；
S3.在SiN层上通过各向异性刻蚀形成SiN侧墙；
S4.通过热氧化形成厚氧化物层；
S5.通过各向同性刻蚀去除SiN侧墙，然后热氧化形成栅氧层；
S6.在栅氧层上进行多晶硅的沉积形成Poly层；
S7.在Poly层上通过各向异性刻蚀形成Poly Spacer作为栅极；通过各向异性刻蚀去除表面的厚氧化物层，保留Poly栅下的厚氧化物层；
S8.进行表面沉积形成氧化层，通过对接触孔刻蚀，经过离子注入硼，在高温热过程退火处理后形成P+区，并通过金属淀积形成金属层。
TO(Thick Oxide)SG IGBT：厚氧化物型SG IGBT。
通过本发明中限定TO(Thick Oxide)SG IGBT结构的类型，与传统的SG IGBT 结构相比，在沟槽底部增加了厚氧化层保护层，用于保护沟槽栅的底部，从而提升了SG IGBT的击穿电压，并降低了开通损耗和栅极-集电极电容。
本发明第二方面提供了一种改进型SG IGBT的制备方法在制备SG IGBT技术领域中进行应用。
有益效果
1.通过本发明制备方法制备得到的P-layer SG IGBT结构，与传统SG IGBT 结构相比，在沟槽底部增加了P型掺杂层，用于保护沟槽栅的底部，从而提升了 SG IGBT的击穿电压，并降低了开通损耗。
2.通过本发明制备方法制备得到的SSG(Split Side Gate)IGBT结构与传统的SGIGBT结构相比，在沟槽底部增加了Poly层，形成分栅，用于保护沟槽栅的底部，从而提升了SG IGBT的击穿电压，并降低了开通损耗和栅极-集电极电容。
3.通过本发明制备方法制备得到的TO(Thick Oxide)SG IGBT结构与传统的SGIGBT结构相比，在沟槽底部增加了厚氧化层保护层，用于保护沟槽栅的底部，从而提升了SGIGBT的击穿电压，并降低了开通损耗和栅极-集电极电容。
4.通过本发明提供的制备方法可以获得具有提升SG IGBT的击穿电压，并降低了开通损耗和栅极-集电极电容的改进型SG IGBT的结构。
附图说明
图1为传统SG IGBT的结构和实施例1获得P-layer SG IGBT结构的对比示意图。
图2中a为实施例1获得N+区的示意图。
图2中b为实施例1获得沟槽的示意图。
图2中c为实施例1获得Gate Oxide和Poly层的示意图。
图3中d为实施例1获得Gate的示意图。
图3中e为实施例1获得P型掺杂层的示意图。
图3中f为实施例1获得金属层的示意图。
图4为传统SG IGBT的结构和实施例2获得SSG(Split Side Gate)IGBT 结构的对比示意图。
图5中a为实施例2获得N+区的示意图。
图5中b为实施例2获得沟槽的示意图。
图5中c为实施例2获得第一Gate Oxide和第一Poly层的示意图。
图6中d为实施例2获得Poly层的示意图。
图6中e为实施例2获得第二Gate Oxide和第二Poly层的示意图。
图6中f为实施例2获得Poly Gate的示意图。
图7中g为实施例2获得金属层的示意图。
图8为传统SG IGBT的结构和实施例3获得TO(Thick Oxide)SG IGBT 结构的对比示意图。
图9中a为实施例3获得沟槽的示意图。
图9中b为实施例3获得SiN层的示意图。
图9中c为实施例3获得SiN侧墙的示意图。
图10中d为实施例3获得厚氧化物层的示意图。
图10中e为实施例3获得栅氧层的示意图。
图10中f为实施例3获得Poly层的示意图。
图11中g为实施例3获得保留Poly栅下的厚氧化物层的示意图。
图11中h为实施例3获得金属层的示意图。
具体实施方式
实施例1
一种改进的SG IGBT结构的制造工艺，包括以下步骤：
S1.在晶圆底层上通过离子注入硼，通过推阱处理形成Pbody区，通过离子注入砷，经过退火处理形成N+区；
S2.通过在形成N+区的基底层上进行刻蚀形成沟槽；
S3.在沟槽处的硅层表面进行氧化形成Gate Oxide，在Gate Oxide上进行多晶硅的沉积形成Poly层；
S4.在Poly层上通过各向异性刻蚀形成Poly层作为Gate；
S5.经过离子注入硼，经过推阱处理形成P型掺杂层；
S6.在P型掺杂层上进行表面沉积形成氧化层，通过对接触孔刻蚀，经过离子注入硼，在高温热过程退火处理后形成P+区，并通过金属淀积形成金属层。
本实施例提供的P-layer SG IGBT结构与传统的SG IGBT结构相比，在沟槽底部增加了P型掺杂层，用于保护沟槽栅的底部，从而提升了SG IGBT的击穿电压，并降低了开通损耗。
实施例2
一种改进的SG IGBT结构的制造工艺，包括以下步骤：
S1.在晶圆底层上通过离子注入硼，通过推阱处理形成Pbody区，通过离子注入磷，经过退火处理形成N+区；
S2.通过在形成N+区的基底层上进行刻蚀形成沟槽；
S3.在沟槽处的硅层表面进行氧化形成第一Gate Oxide，在第一Gate Oxide 上进行多晶硅的沉积形成第一Poly层；
S4.在第一Poly层上通过各向异性刻蚀形成Poly层；通过各向同性刻蚀去除裸露的第一Gate Oxide；
S5.在Poly层上进行表面氧化形成第二Gate Oxide，在第二Gate Oxide上进行多晶硅的沉积形成第二Poly层；
S6.在第二Poly层上进行刻蚀形成Poly Gate；
S7.进行表面沉积形成氧化层，通过对接触孔刻蚀，经过离子注入二氟化硼，在高温热过程中退火形成P+区，并通过金属淀积形成金属层。
本实施例提供了SSG(Split Side Gate)IGBT结构与传统的SG IGBT结构相比，在沟槽底部增加了Poly层，形成分栅，用于保护沟槽栅的底部，从而提升了SG IGBT的击穿电压，并降低了开通损耗和栅极-集电极电容。
实施例3
一种改进的SG IGBT结构的制造工艺，包括以下步骤：
S1.在晶圆底层进行刻蚀形成沟槽；
S2.在沟槽处的硅层表面进行氮化硅的沉积，形成SiN层；
S3.在SiN层上通过各向异性刻蚀形成SiN侧墙；
S4.通过热氧化形成厚氧化物层；
S5.通过各向同性刻蚀去除SiN侧墙，然后热氧化形成栅氧层；
S6.在栅氧层上进行多晶硅的沉积形成Poly层；
S7.在Poly层上通过各向异性刻蚀形成Poly Spacer作为栅极；通过各向异性刻蚀去除表面的厚氧化物层，保留Poly栅下的厚氧化物层；
S8.进行表面沉积形成氧化层，通过对接触孔刻蚀，经过离子注入硼，在高温热过程退火处理后形成P+区，并通过金属淀积形成金属层。
本实施例提供的TO(Thick Oxide)SG IGBT结构与传统的SG IGBT结构相比，在沟槽底部增加了厚氧化层保护层，用于保护沟槽栅的底部，从而提升了 SG IGBT的击穿电压，并降低了开通损耗和栅极-集电极电容。

Claims (10)

1.一种改进型SG IGBT的制备方法，其特征在于，包括以下步骤：
S1.通过在晶圆底层上进行刻蚀形成沟槽；
S2.通过在沟槽处的硅层表面进行氧化形成Gate Oxide，或进行氮化硅的沉积，形成SiN层；
S3.在Gate Oxide上进行多晶硅的沉积形成Poly层，或在SiN层上通过各向异性刻蚀形成SiN Spacer；
S4.在Poly层上进行蚀形成Poly层或Poly Spacer；
S5.经过离子注入硼，进行表面沉积形成氧化层，通过对接触孔刻蚀，经过离子注入含硼化合物，在高温热过程退火处理后形成P+区，并通过金属淀积形成金属层。
2.如权利要求1所述的改进型SG IGBT的制备方法，其特征在于，所述S1中在晶圆底层上通过离子注入硼，通过推阱处理形成Pbody区，通过离子注入砷，经过退火处理形成N+区，通过在形成N+区的基底层上进行刻蚀形成沟槽。
3.如权利要求2所述的改进型SG IGBT的制备方法，其特征在于，所述S2中在沟槽处的硅层表面进行氧化形成Gate Oxide，在Gate Oxide上进行多晶硅的沉积形成Poly层。
4.如权利要求1-3任一项所述的改进型SG IGBT的制备方法，其特征在于，所述S4中通过各向异性刻蚀成Poly层或Poly Spacer。
5.如权利要求4所述的改进型SG IGBT的制备方法，其特征在于，所述S5中经过离子注入硼，经过推阱处理形成P型掺杂层，并在P型掺杂层上进行表面沉积形成氧化层，通过对接触孔刻蚀，经过离子注入硼，在高温热过程退火处理后形成P+区，并通过金属淀积形成金属层。
6.如权利要求3所述的改进型SG IGBT的制备方法，其特征在于，所述S2中在沟槽处的硅层表面进行氧化形成第一Gate Oxide；所述S3中在第一GateOxide上进行多晶硅的沉积形成第一Poly层；所述S4中在第一Poly层上通过各向异性刻蚀形成Poly层；并在Poly层上进行表面氧化形成第二Gate Oxide，在第二Gate Oxide上进行多晶硅的沉积形成第二Poly层。
7.如权利要求6所述的改进型SG IGBT的制备方法，其特征在于，所述第二Poly层上进行刻蚀形成Poly Gate。
8.如权利要求7所述的改进型SG IGBT的制备方法，其特征在于，所述形成Poly Gate后进行表面沉积形成氧化层，通过对接触孔刻蚀，经过离子注入二氟化硼，在高温热过程中退火形成P+区，并通过金属淀积形成金属层。
9.如权利要求1所述的改进型SG IGBT的制备方法，其特征在于，所述S3中形成SiN侧墙后通过热氧化形成厚氧化物层，通过各向同性刻蚀去除SiN侧墙，然后热氧化形成栅氧层，在栅氧层上进行多晶硅的沉积形成Poly层。
10.一种如权利要求1-9任一项所述的改进型SG IGBT的制备方法在制备SGIGBT技术领域中进行应用。
CN202210861671.1A 2022-07-20 2022-07-20 一种改进型sg igbt的制备方法及应用 Pending CN115483284A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210861671.1A CN115483284A (zh) 2022-07-20 2022-07-20 一种改进型sg igbt的制备方法及应用

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210861671.1A CN115483284A (zh) 2022-07-20 2022-07-20 一种改进型sg igbt的制备方法及应用

Publications (1)

Publication Number Publication Date
CN115483284A true CN115483284A (zh) 2022-12-16

Family

ID=84422890

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210861671.1A Pending CN115483284A (zh) 2022-07-20 2022-07-20 一种改进型sg igbt的制备方法及应用

Country Status (1)

Country Link
CN (1) CN115483284A (zh)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130285140A1 (en) * 2010-12-10 2013-10-31 Mitsubishi Electric Corporation Semiconductor device and manufacturing method therefor
JP2015162533A (ja) * 2014-02-27 2015-09-07 サンケン電気株式会社 半導体装置
CN105789290A (zh) * 2016-04-26 2016-07-20 电子科技大学 一种沟槽栅igbt器件及其制造方法
CN105789291A (zh) * 2016-04-26 2016-07-20 电子科技大学 一种双分裂沟槽栅电荷存储型igbt及其制造方法
CN105932042A (zh) * 2016-04-26 2016-09-07 电子科技大学 一种双分裂沟槽栅电荷存储型igbt及其制造方法
WO2018033034A1 (en) * 2016-08-17 2018-02-22 The Hong Kong University Of Science And Technology Semiconductor device with hybrid channel configuration
CN108321193A (zh) * 2018-02-05 2018-07-24 电子科技大学 一种沟槽栅电荷存储型igbt及其制作方法
CN113451401A (zh) * 2021-07-22 2021-09-28 青岛佳恩半导体科技有限公司 一种异型槽分离栅igbt结构及其制造方法
CN113838914A (zh) * 2021-09-23 2021-12-24 电子科技大学 具有分离栅结构的ret igbt器件结构及制作方法
CN113871299A (zh) * 2021-09-24 2021-12-31 贵州大学 一种低损耗鳍型发射区igbt器件及其制作方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130285140A1 (en) * 2010-12-10 2013-10-31 Mitsubishi Electric Corporation Semiconductor device and manufacturing method therefor
JP2015162533A (ja) * 2014-02-27 2015-09-07 サンケン電気株式会社 半導体装置
CN105789290A (zh) * 2016-04-26 2016-07-20 电子科技大学 一种沟槽栅igbt器件及其制造方法
CN105789291A (zh) * 2016-04-26 2016-07-20 电子科技大学 一种双分裂沟槽栅电荷存储型igbt及其制造方法
CN105932042A (zh) * 2016-04-26 2016-09-07 电子科技大学 一种双分裂沟槽栅电荷存储型igbt及其制造方法
WO2018033034A1 (en) * 2016-08-17 2018-02-22 The Hong Kong University Of Science And Technology Semiconductor device with hybrid channel configuration
CN108321193A (zh) * 2018-02-05 2018-07-24 电子科技大学 一种沟槽栅电荷存储型igbt及其制作方法
CN113451401A (zh) * 2021-07-22 2021-09-28 青岛佳恩半导体科技有限公司 一种异型槽分离栅igbt结构及其制造方法
CN113838914A (zh) * 2021-09-23 2021-12-24 电子科技大学 具有分离栅结构的ret igbt器件结构及制作方法
CN113871299A (zh) * 2021-09-24 2021-12-31 贵州大学 一种低损耗鳍型发射区igbt器件及其制作方法

Similar Documents

Publication Publication Date Title
US10763351B2 (en) Vertical trench DMOSFET having integrated implants forming enhancement diodes in parallel with the body diode
KR100662692B1 (ko) 반도체 장치 및 그 제조 방법
US4757026A (en) Source drain doping technique
CN101043053B (zh) 具有改善性能的功率半导体器件和方法
US4784965A (en) Source drain doping technique
CN111081759B (zh) 一种增强型碳化硅mosfet器件及其制造方法
CN101138093A (zh) 沟槽型mosfet及其制造方法
KR101268227B1 (ko) 반도체 장치의 제조 방법
CN104769723A (zh) 沟槽栅功率半导体场效应晶体管
CN103035521B (zh) 实现少子存储层沟槽型igbt的工艺方法
JPH1126758A (ja) トレンチ型ｍｏｓ半導体装置およびその製造方法
CN102054864A (zh) Ldmos及其制造方法
US8492221B2 (en) Method for fabricating power semiconductor device with super junction structure
CN101924103A (zh) 沟槽式功率mosfet及其制造方法
CN115483284A (zh) 一种改进型sg igbt的制备方法及应用
CN213816159U (zh) 一种功率半导体器件
CN107342224B (zh) Vdmos器件的制作方法
CN112309853A (zh) 屏蔽栅极沟槽结构的制备方法
CN108054210B (zh) 沟槽型垂直双扩散金属氧化物晶体管及其制作方法
CN213816161U (zh) 一种具有沟槽型栅极的半导体器件
CN216389378U (zh) 一种沟槽型功率器件
CN116313809B (zh) 沟槽型mos场效应晶体管的制备方法和应用
CN112838007B (zh) 一种沟槽栅功率器件及其制备方法
KR100331032B1 (ko) 측벽막을 이용한 트렌치 게이트 전력소자 제조방법
JP2006332231A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20221216

RJ01 Rejection of invention patent application after publication