CN104769723A - 沟槽栅功率半导体场效应晶体管 - Google Patents

沟槽栅功率半导体场效应晶体管 Download PDF

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CN104769723A
CN104769723A CN201480002401.9A CN201480002401A CN104769723A CN 104769723 A CN104769723 A CN 104769723A CN 201480002401 A CN201480002401 A CN 201480002401A CN 104769723 A CN104769723 A CN 104769723A
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structure according
polysilicon
gate
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conductivity type
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CN104769723B (zh
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周贤达
冯淑华
单建安
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Abstract

本发明提供具有重掺杂的多晶硅源区的沟槽栅功率MOSFET(TMOS/UMOS)结构。所述多晶硅源区通过淀积形成，并且沟槽形接触孔用于所述源区处，以便获得小接触电阻和小元胞尺寸。本发明还可以实施于IGBT中。

Description

沟槽栅功率半导体场效应晶体管
技术领域
本发明大体上涉及功率场效应晶体管的结构和制造，并且具体来说涉及沟槽栅功率金属氧化物半导体场效应晶体管(MOSFET)以及沟槽栅绝缘栅双极晶体管(IGBT)。
背景技术
本发明将在n沟道功率FET中说明，但是在以下说明中将理解，本发明同样适用于p沟道功率FET。在本发明说明书中，重掺杂的n型区域标记为n+，并且重掺杂的p型区域标记为p+。这些重掺杂区域通常具有介于1×1018cm-3与1×1021cm-3之间的掺杂浓度。另一方面，轻掺杂的n型区域标记为n-，并且轻掺杂的p型区域标记为p-。这些轻掺杂区域通常具有介于1×1013cm-3与1×1017cm-3之间的掺杂浓度。
低压功率MOSFET已经广泛用于开关模式电源(例如，DC-DC转换器)中。例如，目前先进技术中央处理单元(CPU)需要DC-DC转换器，所述DC-DC转换器同时提供大约10A的高输出电流以及低输出电压。为了在转换器中获得高效率，此处的功率MOSFET应具有极低的导通电阻。低压功率MOSFET的导通电阻的重要组成部分是沟道电阻。因此，沟槽栅结构常用于低压功率MOSFET中，以提供与平面结构相比相对较大的沟道密度。此外，需要努力减小这些沟槽栅功率MOSFET的元胞尺寸，以便增加沟道密度。因此，本发明的目标是提供具有小元胞尺寸以及因此低导通电阻的低压沟槽栅功率MOSFET。此外，小元胞尺寸在沟槽栅IGBT结构中也是合乎需要的，因为所述小元胞尺寸可以在发射极附近引起注入增强并且因此产生减小的开态压降。因此，本发明的另一目标是提供具有低开态压降的沟槽栅IGBT。
除了导通电阻需求之外，沟槽栅功率MOSFET(TMOS)还需要具有高可靠性。例如，由于该器件中的寄生BJT的激活，因此在非箝位感应开关(UIS)期间该器件不应发生故障。因此，本发明的又另一目标是提供具有改进的UIS强度的TMOS。此外，还应防止IGBT中的寄生BJT的激活，以便使该装置实现无闩锁。因此，本发明的又另一目标是提供无闩锁的沟槽栅IGBT。
图1中示出现有技术TMOS结构的横截面。器件的沟道位于p型体区(13)的侧壁表面处，并且在通路状态下n+源区(11)和n--epi(14)由所述沟道连接。器件的导通电阻大部分取决于所述器件的元胞尺寸。实现高沟道密度以及因此小沟道电阻需要小的元胞尺寸。
图2中示出现有技术沟槽栅TMOS结构的横截面[1]。如图中所示，层间电介质(ILD)(32)位于沟槽中的栅电极(21)的顶部，并且栅电极(21)通过ILD(32)与源极(22)隔离。与图1中所示的结构相比，n+源区(11)的宽度可以减小，因为在沟槽栅TMOS中在源极接触孔与栅电极(21)之间不存在横向空间。减小的元胞尺寸会产生与图1中所示的结构相比减小的导通电阻。然而，需要一种复杂的淀积和深蚀刻过程以在器件中形成ILD(32)。
在图1和图2中示出的器件结构中，在这些结构不变的情况下，可以通过使用先进的光刻技术来减小元胞尺寸。然而，那些结构中的减小的元胞尺寸还可以产生n+源区(11)以及源极(22)的减小的接触面积，并且此处的接触电阻将会增加。由于此种限制，即使使用先进的光刻技术，那些器件的导通电阻也无法减小很多。为了缓和接触问题，已提出现有技术埋栅TMOS结构，如图3中所示[2]。然而，在埋栅结构中，接触面积仍然受元胞尺寸的限制，并且接触问题无法被完全解决。
为了解决源极处的接触问题，已提出现有技术沟槽形源极接触孔TMOS结构[3]。图4中示出沟槽形源极接触孔TMOS结构的横截面。在此结构中，n+源区(11)和源极(22)在沟槽形接触孔的侧壁处接触。在源极处的接触面积不受元胞尺寸的限制，并且接触面积仅由n+源区(11)的深度确定，而不是由n+源区(11)的宽度确定。此结构使器件能够用先进的光刻技术制造，而不会增加源极处的接触电阻。然而，所述结构需要深的n+源区(11)以提供大的源极接触面积，但是浅的n+源区(11)通常用于所述结构中以便获得p型体区(13)的大致均匀的掺杂分布。如图中所示，p型体区(13)位于n+源区(11)的下方，并且出于减小沟道电阻的目的，均匀掺杂的p型体区(13)是合乎需要的[4]。p型体区(13)以及n+源区(11)两者通常通过离子注入以及退火形成。在浅的n+源区(11)的情况下，可以通过多次低能离子注入获得p型体区(13)的大致均匀的掺杂分布，因为这些注入的投影射程的标准差相对较小。然而，如果n+源区(11)较深，那么需要高能离子注入来形成p型体区(13)，并且由于所述注入的投影射程的相对较大的标准差，可能难以实现大致均匀的掺杂分布。由于用于所述结构中的浅n+源区(11)，因此与先前在图1、图2和图3中示出的这些结构相比，源极处的接触电阻不会减小很多。
发明内容
因此，本发明的目标是提供具有减小的导通电阻的沟槽栅功率MOSFET(TMOS)结构。
为了实现此目标以及其他目标，本发明提供具有重掺杂的多晶硅源区的TMOS结构。图5中示出器件结构的横截面。如图中所示，多晶硅n+源区(11)的深度(厚度)比常规TMOS的深度(厚度)大得多，所述常规TMOS在n+源区(11)的侧壁处提供较小接触电阻。在形成p型体区(13)之后，多晶硅n+源区(11)可以通过低温淀积形成。因此，p型体区(13)的掺杂分布可以得到良好控制，因为其在硅的表面附近形成。另一方面，与图1中示出的器件的元胞尺寸相比，在器件的源极处的沟槽形接触孔提供减小的元胞尺寸。通过使用沟槽形接触孔，多晶硅n+源区(11)由接触孔的侧壁处的源极(22)接触，并且如果元胞尺寸通过使用更先进的光刻技术进一步减小，那么接触电阻将不会增加。此外，沟槽形接触孔还提供小的寄生n+源区(11)/p型体区(13)/n--epi(14)三极管的基区电阻，这使器件具备更坚固的UIS性能[5]。
此外，本发明还可以实施于沟槽栅IGBT结构中以提供减小的开态压降以及无闩锁特征。
一种沟槽栅功率MOSFET结构，其包括：
在底部处的漏极(23)，
第一导电型的重掺杂衬底(15)，所述重掺杂衬底(15)在所述漏极(23)的顶部上，
第一导电型的轻掺杂外延层(14)，所述轻掺杂外延层(14)在所述重掺杂衬底(15)的顶部上，
第二导电型的体区(13)，所述体区(13)在所述外延层(14)的顶部上，
第二导电型的重掺杂扩散区(12)，所述重掺杂扩散区(12)将所述体区(13)连接到源极(22)，
源极(22)，所述(22)源极位于沟槽形接触孔(42)中并且位于器件的顶部，
第一导电型的重掺杂多晶硅源区(11)，所述重掺杂多晶硅源区(11)在所述体区(13)的顶部上并且在所述沟槽形接触孔(42)的侧壁处由所述源极(22)接触，
栅电介质(31)，所述栅电介质(31)覆盖所述体区(13)的侧壁表面并且在所述源区(11)与所述外延层(14)之间形成沟道，
栅电极(21)，所述栅电极(21)靠近栅沟槽(41)中的所述栅电介质(31)以及
层间电介质(32)，所述层间电介质(32)覆盖所述栅电极(21)的上表面以及所述源区(11)的上表面。
进一步的，其中所述栅电介质(31)是氧化硅或高介电常数电介质，包含但不限于，二氧化铪和氧化铝。
进一步的，其中所述栅电极(21)是多晶硅、金属以及金属硅化物中的至少一者。
进一步的，其中所述ILD(32)是是氧化硅。
进一步的，其中所述体区(13)具有大致均匀的掺杂分布。
进一步的，其中所述源极(22)以及所述漏极(23)是金属或金属硅化物，包含但不限于，铝、铜、钨、钛硅化物、钴硅化物以及镍硅化物。
一种沟槽栅IGBT结构，其包括：
在底部处的集电极(25)，
第二导电型的重掺杂集电区(17)，所述重掺杂集电区(17)在所述集电极(25)的顶部上，
第一导电型的缓冲区(16)，所述缓冲区(16)在所述集电区(17)的顶部上，
第一导电型的轻掺杂漂移区(14)，所述轻掺杂漂移区(14)在所述缓冲区(16)的顶部上，
第二导电型的体区(13)，所述体区(13)在所述漂移区(14)的顶部上，
第二导电型的重掺杂扩散区(12)，所述重掺杂扩散区(12)将所述体区(13)连接到发射极(24)，
发射极(24)，所述发射极(24)位于沟槽形接触孔(42)中并且位于器件的顶部，
第一导电型的重掺杂多晶硅发射区(11)，所述重掺杂多晶硅发射区(11)在所述体区(13)的顶部上并且在所述沟槽形接触孔(42)的侧壁处由所述发射极(24)接触，
栅电介质(31)，所述栅电介质(31)覆盖所述体区(13)的侧壁表面并且在所述发射区(11)与所述漂移区(14)之间形成沟道，
栅电极(21)，所述栅电极(21)靠近栅沟槽(41)中的所述栅电介质(31)以及
层间电介质(32)，所述层间电介质(32)覆盖所述栅电极(21)的上表面以及所述发射区(11)的上表面。
进一步的，其中所述发射极(24)以及所述集电极(25)是金属或金属硅化物，包含但不限于，铝、铜、钨、钛硅化物、钴硅化物以及镍硅化物。
进一步的，其中所述栅电介质(31)是氧化硅或高介电常数电介质，包含但不限于，二氧化铪和氧化铝。
进一步的，其中所述栅电极(21)是多晶硅、金属以及金属硅化物中的至少一者。
进一步的，其中所述ILD(32)是是氧化硅。
进一步的，其中所述体区(13)具有大致均匀的掺杂分布。
一种制造沟槽栅功率MOSFET结构的方法，其包括
以外延晶片开始，其中第一导电型的轻掺杂外延层(14)在第一导电型的重掺杂衬底(15)的顶部上，
在所述外延层(14)的顶部上形成第二导电型的体区(13)，
在所述体区(13)的顶部上形成第一导电型的重掺杂多晶硅源区(11)，
通过图案化所述多晶硅源区(11)和所述体区(13)形成栅沟槽(41)，
在所述栅沟槽(41)中并且在所述多晶硅源区(11)的上表面处形成栅电介质(31)，
通过淀积以及深蚀刻形成栅电极(21)，
将ILD(32)淀积在所述栅电极(21)的顶部上以及所述源区(11)的表面上，
通过图案化所述ILD(32)以及所述源区(11)形成沟槽形接触孔(42)，
通过离子注入以及退火在所述接触孔(42)的底部处形成第二导电型的重掺杂扩散(12)，以及
在晶片正面形成源极(22)并且在晶片背面形成漏极(23)。
进一步的，其中所述体区(13)通过单次或多次离子注入且随后退火而形成。
进一步的，其中所述体区(13)通过外延生长形成。16.根据权利要求13所述的制造沟槽栅功率MOSFET结构的方法，其中所述多晶硅源区(11)通过化学气相淀积形成。
进一步的，其中所述多晶硅源区(11)通过淀积非晶硅且随后退火以将所述非晶硅转变成多晶硅而形成。18.根据权利要求13所述的制造沟槽栅功率MOSFET结构的方法，其中所述多晶硅源区(11)通过淀积非晶硅并且将所述非晶硅在形成所述栅电介质(31)的过程中转变成多晶硅而形成。
进一步的，其中所述沟槽形接触孔(42)通过光刻且随后蚀刻形成。
进一步的，其中所述栅电介质(31)是通过淀积形成的高介电常数电介质。
进一步的，其中所述沟槽形接触孔(42)通过光刻且随后蚀刻形成。
进一步的，其中所述的蚀刻为干式蚀刻，包含但不限于深反应离子刻蚀。
进一步的，其中所述源极(22)通过淀积形成，包含但不限于，溅射、蒸发以及电镀。
进一步的，其中所述栅电极(21)通过淀积多晶硅且随后蚀刻而形成。
一种制造IGBT结构的方法，其包括
以第一导电型的轻掺杂的衬底晶片(14)开始，
在所述衬底(14)的顶部上形成第二导电型的体区(13)，
在所述体区(13)的顶部上形成第一导电型的重掺杂多晶硅发射区(11)，
通过图案化所述多晶硅发射区(11)和所述体区(13)形成栅沟槽(41)，
在所述栅沟槽(41)中并且在所述多晶硅发射区(11)的上表面处形成栅电介质(31)，
通过淀积以及之后的蚀刻形成栅电极(21)，
将ILD(32)淀积在所述栅电极(21)的顶部上以及所述发射区(11)的表面上，
通过图案化所述ILD(32)以及所述发射区(11)形成沟槽形接触孔(42)，
通过离子注入以及退火在所述接触孔(42)的底部处形成第二导电型的重掺杂扩散(12)，
在晶片正面形成发射极(24)，
在晶片背面使所述衬底晶片(14)变薄，
在所述晶片背面形成第一导电型的缓冲区(16)以及第二导电型的重掺杂集电区(17)，以及
在所述晶片背面处形成集电极(25)。
进一步的，其中所述体区(13)通过单次或多次离子注入且随后退火而形成。
进一步的，其中所述体区(13)通过外延生长形成。
进一步的，其中所述多晶硅发射区(11)通过化学气相淀积形成。
进一步的，其中所述多晶硅发射区(11)通过淀积非晶硅且随后退火以将所述非晶硅转变成多晶硅而形成。30.根据权利要求25所述的制造IGBT结构的方法，其中所述多晶硅发射区(11)通过淀积非晶硅并且将所述非晶硅在形成所述栅电介质(31)的过程中转变成多晶硅而形成。
进一步的，其中所述沟槽形接触孔(42)通过光刻且随后蚀刻形成。
进一步的，其中所述栅电介质(31)是通过淀积形成的高介电常数电介质。
进一步的，其中所述沟槽形接触孔(42)通过光刻且随后蚀刻形成。
更进一步的，其中所述的蚀刻为干式蚀刻，包含但不限于深反应离子刻蚀。
进一步的，其中所述发射极(24)通过淀积形成，包含但不限于，溅射、蒸发以及电镀。
进一步的，其中所述栅电极(21)通过淀积多晶硅且随后蚀刻而形成。
一种制造IGBT结构的方法，其包括
以第一导电型的轻掺杂的衬底晶片(14)开始，
在所述衬底(14)的顶部上形成第二导电型的体区(13)，
在所述体区(13)的顶部上形成第一导电型的重掺杂多晶硅发射区(11)，
通过图案化所述多晶硅发射区(11)和所述体区(13)形成栅沟槽(41)，
在所述栅沟槽(41)中并且在所述多晶硅发射区(11)的上表面处形成栅电介质(31)，
通过淀积以及之后的蚀刻形成栅电极(21)，
将ILD(32)淀积在所述栅电极(21)的顶部上以及所述发射区(11)的表面上，
在晶片背面使所述衬底晶片(14)变薄，
在所述晶片背面形成第一导电型的缓冲区(16)以及第二导电型的重掺杂集电区(17)，
通过图案化所述ILD(32)以及所述发射区(11)形成沟槽形接触孔(42)，
通过离子注入以及退火在所述接触孔(42)的底部处形成第二导电型的重掺杂扩散(12)，以及
在晶片正面形成发射极(24)并且在所述晶片背面形成集电极(23)。
进一步的，其中所述体区(13)通过单次或多次离子注入且随后退火而形成。
进一步的，其中所述体区(13)通过外延生长形成。
进一步的，其中所述多晶硅发射区(11)通过化学气相淀积形成。
进一步的，其中所述多晶硅发射区(11)通过淀积非晶硅且随后退火以将所述非晶硅转变成多晶硅而形成。
进一步的，其中所述多晶硅发射区(11)通过淀积非晶硅并且将所述非晶硅在形成所述栅电介质(31)的过程中转变成多晶硅而形成。
进一步的，其中所述栅电介质(31)是通过氧化或淀积形成的氧化硅。
进一步的，其中所述栅电介质(31)是通过淀积形成的高介电常数电介质。
进一步的，其中所述沟槽形接触孔(42)通过光刻且随后蚀刻形成。
更进一步的，其中所述的蚀刻为干式蚀刻，包含但不限于深反应离子刻蚀。
进一步的，其中所述发射极(24)通过淀积形成，包含但不限于，溅射、蒸发以及电镀。
进一步的，其中所述栅电极(21)通过淀积多晶硅且随后蚀刻而形成。
附图说明
图1是现有技术TMOS结构的截面图。
图2是现有技术沟槽栅TMOS结构的截面图。
图3是现有技术埋栅TMOS结构的截面图。
图4是具有沟槽形源极接触孔的现有技术TMOS结构的截面图。
图5是实施于TMOS结构中的本发明的截面图。
图6是实施于沟槽栅IGBT结构中的本发明的截面图。
图7A至图7G示出如先前在图5中示出的TMOS的制造方法。
图8A至图8I示出如先前在图6中示出的沟槽栅IGBT的制造方法。
图9A至图9H示出如先前在图6中示出的沟槽栅IGBT的另一制造方法。
具体实施方式
图1是现有技术TMOS结构的截面图。在器件中，约一半的n+源区(11)由层间电介质(ILD)(32)覆盖，并且剩余的n+源区(11)由源极(22)接触。源极(22)通过ILD(32)与栅电极(21)隔离。
图2是现有技术沟槽栅TMOS结构的截面图。在器件中，所有ILD(32)位于沟槽中，并且n+源区(11)的整个上表面由源极(22)接触。
图3是现有技术埋栅TMOS结构的截面图。在器件中，所有ILD(32)位于沟槽中，并且n+源区(11)的整个上表面由源极(22)接触。此外，部分n+源区(11)位于ILD(32)的顶部上，并且该部分n+源区(11)是多晶硅。
图4是具有沟槽形源极接触孔的现有技术TMOS结构的截面图。在器件中，n+源区(11)在沟槽形接触孔的侧壁处由源极(22)接触。
图5是实施于沟槽栅功率MOSFET结构中的本发明的截面图。沟槽栅功率MOSFET结构包括在底部处的漏极(23)；在漏极(23)的顶部上的n+衬底(15)；在n+衬底(15)的顶部上的n--epi(14)；在n--epi(14)的顶部上的p型体区(13)；p+扩散(12)，所述p+扩散将p型体区(13)连接到源极(22)；源极(22)，所述源极位于沟槽形接触孔(42)中并且位于器件的顶部；多晶硅n+源区(11)，所述多晶硅n+源区位于p型体区(13)的顶部上并且由接触孔(42)的侧壁处的源极(22)接触；栅电介质(31)，所述栅电介质覆盖p型体区(13)的侧壁表面并且在n+源区(11)与n--epi(14)之间形成沟道；栅电极(21)，所述栅电极靠近栅沟槽(41)中的栅电介质(31)；以及层间电介质(ILD)(32)，所述层间电介质覆盖栅电极(21)的上表面以及n+源区(11)的上表面两者。漏极(23)以及源极(22)两者应具有低电阻率，并且它们通常是金属或金属硅化物，包含但不限于，铝、铜、钨、钛硅化物、钴硅化物以及镍硅化物。栅电介质(31)通常是氧化硅。然而，为了将制造的热过程最小化，高介电常数电介质(例如，二氧化铪以及氧化铝)还可以用作栅电介质(31)。栅电极(21)通常是n+多晶硅，并且使用多晶硅以便使器件适合于高温制造过程。例如，在制造过程中，p+扩散(12)在形成栅电极(21)之后形成，并且该步骤通常需要高温退火(例如，950℃)。然而，在高温过程之后，多晶硅可以部分或全部转变成金属或金属硅化物，以便获得小的栅电阻。ILD(32)可以是任何类型的电介质，并且其通常是氧化硅。在本发明的优选实施例中，p型体区(13)具有大致均匀的掺杂分布，以便获得器件的小导通电阻。
图6是实施于沟槽栅IGBT结构中的本发明的截面图。所述器件具有与先前在图5中示出的TMOS的结构类似的结构。然而，IGBT具有不同的晶片背面结构。如图中所示，在集电极(25)的顶部上存在p+集电区(17)，并且n缓冲区(16)在p+集电区(17)的顶部上。在n缓冲区(16)上方的这些部分与图5中的n+衬底(15)上方的部分相同，但是不同名称用于这些部分。IGBT中的发射极(24)与TMOS中的源极(22)相同。IGBT中的n+发射区(11)与TMOS中的n+源区(11)相同。IGBT中的n-漂移区(14)与TMOS中的n--epi(14)相同。
图7A至图7G示出如先前在图5中示出的TMOS的制造方法。制造过程包括(001)以具有在n+衬底(15)的顶部上的n--epi(14)的外延晶片开始；(002)在n--epi(14)的顶部上形成p型体区(13)；(003)在p型体区(13)的顶部上形成多晶硅n+源区(11)；(004)通过图案化n+源区(11)和p型体区(13)形成栅沟槽(41)；(005)在栅沟槽(41)中以及在n+源区(11)的上表面处形成栅电介质(31)；(006)通过淀积以及深蚀刻形成栅电极(21)；(007)将ILD(32)淀积到栅电极(21)的顶部上以及n+源区(11)的表面上；(008)通过图案化ILD(32)以及n+源区(11)形成沟槽形接触孔(42)；(009)通过离子注入以及退火在接触孔(42)的底部处形成p+扩散(12)；以及(010)在晶片正面形成源极(22)并且在晶片背面形成漏极(23)。
图7A示出p型体区(13)的形成。在本发明的优选实施例中，p型体区(13)具有大致均匀的掺杂分布，以便获得器件的小导通电阻。在本发明的实施例中，p型体区(13)通过离子注入以及退火形成。在本发明的另一实施例中，p型体区(13)通过多次离子注入以及退火形成，以便使掺杂分布更接近均匀分布。在本发明的又另一实施例中，p型体区(13)通过p型外延生长形成于n--epi(14)的顶部上，以便使掺杂分布更接近均匀分布。
图7B示出多晶硅n+源区(11)的形成。在本发明的实施例中，多晶硅n+源区(11)通过化学气相淀积(CVD)形成。例如，n+源区(11)可以通过将掺磷多晶硅淀积在p型体区(13)的顶部上形成。在本发明的另一实施例中，多晶硅n+源区(11)通过淀积非晶硅且随后退火以将非晶硅转变成多晶硅而形成。退火温度通常高于600℃并且低于1100℃。例如，非晶硅是掺磷的，并且其通过CVD或溅射淀积。在本发明的又另一实施例中，多晶硅n+源区(11)通过在形成栅电介质(31)的过程中淀积非晶硅并且将非晶硅转变成多晶硅而形成。例如，在栅电介质(31)的氧化过程期间，非晶硅可以被转变成多晶硅。氧化硅的氧化温度(例如，950℃)足以将非晶硅转变成多晶硅。此外，可以在非晶硅表面上获得相对较厚的氧化硅，这会产生减小的栅源电容。
图7C示出栅沟槽(41)的形成。栅沟槽(41)通过图案化n+源区(11)以及p型体区(13)形成。例如，栅沟槽(41)可以通过光刻且随后干式蚀刻而形成。
图7D示出栅电介质(31)和栅电极(21)的形成。在本发明的实施例中，栅电介质(31)是通过氧化或淀积形成的氧化硅。热氧化物具有高质量，但是经淀积的氧化物具有低的热过程。在本发明的另一实施例中，栅电介质(31)是通过淀积形成的高介电常数电介质，并且所述过程的热过程可以保持为低。栅电极(21)通常是重掺杂的多晶硅(例如，掺磷多晶硅)，并且栅电极(21)通过淀积且随后深蚀刻而形成。在深蚀刻多晶硅之后，在n+源区(11)上的栅电介质(31)可以保留或部分保留。然而，这对以下步骤来说没有区别，因为栅电介质(31)具有与ILD(32)基本上相同的电气特性。即使在深蚀刻多晶硅之后一些栅电介质(31)遗留在n+源区(11)上，栅电介质(31)仍可以在沟槽形接触孔(42)的蚀刻过程中与ILD(32)一起进行图案化，并且引起器件的可忽略的电气性能变化。此外，或者，在形成p+扩散(12)之后，栅的多晶硅还可以完全地或部分地由金属或金属硅化物替换，以便获得小的栅电阻。
图7E示出ILD(32)的形成。ILD(32)通常是氧化硅。例如，ILD(32)是通过CVD淀积的氧化硅。然而，ILD(32)可以是任何类型的电介质。例如，可以使用低介电常数电介质以便减小寄生的栅源电容。
图7F示出沟槽形接触孔(42)的形成。接触孔(42)是通过图案化ILD(32)以及n+源区(11)形成的沟槽。通常图案化包含光刻且随后蚀刻。在本发明的实施例中，用于接触孔(42)的蚀刻是干式蚀刻。例如，目前先进技术深反应离子蚀刻(DRIE)可以以约1：20的宽度：高度比率获得沟槽形接触孔(42)。通过使用DRIE，即使在元胞尺寸显著减小的情况下，源极的接触电阻也可以保持为低。在形成接触孔(42)之后，p+扩散(12)通过离子注入以及退火形成。例如，离子注入可以通过将ILD(32)用作硬掩模而执行。又例如，在光刻以及蚀刻接触孔(42)之后，光刻胶可以被保持作为用于离子注入的掩模，并且所述光刻胶在离子注入之后移除。
图7G示出在晶片正面源极(22)的形成以及在晶片背面漏极(23)的形成。在本发明的实施例中，源极(22)通过淀积形成。例如，源极(22)可以通过常用的溅射或蒸发形成。又例如，源极(22)还可以通过电镀形成，以便以高宽高比填充沟槽形接触孔(42)。另一方面，漏极(23)通常通过溅射或蒸发形成。
图8A至图8I示出如先前在图6中示出的沟槽栅IGBT的制造方法。制造过程包括(001)以n-衬底晶片(14)开始；(002)在n-衬底(14)的顶部上形成p型体区(13)；(003)在p型体区(13)的顶部上形成多晶硅n+发射区(11)；(004)通过图案化n+发射区(11)和p型体区(13)形成栅沟槽(41)；(005)在栅沟槽(41)中并且在n+发射区(11)的上表面处形成栅电介质(31)；(006)通过淀积以及深蚀刻形成栅电极(21)；(007)将ILD(32)淀积在栅电极(21)的顶部上以及n+发射区(11)的表面上；(008)通过图案化ILD(32)和n+发射区(11)形成沟槽形接触孔(42)；(009)通过注入以及退火在接触孔(42)的底部处形成p+扩散(12)；(010)在晶片正面形成发射极电极(24)；(011)在晶片背面使n-衬底晶片(14)变薄；(012)在晶片背面形成n缓冲区(16)和p+集电区(17)；以及(013)在晶片背面形成集电极(25)。用于TMOS的制造过程中的相同技术也适用于IGBT的制造过程。
从图8A至图8G示出的过程步骤类似于功率MOSFET的过程步骤，除了代替外延晶片使用n-衬底晶片(14)之外。
图8H示出在晶片背面处n缓冲区(16)和p+集电区(17)的形成。在形成之前，在晶片背面处使它们变薄，以将衬底晶片(14)的厚度减小至目标值。例如，600V IGBT的晶片厚度约为60μm。n缓冲区(16)和p+集电区(17)通常通过离子注入以及退火形成。由于在晶片正面处的金属，因此退火通常以低温(例如，480℃)进行。
图8I示出集电极(25)的形成。集电极(25)通常通过溅射或蒸发形成。
图9A至图9H示出如先前在图6中示出的沟槽栅IGBT的另一制造方法。制造过程包括(001)以n-衬底晶片(14)开始；(002)在n-衬底(14)的顶部上形成p型体区(13)；(003)在p型体区(13)的顶部上形成多晶硅n+发射区(11)；(004)通过图案化n+发射区(11)和p型体区(13)形成栅沟槽(41)；(005)在栅沟槽(41)中并且在n+发射区(11)的上表面处形成栅电介质(31)；(006)通过淀积以及深蚀刻形成栅电极(21)；(007)将ILD(32)淀积在栅电极(21)的顶部上以及n+发射区(11)的表面上；(008)在晶片背面使n-衬底晶片(14)变细；(009)在晶片背面形成n缓冲区(16)和p+集电区(17)；(010)通过图案化ILD(32)和n+发射区(11)形成沟槽形接触孔(42)；(011)通过注入以及退火在接触孔(42)的底部处形成p+扩散(12)；(012)在晶片正面形成发射极电极(24)并且在晶片背面形成集电极(23)。用于TMOS的制造过程中的相同技术也适用于IGBT的制造过程。
从图9A至图9E示出的过程步骤类似于功率MOSFET的过程步骤，除了代替外延晶片使用n-衬底晶片(14)之外。
图9F示出在晶片背面处n缓冲区(16)和p+集电区(17)的形成。在形成之前，在晶片背面处使它们变薄，以将衬底晶片(14)的厚度减小至目标值。例如，600V IGBT的晶片厚度约为60μm。n缓冲区(16)和p+集电区(17)通常通过离子注入以及退火形成。由于在此步骤处晶片上不存在金属，因此可以在高温(例如，1050℃)下对n缓冲区(16)和p+集电区(17)执行退火，并且几乎此处所有的杂质都会被激活。
图9G示出沟槽形接触孔(42)和p+扩散(12)的形成。此步骤类似于TMOS的步骤。然而，在此步骤处需要薄晶片处理能力，因为晶片已变薄。
图9H示出发射极(24)和集电极(25)的形成。此步骤类似于TMOS的源极(22)和漏极(23)的形成。

Claims (45)

1.一种沟槽栅功率MOSFET结构，其包括：
在底部处的漏极(23)，
第一导电型的重掺杂衬底(15)，所述重掺杂衬底(15)在所述漏极(23)的顶部上，
第一导电型的轻掺杂外延层(14)，所述轻掺杂外延层(14)在所述重掺杂衬底(15)的顶部上，
第二导电型的体区(13)，所述体区(13)在所述外延层(14)的顶部上，
第二导电型的重掺杂扩散区(12)，所述重掺杂扩散区(12)将所述体区(13)连接到源极(22)，
源极(22)，所述(22)源极位于沟槽形接触孔(42)中并且位于器件的顶部，第一导电型的重掺杂多晶硅源区(11)，所述重掺杂多晶硅源区(11)在所述体区(13)的顶部上并且在所述沟槽形接触孔(42)的侧壁处由所述源极(22)接触，
栅电介质(31)，所述栅电介质(31)覆盖所述体区(13)的侧壁表面并且在所述源区(11)与所述外延层(14)之间形成沟道，
栅电极(21)，所述栅电极(21)靠近栅沟槽(41)中的所述栅电介质(31)以及
层间电介质(32)，所述层间电介质(32)覆盖所述栅电极(21)的上表面以及所述源区(11)的上表面。
2.根据权利要求1所述的沟槽栅功率MOSFET结构，其中所述栅电介质(31)是氧化硅或高介电常数电介质，包含但不限于，二氧化铪和氧化铝。
3.根据权利要求1所述的沟槽栅功率MOSFET结构，其中所述栅电极(21)是多晶硅、金属以及金属硅化物中的至少一者。
4.根据权利要求1所述的沟槽栅功率MOSFET结构，其中所述ILD(32)是是氧化硅。
5.根据权利要求1所述的沟槽栅功率MOSFET结构，其中所述体区(13)具有大致均匀的掺杂分布。
6.根据权利要求1所述的沟槽栅功率MOSFET结构，其中所述源极(22)以及所述漏极(23)是金属或金属硅化物，包含但不限于，铝、铜、钨、钛硅化物、钴硅化物以及镍硅化物。
7.一种沟槽栅IGBT结构，其包括：
在底部处的集电极(25)，
第二导电型的重掺杂集电区(17)，所述重掺杂集电区(17)在所述集电极(25)的顶部上，
第一导电型的缓冲区(16)，所述缓冲区(16)在所述集电区(17)的顶部上，第一导电型的轻掺杂漂移区(14)，所述轻掺杂漂移区(14)在所述缓冲区(16)的顶部上，
第二导电型的体区(13)，所述体区(13)在所述漂移区(14)的顶部上，
第二导电型的重掺杂扩散区(12)，所述重掺杂扩散区(12)将所述体区(13)连接到发射极(24)，
发射极(24)，所述发射极(24)位于沟槽形接触孔(42)中并且位于器件的顶部，
第一导电型的重掺杂多晶硅发射区(11)，所述重掺杂多晶硅发射区(11)在所述体区(13)的顶部上并且在所述沟槽形接触孔(42)的侧壁处由所述发射极(24)接触，
栅电介质(31)，所述栅电介质(31)覆盖所述体区(13)的侧壁表面并且在所述发射区(11)与所述漂移区(14)之间形成沟道，
栅电极(21)，所述栅电极(21)靠近栅沟槽(41)中的所述栅电介质(31)以及
层间电介质(32)，所述层间电介质(32)覆盖所述栅电极(21)的上表面以及所述发射区(11)的上表面。
8.根据权利要求7所述的沟槽栅IGBT结构，其中所述发射极(24)以及所述集电极(25)是金属或金属硅化物，包含但不限于，铝、铜、钨、钛硅化物、钴硅化物以及镍硅化物。
9.根据权利要求或7所述的沟槽栅IGBT结构，其中所述栅电介质(31)是氧化硅或高介电常数电介质，包含但不限于，二氧化铪和氧化铝。
10.根据权利要求7所述的沟槽栅IGBT结构，其中所述栅电极(21)是多晶硅、金属以及金属硅化物中的至少一者。
11.根据权利要求7所述的沟槽栅IGBT结构，其中所述ILD(32)是是氧化硅。
12.根据权利要求7所述的沟槽栅IGBT结构，其中所述体区(13)具有大致均匀的掺杂分布。
13.一种制造沟槽栅功率MOSFET结构的方法，其包括
以外延晶片开始，其中第一导电型的轻掺杂外延层(14)在第一导电型的重掺杂衬底(15)的顶部上，
在所述外延层(14)的顶部上形成第二导电型的体区(13)，
在所述体区(13)的顶部上形成第一导电型的重掺杂多晶硅源区(11)，
通过图案化所述多晶硅源区(11)和所述体区(13)形成栅沟槽(41)，
在所述栅沟槽(41)中并且在所述多晶硅源区(11)的上表面处形成栅电介质(31)，
通过淀积以及深蚀刻形成栅电极(21)，
将ILD(32)淀积在所述栅电极(21)的顶部上以及所述源区(11)的表面上，通过图案化所述ILD(32)以及所述源区(11)形成沟槽形接触孔(42)，
通过离子注入以及退火在所述接触孔(42)的底部处形成第二导电型的重掺杂扩散(12)，以及
在晶片正面形成源极(22)并且在晶片背面形成漏极(23)。
14.根据权利要求13所述的制造沟槽栅功率MOSFET结构的方法，其中所述体区(13)通过单次或多次离子注入且随后退火而形成。
15.根据权利要求13所述的制造沟槽栅功率MOSFET结构的方法，其中所述体区(13)通过外延生长形成。16.根据权利要求13所述的制造沟槽栅功率MOSFET结构的方法，其中所述多晶硅源区(11)通过化学气相淀积形成。
16.根据权利要求13所述的制造沟槽栅功率MOSFET结构的方法，其中所述多晶硅源区(11)通过淀积非晶硅且随后退火以将所述非晶硅转变成多晶硅而形成。18.根据权利要求13所述的制造沟槽栅功率MOSFET结构的方法，其中所述多晶硅源区(11)通过淀积非晶硅并且将所述非晶硅在形成所述栅电介质(31)的过程中转变成多晶硅而形成。
17.根据权利要求13所述的制造沟槽栅功率MOSFET结构的方法，其中所述沟槽形接触孔(42)通过光刻且随后蚀刻形成。
18.根据权利要求13所述的制造沟槽栅功率MOSFET结构的方法，其中所述栅电介质(31)是通过淀积形成的高介电常数电介质。
19.根据权利要求13所述的制造沟槽栅功率MOSFET结构的方法，其中所述沟槽形接触孔(42)通过光刻且随后蚀刻形成。
20.根据权利要求21所述的制造沟槽栅功率MOSFET结构的方法，其中所述的蚀刻为干式蚀刻，包含但不限于深反应离子刻蚀。
21.根据权利要求13所述的制造沟槽栅功率MOSFET结构的方法，其中所述源极(22)通过淀积形成，包含但不限于，溅射、蒸发以及电镀。
22.根据权利要求13所述的制造沟槽栅功率MOSFET结构的方法，其中所述栅电极(21)通过淀积多晶硅且随后蚀刻而形成。
23.一种制造IGBT结构的方法，其包括
以第一导电型的轻掺杂的衬底晶片(14)开始，
在所述衬底(14)的顶部上形成第二导电型的体区(13)，
在所述体区(13)的顶部上形成第一导电型的重掺杂多晶硅发射区(11)，
通过图案化所述多晶硅发射区(11)和所述体区(13)形成栅沟槽(41)，
在所述栅沟槽(41)中并且在所述多晶硅发射区(11)的上表面处形成栅电介质(31)，
通过淀积以及之后的蚀刻形成栅电极(21)，
将ILD(32)淀积在所述栅电极(21)的顶部上以及所述发射区(11)的表面上，通过图案化所述ILD(32)以及所述发射区(11)形成沟槽形接触孔(42)，
通过离子注入以及退火在所述接触孔(42)的底部处形成第二导电型的重掺杂扩散(12)，
在晶片正面形成发射极(24)，
在晶片背面使所述衬底晶片(14)变薄，
在所述晶片背面形成第一导电型的缓冲区(16)以及第二导电型的重掺杂集电区(17)，以及
在所述晶片背面处形成集电极(25)。
24.根据权利要求25所述的制造IGBT结构的方法，其中所述体区(13)通过单次或多次离子注入且随后退火而形成。
25.根据权利要求25所述的制造IGBT结构的方法，其中所述体区(13)通过外延生长形成。
26.根据权利要求25所述的制造IGBT结构的方法，其中所述多晶硅发射区(11)通过化学气相淀积形成。
27.根据权利要求25所述的制造IGBT结构的方法，其中所述多晶硅发射区(11)通过淀积非晶硅且随后退火以将所述非晶硅转变成多晶硅而形成。30.根据权利要求25所述的制造IGBT结构的方法，其中所述多晶硅发射区(11)通过淀积非晶硅并且将所述非晶硅在形成所述栅电介质(31)的过程中转变成多晶硅而形成。
28.根据权利要求25所述的制造IGBT结构的方法，其中所述沟槽形接触孔(42)通过光刻且随后蚀刻形成。
29.根据权利要求25所述的制造IGBT结构的方法，其中所述栅电介质(31)是通过淀积形成的高介电常数电介质。
30.根据权利要求25所述的制造IGBT结构的方法，其中所述沟槽形接触孔(42)通过光刻且随后蚀刻形成。
31.根据权利要求33所述的制造IGBT结构的方法，其中所述的蚀刻为干式蚀刻，包含但不限于深反应离子刻蚀。
32.根据权利要求25所述的制造IGBT结构的方法，其中所述发射极(24)通过淀积形成，包含但不限于，溅射、蒸发以及电镀。
33.根据权利要求25所述的制造IGBT结构的方法，其中所述栅电极(21)通过淀积多晶硅且随后蚀刻而形成。
34.一种制造IGBT结构的方法，其包括
以第一导电型的轻掺杂的衬底晶片(14)开始，
在所述衬底(14)的顶部上形成第二导电型的体区(13)，
在所述体区(13)的顶部上形成第一导电型的重掺杂多晶硅发射区(11)，
通过图案化所述多晶硅发射区(11)和所述体区(13)形成栅沟槽(41)，
在所述栅沟槽(41)中并且在所述多晶硅发射区(11)的上表面处形成栅电介质(31)，
通过淀积以及之后的蚀刻形成栅电极(21)，
将ILD(32)淀积在所述栅电极(21)的顶部上以及所述发射区(11)的表面上，在晶片背面使所述衬底晶片(14)变薄，
在所述晶片背面形成第一导电型的缓冲区(16)以及第二导电型的重掺杂集电区(17)，
通过图案化所述ILD(32)以及所述发射区(11)形成沟槽形接触孔(42)，
通过离子注入以及退火在所述接触孔(42)的底部处形成第二导电型的重掺杂扩散(12)，以及
在晶片正面形成发射极(24)并且在所述晶片背面形成集电极(23)。
35.根据权利要求37所述的制造IGBT结构的方法，其中所述体区(13)通过单次或多次离子注入且随后退火而形成。
36.根据权利要求37所述的制造IGBT结构的方法，其中所述体区(13)通过外延生长形成。
37.根据权利要求37所述的制造IGBT结构的方法，其中所述多晶硅发射区(11)通过化学气相淀积形成。
38.根据权利要求37所述的制造IGBT结构的方法，其中所述多晶硅发射区(11)通过淀积非晶硅且随后退火以将所述非晶硅转变成多晶硅而形成。
39.根据权利要求37所述的制造IGBT结构的方法，其中所述多晶硅发射区(11)通过淀积非晶硅并且将所述非晶硅在形成所述栅电介质(31)的过程中转变成多晶硅而形成。
40.根据权利要求37所述的制造IGBT结构的方法，其中所述栅电介质(31)是通过氧化或淀积形成的氧化硅。
41.根据权利要求37所述的制造IGBT结构的方法，其中所述栅电介质(31)是通过淀积形成的高介电常数电介质。
42.根据权利要求37所述的制造IGBT结构的方法，其中所述沟槽形接触孔(42)通过光刻且随后蚀刻形成。
43.根据权利要求45所述的制造IGBT结构的方法，其中所述的蚀刻为干式蚀刻，包含但不限于深反应离子刻蚀。
44.根据权利要求37所述的制造IGBT结构的方法，其中所述发射极(24)通过淀积形成，包含但不限于，溅射、蒸发以及电镀。
45.根据权利要求37所述的制造IGBT结构的方法，其中所述栅电极(21)通过淀积多晶硅且随后蚀刻而形成。
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