CN110767752A - 一种新型结构的底部沟槽栅极GaN-MOSFET器件及其制备方法 - Google Patents
一种新型结构的底部沟槽栅极GaN-MOSFET器件及其制备方法 Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 6
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 24
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 24
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 24
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 229910020776 SixNy Inorganic materials 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 229910002601 GaN Inorganic materials 0.000 claims description 104
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 82
- 238000000034 method Methods 0.000 claims description 18
- VSCWAEJMTAWNJL-UHFFFAOYSA-K aluminium trichloride Chemical compound Cl[Al](Cl)Cl VSCWAEJMTAWNJL-UHFFFAOYSA-K 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000010894 electron beam technology Methods 0.000 claims description 5
- 238000000407 epitaxy Methods 0.000 claims description 5
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 150000002902 organometallic compounds Chemical group 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 238000007740 vapor deposition Methods 0.000 claims description 4
- MHYQBXJRURFKIN-UHFFFAOYSA-N C1(C=CC=C1)[Mg] Chemical compound C1(C=CC=C1)[Mg] MHYQBXJRURFKIN-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 3
- 239000011777 magnesium Substances 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 238000005245 sintering Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 13
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 230000005684 electric field Effects 0.000 abstract description 3
- 238000005265 energy consumption Methods 0.000 abstract description 2
- 239000006185 dispersion Substances 0.000 abstract 1
- 239000000463 material Substances 0.000 description 13
- 230000005669 field effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- -1 InP compound Chemical class 0.000 description 1
- 229910003910 SiCl4 Inorganic materials 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical group 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052984 zinc sulfide Inorganic materials 0.000 description 1
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Abstract
一种新型结构的底部沟槽栅极GaN‑MOSFET器件及其制备方法涉及高功率开关半导体器件和制造该半导体器件的技术领域，该器件从下至上依次为衬底、n型GaN外延层、P型GaN外延层和在P型GaN外延层中离子注入一层n型GaN，在器件中形成底部沟槽结构，侧壁为SixNy/SiO2结构，沟槽深度穿过P型GaN外延层，到达n型GaN外延层，在沟槽结构底部生长一层P型GaN；在器件上表面和沟槽结构表面制作栅极绝缘层SixNy/SiO2双层结构，制作与上表面P型GaN外延层接触的源极接触电极Ti/Al，与栅极绝缘层SixNy/SiO2接触的栅极电极Ni/Au，与衬底接触的漏极电极Al。本发明保护了底部氧化物，有效降低了底部氧化物的最大电场，其具有更低能耗损失，更高的器件击穿电压，在较高温条件下工作以及器件良好的散热性能等优点。
Description
技术领域
本发明涉及高功率开关的半导体器件和制造该半导体器件的技术领域，具体涉及一种新型结构的底部沟槽栅极GaN-MOSFET器件及其制备方法。
背景技术
现如今，21世纪大家追求的是高效节约能源，在过去30年间，基于硅的MOSFET器件性能获得了超过两个数量级的改善，但如今也已到达其性能平稳期。除硅基以外，现如今氮化物基半导体来制作也是场效应晶体管很好的选择，在氮化镓(GaN)技术出现之初，它被引进为可以替代MOSFET的卓越技术，之后数年间，GaN技术有希望成为替代日益老化的功率MOSFET的创新技术。基于GaN技术的功率集成电路及模拟集成电路将可以具有与GaN晶体管相同的优势，从而满足新型产品的使用需求，需要采用新型MOSFET结构来解决不断涌现的功率挑战，近年来，具有垂直结构的晶体管作为功率控制晶体管受到关注。在此，提出采用一种新型GaN MOSFET器件结构。
GaN材料的研究与应用是目前全球半导体研究的前沿和热点，GaN是一种直接能隙的半导体，自1990年起常用在发光二极管中，此化合物结构类似纤锌矿，硬度很高。氮化镓的能隙很宽，为3.4电子伏特，可以用在高功率、高速的光电元件中，是研制微电子器件、光电子器件的新型半导体材料，并与SIC、金刚石等半导体材料一起，被誉为是继第一代Ge、Si半导体材料、第二代GaAs、InP化合物半导体材料之后的第三代半导体材料。GaN材料系列具有低的热产生率和高的击穿电场，是研制高温大功率电子器件和高频微波器件的重要材料。目前，随着分子束外延技术在GaN材料应用中的进展和关键薄膜生长技术的突破，成功地生长出了GaN多种异质结构。用GaN材料制备出了金属场效应晶体管(MESFET)、异质结场效应晶体管(HFET)、调制掺杂场效应晶体管(MODFET)等新型器件，其中最重要的是金属氧化物半导体场效应晶体管(MOSFET)器件。
发明内容
为了解决现有技术中存在的问题，本发明提供了一种新型结构的底部沟槽栅极GaN-MOSFET器件及其制备方法，在垂直沟槽下方生长一层P型GaN，保护了底部氧化物，有效降低了底部氧化物的最大电场，实现更低能耗损失，更高的器件击穿电压，具有良好导热性使器件以及能在较高温条件下工作。
本发明解决技术问题所采用的技术方案如下：
一种新型结构的底部沟槽栅极GaN-MOSFET器件，该器件从下至上依次为衬底、n型GaN外延层、P型GaN外延层和在P型GaN外延层中离子注入一层n型GaN，在器件中形成底部沟槽结构，侧壁为SixNy/SiO2结构，沟槽深度穿过P型GaN外延层，到达n型GaN外延层，在所述沟槽结构底部生长一层P型GaN；在器件上表面和沟槽结构表面制作栅极绝缘层SixNy/SiO2双层结构，制作与上表面P型GaN外延层接触的源极接触电极Ti/Al，与栅极绝缘层SixNy/SiO2接触的栅极电极Ni/Au，与衬底接触的漏极电极Al。
优选的，所述衬底的材料为：氮化镓、碳化硅或氯化铝衬底。
优选的，n型GaN外延层、P型GaN外延层和在P型GaN外延层中离子注入一层n型GaN生长方法为金属有机化合物气相沉积或氢化物气相外延或电子束外延法。
优选的，所述n型GaN外延层厚度为400-900nm，载流子浓度约为5x1016-5x1017cm-3；所述p型GaN外延层厚度为300-600nm，载流子浓度约为1x1018-5x1018cm-3；所述离子注入一层n型GaN厚度为100-250nm，载流子浓度约为1x1018-3x1019cm-3，位于沟槽底部的p型GaN层厚度为100-200nm，载流子浓度约为3x1018-5x1019cm-3。
优选的，所述底部沟槽结构的倾斜角为50°-90°。
一种新型结构的底部沟槽栅极GaN-MOSFET器件的制备方法，该方法包括如下步骤：
步骤一：在衬底上通过金属有机化合物气相沉积或氢化物气相外延或电子束外延法依次生长n型GaN外延层、p型GaN外延层和在P型GaN外延层中离子注入一层n型GaN；
步骤二：在器件上表面通过等离子体增强化学气相沉积或原子层沉积生长一层SiN；
步骤三：通过干法或者湿法刻蚀去掉部分SiN后，通过干法刻蚀形成底部沟槽结构，其中沟槽深度穿过P型GaN外延层，到达n型GaN外延层，；
步骤四：去掉器件表面剩余的SiN后，在所述沟槽底部生长一层p型GaN；
步骤五：在所述沟槽内和器件的部分上表面用电子回旋共振等离子体沉积SixNy/SiO2组成的双层结构作为栅极绝缘体；
步骤六：在器件的其他部分上表面形成Ni/Au作为栅极电极，使用剥离脱离工艺在600℃烧结形成用于源极接触的电极Ti/Al，在衬底底面形成漏极电极Al，完成一种新型结构的底部沟槽栅极GaN-MOSFET器件的制作方法。
优选的，所述步骤一中述n型GaN外延层厚度为400-900nm，载流子浓度约为5x1016-5x1017cm-3；所述p型GaN外延层厚度为300-600nm，载流子浓度约为1x1018-5x1018cm-3；所述离子注入一层n型GaN厚度为100-250nm，载流子浓度约为1x1018-3x1019cm-3。
优选的，所述步骤一中，氢基硅烷用作n型GaN掺杂的Si原料，而环戊二烯基镁可以用作p型GaN掺杂的Mg原料。
优选的，所述位于沟槽底部的p型GaN层厚度为100-200nm，载流子浓度约为3x1018-5x1019cm-3。
优选的，所述步骤五中，所述SixNy厚度为1nm-8nm，SiO2厚度为92nm-105nm。
本发明的有益效果是：本发明提出的底部沟槽栅极GaN-MOSFET器件结构，在垂直沟槽下方生长了一层P型GaN，保护了底部氧化物，有效降低了底部氧化物的最大电场，其具有更低能耗损失，更高的器件击穿电压，在较高温条件下工作以及器件良好的散热性能等优点。
附图说明
图1本发明一种新型结构的底部沟槽栅极GaN-MOSFET器件的结构示意图。
图2本发明一种新型结构的底部沟槽栅极GaN-MOSFET器件的制备方法步骤一和步骤二示意图。
图3本发明一种新型结构的底部沟槽栅极GaN-MOSFET器件的制备方法步骤三示意图。
图4本发明一种新型结构的底部沟槽栅极GaN-MOSFET器件的制备方法步骤四示意图。
具体实施方式
下面结合附图和实施例对本发明做进一步详细说明。
如图1所示，一种新型结构的底部沟槽栅极GaN-MOSFET器件，该器件从下至上依次为衬底、n型GaN外延层、P型GaN外延层和在P型GaN外延层中离子注入一层n型GaN，所述衬底的材料为：氮化镓、碳化硅或氯化铝衬底。本实施例中，衬底选用双面抛光的GaN材料。所述n型GaN外延层厚度为400-900nm，载流子浓度约为5x1016-5x1017cm-3，本实施例中，n型GaN外延层厚度为700nm，载流子浓度约为1x1017cm-3；所述p型GaN外延层厚度为300-600nm，载流子浓度约为1x1018-5x1018cm-3，本实施例中，p型GaN外延层厚度为500nm，载流子浓度约为2x1018cm-3；所述离子注入一层n型GaN厚度为100-250nm，载流子浓度约为1x1018-3x1019cm-3，本实施例中，n型GaN外延层厚度为150nm，载流子浓度约为3x1018；在器件中形成底部沟槽结构，侧壁为SixNy/SiO2结构，沟槽深度穿过P型GaN外延层，到达n型GaN外延层，在所述沟槽结构底部生长一层P型GaN；位于沟槽底部的p型GaN层厚度为100-200nm，载流子浓度约为3x1018-5x1019cm-3，本实施例中，p型GaN外延层厚度为100nm，载流子浓度约为1x1019cm-3。所述底部沟槽结构的底角可以为直角，或者其他角度，其中倾斜角的范围为50°-90°。
在器件上表面和沟槽结构表面制作栅极绝缘层SixNy/SiO2双层结构，其中SixNy厚度范围可以从1nm至8nm，本实施例中，SixNy厚度约为1nm，SiO2厚度范围可以从92nm-105nm，本实施例中，SiO2的厚度约为99nm。制作与上表面P型GaN外延层接触的源极接触电极Ti/Al，本实施例中，Ti的厚度为10nm，Al的厚度为240nm，与栅极绝缘层SixNy/SiO2接触的栅极电极Ni/Au，本实施例中，Ni的厚度为15nm，Au的厚度为125nm，与衬底接触的漏极电极Al，本实施例中，Al的厚度为250nm。
一种新型结构的底部沟槽栅极GaN-MOSFET器件的制备方法，该方法包括如下步骤：
步骤一：选用双面抛光的GaN衬底，在所述GaN衬底上通过金属有机化合物气相沉积(MOCVD)或氢化物气相外延或电子束外延法(MBE)依次生长n型GaN外延层、p型GaN外延层和在P型GaN外延层中离子注入一层n型GaN；所述n型GaN外延层厚度为400-900nm，载流子浓度约为5x1016-5x1017cm-3，本实施例中，n型GaN外延层厚度为700nm，载流子浓度约为1x1017cm-3；所述p型GaN外延层厚度为300-600nm，载流子浓度约为1x1018-5x1018cm-3，本实施例中，p型GaN外延层厚度为500nm，载流子浓度约为2x1018cm-3；所述离子注入一层n型GaN厚度为100-250nm，载流子浓度约为1x1018-3x1019cm-3，本实施例中，n型GaN外延层厚度为150nm，载流子浓度约为3x1018。氢基硅烷用作n型GaN掺杂的Si原料，而环戊二烯基镁可以用作p型GaN掺杂的Mg原料。
步骤二：利用等离子体增强化学气相沉积(PECVD)或原子层沉积(ALD)方法在GaN基器件结构表面生长一层20nm的SiN，以保护结构表面。
步骤三：通过干法或者湿法刻蚀去掉部分SiN后，通过Cl2/SiCl4干法刻蚀形成底部沟槽结构，侧壁为SixNy/SiO2结构，其中沟槽深度穿过P型GaN外延层，到达n型GaN外延层，沟槽底角的范围为50°-90°，本实施例中，底角的值为90°；
步骤四：在所述沟槽底部生长一层p型GaN后，去掉器件表面剩余的SiN；位于沟槽底部的p型GaN层厚度为100-200nm，载流子浓度约为3x1018-5x1019cm-3，本实施例中，p型GaN外延层厚度为100nm，载流子浓度约为1x1019cm-3。
步骤五：在所述沟槽内和器件的部分上表面用电子回旋共振(ECR)等离子体沉积SixNy/SiO2组成的双层结构作为栅极绝缘体，其中SixNy厚度范围为1nm至8nm，SiO2厚度范围为92nm-105nm，本实施例中，SixNy厚度约为1nm，SiO2约为99nm。
步骤六：在器件的其他部分上表面形成Ni/Au作为栅极电极，使用剥离脱离工艺在600℃烧结形成用于源极接触的电极Ti/Al，在衬底底面形成漏极电极Al，本实施例中，Ti的厚度为10nm，Al的厚度为240nm，与栅极绝缘层SixNy/SiO2接触的栅极电极Ni/Au，本实施例中，Ni的厚度为15nm，Au的厚度为125nm，与衬底接触的漏极电极Al，本实施例中，Al的厚度为250nm，完成一种新型结构的底部沟槽栅极GaN-MOSFET器件的制作方法。
Claims (10)
1.一种新型结构的底部沟槽栅极GaN-MOSFET器件，该器件从下至上依次为衬底、n型GaN外延层、P型GaN外延层和在P型GaN外延层中离子注入一层n型GaN，其特征在于，在器件中形成底部沟槽结构，侧壁为SixNy/SiO2结构，沟槽深度穿过P型GaN外延层，到达n型GaN外延层，在所述沟槽结构底部生长一层P型GaN；在器件上表面和沟槽结构表面制作栅极绝缘层SixNy/SiO2双层结构，制作与上表面P型GaN外延层接触的源极接触电极Ti/Al，与栅极绝缘层SixNy/SiO2接触的栅极电极Ni/Au，与衬底接触的漏极电极Al。
2.根据权利要求1所述的一种新型结构的底部沟槽栅极GaN-MOSFET器件，其特征在于，所述衬底的材料为：氮化镓、碳化硅或氯化铝衬底。
3.根据权利要求1所述的一种新型结构的底部沟槽栅极GaN-MOSFET器件，其特征在于，n型GaN外延层、P型GaN外延层和在P型GaN外延层中离子注入一层n型GaN生长方法为金属有机化合物气相沉积或氢化物气相外延或电子束外延法。
4.根据权利要求1所述的一种新型结构的底部沟槽栅极GaN-MOSFET器件，其特征在于，所述n型GaN外延层厚度为400-900nm，载流子浓度约为5x1016-5x1017cm-3；所述p型GaN外延层厚度为300-600nm，载流子浓度约为1x1018-5x1018cm-3；所述离子注入一层n型GaN厚度为100-250nm，载流子浓度约为1x1018-3x1019cm-3，位于沟槽底部的p型GaN层厚度为100-200nm，载流子浓度约为3x1018-5x1019cm-3。
5.根据权利要求1所述的一种新型结构的底部沟槽栅极GaN-MOSFET器件，其特征在于，所述底部沟槽结构的倾斜角为50o-90o。
6.基于权利要求1-5所述的一种新型结构的底部沟槽栅极GaN-MOSFET器件的制备方法，其特征在于，该方法包括如下步骤：
步骤一：在衬底上通过金属有机化合物气相沉积或氢化物气相外延或电子束外延法依次生长n型GaN外延层、p型GaN外延层和在P型GaN外延层中离子注入一层n型GaN；
步骤二：在器件上表面通过等离子体增强化学气相沉积或原子层沉积生长一层SiN；
步骤三：通过干法或者湿法刻蚀去掉部分SiN后，通过干法刻蚀形成底部沟槽结构，侧壁为SixNy/SiO2结构，其中沟槽深度穿过P型GaN外延层，到达n型GaN外延层，；
步骤四：在所述沟槽底部生长一层p型GaN后，去掉器件表面剩余的SiN；
步骤五：在所述沟槽内和器件的部分上表面用电子回旋共振等离子体沉积SixNy/SiO2组成的双层结构作为栅极绝缘体；
步骤六：在器件的其他部分上表面形成Ni/Au作为栅极电极，使用剥离脱离工艺在600℃烧结形成用于源极接触的电极Ti/Al，在衬底底面形成漏极电极Al，完成一种新型结构的底部沟槽栅极GaN-MOSFET器件的制作方法。
7.根据权利要求6所述的制作方法，其特征在于，所述步骤一中述n型GaN外延层厚度为400-900nm，载流子浓度约为5x1016-5x1017cm-3；所述p型GaN外延层厚度为300-600nm，载流子浓度约为1x1018-5x1018cm-3；所述离子注入一层n型GaN厚度为100-250nm，载流子浓度约为1x1018-3x1019cm-3。
8.根据权利要求6所述的制作方法，其特征在于，所述步骤一中，氢基硅烷用作n型GaN掺杂的Si原料，而环戊二烯基镁可以用作p型GaN掺杂的Mg原料。
9.根据权利要求6所述的制作方法，其特征在于，所述步骤四中，所述位于沟槽底部的p型GaN层厚度为100-200nm，载流子浓度约为3x1018-5x1019cm-3。
10.根据权利要求6所述的制作方法，其特征在于，所述步骤五中，所述SixNy厚度为1nm-8nm，SiO2厚度为92nm-105nm。
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