CN115188803B - 一种沟槽侧壁栅碳化硅mosfet及其制备方法 - Google Patents
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Abstract
本发明提供了一种沟槽侧壁栅碳化硅MOSFET及其制备方法，本发明通过在制备5‑10μm的宽碳化硅沟槽，沟槽间距2‑6μm；在宽沟槽内沉积侧壁保护层，向沟槽底部及非沟槽的中间部分进行加浓铝离子注入，去除侧壁掩膜层，涂布光刻胶，并无掩膜曝光，保留沟槽内的光刻胶，露出刻蚀掩膜层，清除刻蚀掩膜层，用光刻胶做氮离子注入阻挡层，并注入氮离子用来形成N+区；去除光刻胶，涂布碳膜，高温激活铝离子及氮离子，形成浓的P+，淡的P及浓的N+区。该结构的底部及Pwell中的P+区可以夹断栅氧拐角处的电场，保护栅氧不容易击穿；同时P+区可以同N外延区形成PN结，用作开关时的续流。
Description
技术领域
本发明涉及碳化硅沟槽MOSFET制备技术领域，具体涉及一种沟槽侧壁栅碳化硅MOSFET及其制备方法。
背景技术
半导体器件是导电性介于良导电体与绝缘体之间，利用半导体材料特殊电特性来完成特定功能的电子器件，可用来产生、控制、接收、变换、放大信 号和进行能量转换，其中，沟槽型半导体功率器件具有高集成度、导通电阻低、开关速度快、开关损耗小，广泛应用于各类电源管理及开关转换。随着国家对节能减排越来越重视，对功率器件的损耗及转换效率要求越来越高，导通损耗主要受导通电阻大小的影响。
半导体器件碳化硅(SiC)材料因其优越的物理特性，开始受到人们的关注和研究，碳化硅材料较高的热导率决定了其高电流密度的特性，较高的禁带宽度又决定了SiC 器件的高击穿场强和高工作温度。
目前，沟槽型碳化硅MOSFET是主流，然而在现有技术的制备方案中制备出的沟槽型碳化硅MOSFET中的栅氧结构容易被击穿，从而影响沟槽型碳化硅MOSFET的使用寿命。
发明内容
有鉴于此，本发明提供了一种沟槽侧壁栅碳化硅MOSFET制备方法，解决了现有技术中沟槽型碳化硅MOSFET中的栅氧结构容易被击穿，从而影响沟槽型碳化硅MOSFET的使用寿命的技术问题。
为了实现上述目的，本发明提供了一种沟槽侧壁栅碳化硅MOSFET，包括：漏极，位于所述漏极上方的碳化硅衬底，位于所述碳化硅衬底上方的碳化硅N外延，位于所述碳化硅N外延上方的第一P+区和第二P+区，位于所述第一P+区上方对称设置的栅氧区、栅极以及N沟道，位于所述栅氧区、栅极以及N沟道侧面的Pwell区和N+区，位于所述Pwell区和N+区上方的源极；
其中，所述第一P+区的宽度大于所述第二P+区的宽度，且第一P+区的深度大于所述第二P+区的深度。
优选的，所述第二P+区的两侧面对称设置有Pwell区和N+区。
优选的，所述N+区位于所述Pwell区的上方。
为了实现上述目的，本发明实施例还提供了一种沟槽侧壁栅碳化硅MOSFET的制备方法，包括如下步骤：
通过注入或外延的方式制作Pwell区，并沉积碳化硅沟槽刻蚀得到混合掩膜层，旋涂光刻胶并光刻，随后对混合掩膜层进行刻蚀，去除光刻胶；
在混合掩膜层的作用下，刻蚀碳化硅，形成5-10μm宽的碳化硅沟槽；
沉积侧壁保护层；
干法刻蚀侧壁保护层至碳化硅暴露出，通过光刻胶，刻蚀沟槽中间的混合掩膜层，形成1-2μm宽的沟槽；
去除光刻胶，在混合掩膜及侧壁保护层的作用下，进行高温铝离子注入，形成高浓度的第一P+区和第二P+区；
清除侧壁保护层，旋涂光刻胶，胶厚1-2μm；
调整曝光强度，露出混合掩膜层，保留孔内的光刻胶，清除混合掩膜层；
在光刻胶的掩膜下进行氮离子注入，形成N+区，去除光刻胶；
制备栅氧，并沉积1-2μm的多晶硅，无掩膜刻蚀多晶硅，至暴露出底部及顶部的栅氧，沉积隔离介质层，填充宽沟槽，通过光刻胶掩膜，刻蚀隔离介质层及栅氧区，形成多晶硅的电隔离层，沉积金属定义栅极、源极和漏极。
采用上述实施例的有益效果是：
本发明通过在制备5-10μm的宽碳化硅沟槽，沟槽间距2-6μm；在宽沟槽内沉积侧壁保护层，向沟槽底部及非沟槽的中间部分进行加浓铝离子注入，去除侧壁掩膜层，涂布光刻胶，并无掩膜曝光，保留沟槽内的光刻胶，露出刻蚀掩膜层，清除刻蚀掩膜层，用光刻胶做氮离子注入阻挡层，并注入氮离子用来形成N+区；去除光刻胶，涂布碳膜，高温激活铝离子及氮离子，形成浓的P+，淡的P及浓的N+区；制备栅氧，并沉积1-2μm厚的多晶硅，无掩膜干法刻蚀多晶硅，至暴露出栅氧；沉积ILD，在掩膜板的作用下，刻蚀ILD及栅氧，形成侧壁栅氧隔离层；制备金属，定义栅、源及漏，该结构的底部及Pwell中的P+区可以夹断栅氧拐角处的电场，保护栅氧不容易击穿；同时P+区可以同N外延区形成PN结，用作开关时的续流。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明提供的沟槽侧壁栅碳化硅MOSFET制备方法中步骤S1执行后沟槽侧壁栅碳化硅MOSFET一实施例的结构变化示意图；
图2为本发明提供的沟槽侧壁栅碳化硅MOSFET制备方法中步骤S2执行后沟槽侧壁栅碳化硅MOSFET一实施例的结构变化示意图；
图3为本发明提供的沟槽侧壁栅碳化硅MOSFET制备方法中步骤S3执行后沟槽侧壁栅碳化硅MOSFET一实施例的结构变化示意图；
图4为本发明提供的沟槽侧壁栅碳化硅MOSFET制备方法中步骤S4执行后沟槽侧壁栅碳化硅MOSFET一实施例的结构变化示意图；
图5为本发明提供的沟槽侧壁栅碳化硅MOSFET制备方法中步骤S5执行后沟槽侧壁栅碳化硅MOSFET一实施例的结构变化示意图；
图6为本发明提供的沟槽侧壁栅碳化硅MOSFET制备方法中步骤S6执行后沟槽侧壁栅碳化硅MOSFET一实施例的结构变化示意图；
图7为本发明提供的沟槽侧壁栅碳化硅MOSFET制备方法中步骤S7执行后沟槽侧壁栅碳化硅MOSFET一实施例的结构变化示意图；
图8为本发明提供的沟槽侧壁栅碳化硅MOSFET制备方法中步骤S8执行后沟槽侧壁栅碳化硅MOSFET一实施例的结构变化示意图；
图9为本发明提供的沟槽侧壁栅碳化硅MOSFET制备方法中步骤S9执行后沟槽侧壁栅碳化硅MOSFET一实施例的结构变化示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
为了解决现有技术中的技术问题，本发明提供了一种沟槽侧壁栅碳化硅MOSFET，请参阅图9，此图9为本发明提供的沟槽侧壁栅碳化硅MOSFET的制备完成的最终实施例附图。
具体的，该沟槽侧壁栅碳化硅MOSFET，包括：漏极113，位于所述漏极113上方的碳化硅衬底101，位于所述碳化硅衬底101上方的碳化硅N外延102，位于所述碳化硅N外延102上方的第一P+区117和第二P+区127，位于所述第一P+区117上方对称设置的栅氧区、栅极112以及N沟道，位于所述栅氧区、栅极112以及N沟道侧面的Pwell区103和N+区109，位于所述Pwell区103和N+区109上方的源极111；
其中，所述第一P+区117的宽度大于所述第二P+区127的宽度，且第一P+区117的深度大于所述第二P+区127的深度。所述第二P+区127的两侧面对称设置有Pwell区103和N+区109。所述N+区109位于所述Pwell区103的上方。
在本实施例中，本发明通过形成浓的P+，淡的P及浓的N+区109，并沉积1-2μm厚的多晶硅，无掩膜干法刻蚀多晶硅，至暴露出栅氧，该结构的底部及Pwell中的P+区（即第一P+区117和第二P+区127）可以夹断栅氧拐角处的电场，保护栅氧不容易击穿，同时第二P+区127可以同N外延区形成PN结，用作开关时的续流。
为了制备该沟槽侧壁栅碳化硅MOSFET，在本发明的实施例中，请参阅图1-图7，本发明还提供了一种沟槽侧壁栅碳化硅MOSFET制备方法，包括如下步骤：
S1、通过注入或外延的方式制作Pwell区103，并沉积碳化硅沟槽105刻蚀得到混合掩膜层104，旋涂光刻胶108并光刻，随后对混合掩膜层104进行刻蚀，去除光刻胶108，其中，根据刻蚀选择比和后期注入状况进行硅化物的加厚得到硅化物与Ni的混合层，混合层Ni在顶部，硅化物在底部，Ni层可选择较薄的0.5微米左右，硅化物选择较厚的2微米左右，硅化物优选二氧化硅，该混合掩膜层104充当刻蚀掩膜层及注入阻挡层，具体请参阅图1，其中，通过在碳化硅衬底101上进行碳化硅N外延102处理后制备Pwell区103；
S2、在混合掩膜层104的作用下，刻蚀碳化硅，形成5-10μm宽的碳化硅沟槽105，沟槽间距为2-6μm，具体请参阅图2，其中，碳化硅沟槽105穿过混合掩膜层104、Pwell区103和碳化硅N外延102；
S3、沉积侧壁保护层106，具体请参阅图3；
S4、干法刻蚀侧壁保护层106至碳化硅暴露出，通过光刻胶108，刻蚀沟槽中间的混合掩膜层104，形成1-2μm宽的沟槽，具体请参阅图4；
S5、去除光刻胶108，在混合掩膜及侧壁保护层106的作用下，进行高温铝离子注入，形成高浓度的第一P+区117和第二P+区127，其中，所述第一P+区117的宽度大于所述第二P+区127的宽度，且第一P+区117的深度大于所述第二P+区127的深度。所述第二P+区127的两侧面对称设置有Pwell区103和N+区109，具体请参阅图5；
S6、清除侧壁保护层106，旋涂光刻胶108，胶厚1-2μm，具体请参阅图6；
S7、调整曝光强度，露出混合掩膜层104，保留孔内的光刻胶108，清除混合掩膜层104，具体请参阅图7；
S8、在光刻胶108的掩膜下进行氮离子注入，形成N+区109，去除光刻胶108，具体请参阅图8；
S9、制备栅氧，并沉积1-2μm的多晶硅，无掩膜刻蚀多晶硅，至暴露出底部及顶部的栅氧，沉积隔离介质层110，填充宽沟槽，通过光刻胶108掩膜，刻蚀隔离介质层110及栅氧区，形成多晶硅的电隔离层，沉积金属定义栅极112、源极111和漏极113，具体请参阅图9，其中，该结构的底部及Pwell中的P+区可以夹断栅氧拐角处的电场，保护栅氧不容易击穿；同时P+区可以同N外延区形成PN结，用作开关时的续流。
综上所述，本发明通过在制备5-10μm的宽碳化硅沟槽，沟槽间距2-6μm；在宽沟槽内沉积侧壁保护层，向沟槽底部及非沟槽的中间部分进行加浓铝离子注入，去除侧壁掩膜层，涂布光刻胶，并无掩膜曝光，保留沟槽内的光刻胶，露出刻蚀掩膜层，清除刻蚀掩膜层，用光刻胶做氮离子注入阻挡层，并注入氮离子用来形成N+区；去除光刻胶，涂布碳膜，高温激活铝离子及氮离子，形成浓的P+，淡的P及浓的N+区；制备栅氧，并沉积1-2μm厚的多晶硅，无掩膜干法刻蚀多晶硅，至暴露出栅氧；沉积ILD，在掩膜板的作用下，刻蚀ILD及栅氧，形成侧壁栅氧隔离层；制备金属，定义栅、源及漏，该结构的底部及Pwell中的P+区可以夹断栅氧拐角处的电场，保护栅氧不容易击穿；同时P+区可以同N外延区形成PN结，用作开关时的续流。
以上对本发明所提供的沟槽侧壁栅碳化硅MOSFET制备方法进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。
Claims (3)
1.一种沟槽侧壁栅碳化硅MOSFET的制备方法，其特征在于，所述沟槽侧壁栅碳化硅MOSFET，包括：漏极，位于所述漏极上方的碳化硅衬底，位于所述碳化硅衬底上方的碳化硅N外延，位于所述碳化硅N外延上方的第一P+区和第二P+区，位于所述第一P+区上方对称设置的栅氧区、栅极以及N沟道，位于所述栅氧区、栅极以及N沟道侧面的Pwell区和N+区，位于所述Pwell区和N+区上方的源极；
其中，所述第一P+区的宽度大于所述第二P+区的宽度，且第一P+区的深度大于所述第二P+区的深度；
所述沟槽侧壁栅碳化硅MOSFET的制备方法包括如下步骤：
通过注入或外延的方式制作Pwell区，并形成混合掩膜材料，旋涂光刻胶并光刻，随后对混合掩膜材料进行刻蚀，去除光刻胶，以得到混合掩膜层；
在混合掩膜层的作用下，刻蚀碳化硅，形成5-10μm宽的碳化硅沟槽；
沉积侧壁保护层；
干法刻蚀侧壁保护层至碳化硅暴露出，通过光刻胶，刻蚀沟槽中间的混合掩膜层，形成1-2μm宽的沟槽；
去除光刻胶，在混合掩膜及侧壁保护层的作用下，进行高温铝离子注入，形成高浓度的第一P+区和第二P+区；
清除侧壁保护层，旋涂光刻胶，胶厚1-2μm；
调整曝光强度，露出混合掩膜层，保留孔内的光刻胶，清除混合掩膜层；
在光刻胶的掩膜下进行氮离子注入，形成N+区，去除光刻胶；
制备栅氧，并沉积1-2μm的多晶硅，无掩膜刻蚀多晶硅，至暴露出底部及顶部的栅氧，沉积隔离介质层，填充宽沟槽，通过光刻胶掩膜，刻蚀隔离介质层及栅氧区，形成多晶硅的电隔离层，沉积金属定义栅极、源极和漏极。
2.根据权利要求1所述的沟槽侧壁栅碳化硅MOSFET的制备方法，其特征在于，所述第二P+区的两侧面对称设置有Pwell区和N+区。
3.根据权利要求1所述的沟槽侧壁栅碳化硅MOSFET的制备方法，其特征在于，所述N+区位于所述Pwell区的上方。
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