JP6385755B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP6385755B2 JP6385755B2 JP2014162936A JP2014162936A JP6385755B2 JP 6385755 B2 JP6385755 B2 JP 6385755B2 JP 2014162936 A JP2014162936 A JP 2014162936A JP 2014162936 A JP2014162936 A JP 2014162936A JP 6385755 B2 JP6385755 B2 JP 6385755B2
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Description
<半導体装置の全体構造について>
本実施の形態の半導体装置を、図面を参照して説明する。
次に、上記半導体装置(半導体チップ)CPの内部構造について、図面を参照して説明する。
次に、本実施の形態の半導体装置の製造工程について、図8〜図25を参照して説明する。図8および図9は、本実施の形態の半導体装置の製造工程を示すプロセスフロー図である。図10〜図25は、本実施の形態の半導体装置の製造工程中の要部断面図であり、上記図4に対応する断面図が示されている。
図26は、半導体基板SBのトランジスタセル領域に形成されている上記単位トランジスタQ1を構成するIGBTの等価回路図である。
次に、本発明者が検討した検討例の半導体装置について説明する。
本実施の形態の半導体装置は、n型の半導体基板SBと、半導体基板SBの主面上に形成された絶縁層ZSと、絶縁層ZSに形成された溝TRと、溝TR内において、溝TRの底部で露出する半導体基板SB上に形成された半導体層EPと、溝TR内において、半導体層EPを挟むように半導体層EPの両側に形成された一対のゲート電極GEと、を有している。本実施の形態の半導体装置は、更に、溝TR内において、半導体層EPと一対のゲート電極GEとの間に介在するゲート絶縁膜GIと、絶縁層ZS上に、半導体層EPおよび一対のゲート電極GEを覆うように形成された絶縁層ILと、半導体層EP上に形成され、絶縁層ILを貫通し、半導体層EPに達するコンタクトホールCT1と、を有している。本実施の形態の半導体装置は、更に、コンタクトホールCT1内に形成されたエミッタ用ビア部VE(電極部、エミッタ電極)と、半導体基板SBにおいて、絶縁層ZSが形成されている側とは反対側である裏面側に形成されたp型半導体領域CLと、半導体基板SBの裏面上に形成され、p型半導体領域CLに電気的に接続された裏面電極BEと、を有している。半導体層EPにおいて、半導体層EPの上部には、p型半導体領域PRとp型半導体領域PR上のn+型半導体領域NRとが形成されている。半導体層EPにおいて、p型半導体領域PRの下の部分はn型である。エミッタ用ビア部VE(電極部、エミッタ電極)は、p型半導体領域PRおよびn+型半導体領域NRと電気的に接続されている。半導体層EPの両側に形成された一対のゲート電極GEの下には、絶縁層ZSの一部が存在し、一対のゲート電極GEにおけるゲート絶縁膜GIを介して半導体層EPに対向する側とは反対側の側面は、絶縁層ZSに隣接している。
図34および図35は、本実施の形態2の半導体装置の製造工程中の要部断面図である。
図36および図37は、本実施の形態2の半導体装置の製造工程中の要部断面図である。
図38は、本実施の形態4の半導体装置の要部平面図であり、上記実施の形態1の上記図3に対応するものである。図39は、本実施の形態4の半導体装置の要部断面図であり、上記実施の形態1の上記図4に対応するものである。図39は、図38のA−A線の断面図にほぼ対応している。
BE100 裏面コレクタ電極
C コレクタ電極
CC キャリア排出用セル
CL p型半導体領域
CL100 p型コレクタ層
CP 半導体装置
CT1,CT2,CT3,CT100 コンタクトホール
W1,W2 幅
E エミッタ電極
EP,EP2,EP100 半導体層
EP1,EP3 n型半導体領域
FS n型半導体領域
G 電極
GE,GE100 ゲート電極
GI,GI100 ゲート絶縁膜
GIa 絶縁膜
IL,IL100 絶縁層
M1 配線
M1E,M1E100 エミッタ用の配線
M1G ゲート用の配線
NR n+型半導体領域
NR100 n型エミッタ層
NSB n型基板領域
OP 開口部
OPE エミッタ用開口部
OPG ゲート用開口部
OX 酸化膜
PA 絶縁膜
PDE エミッタ用パッド
PDG ゲート用パッド
PR,PR2 p型半導体領域
PR100 p型ベース層
Q1 単位トランジスタ
RG1 領域
RP1,RP2 フォトレジストパターン
RP1a 開口部
SB,SB100 半導体基板
TR,TR1a,TR2a,TR101,TR102 溝
TR1,TR2 溝部
TR1a,TR2a,TR3 溝
UCL 単位構造
VC キャリア排出用ビア部
VE,VE100 エミッタ用ビア部
VG ゲート用ビア部
W3,W4,W5a,W5b,W6,W7,W8,W9,W11,W12 幅
ZS,ZS100 絶縁層
Claims (13)
- IGBTを有する半導体装置の製造方法であって、
(a)第1導電型の第1ベース領域用の半導体基板を用意する工程、
(b)前記半導体基板の主面上に第1絶縁層を形成する工程、
(c)前記第1絶縁層に、前記第1絶縁層を貫通して前記半導体基板の一部を露出する第1溝を形成する工程、
(d)前記第1溝の底部で露出する前記半導体基板上に、前記第1溝内を埋めるように、前記第1導電型の第1半導体層を形成する工程、
(e)前記第1絶縁層において、前記第1溝の両側に、前記第1溝を挟むように、一対の第2溝を形成する工程、
(f)前記一対の第2溝を拡張して、前記一対の第2溝から、前記第1半導体層の側面の一部を露出させる工程、
(g)前記一対の第2溝から露出する前記第1半導体層の側面にゲート絶縁膜用の絶縁膜を形成する工程、
(h)前記一対の第2溝内のそれぞれに、ゲート電極を形成する工程、
(i)前記第1半導体層の上部に、前記第1導電型とは反対の第2導電型の第2ベース領域と、前記第1導電型のエミッタ領域とを形成する工程、
を有し、
前記(e)工程では、前記一対の第2溝から前記第1半導体層の側面は露出されず、かつ、前記一対の第2溝は、前記半導体基板に達していない、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(d)工程では、前記第1半導体層は、エピタキシャル成長により形成される、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(f)工程では、等方性エッチングにより前記一対の第2溝を拡張する、半導体装置の製造方法。 - 請求項3記載の半導体装置の製造方法において、
前記(f)工程では、ウェットエッチングにより前記一対の第2溝を拡張する、半導体装置の製造方法。 - 請求項4記載の半導体装置の製造方法において、
前記(f)工程では、前記第1絶縁層よりも前記第1半導体層がエッチングされにくい条件でエッチングを行うことにより、前記一対の第2溝を拡張する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(f)工程では、前記一対の第2溝の下に前記第1絶縁層の一部が残存し、
前記(h)工程で形成された一対の前記ゲート電極の下には、前記第1絶縁層の一部が存在する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(c)工程で形成された前記第1溝は、前記第1溝の上部における幅が、前記第1溝の下部における幅よりも大きい、半導体装置の製造方法。 - 請求項7記載の半導体装置の製造方法において、
前記(c)工程は、
(c1)前記第1絶縁層にマスク層を形成する工程、
(c2)前記マスク層をエッチングマスクとして用いて、前記第1絶縁層を等方性エッチングする工程、
(c3)前記(c2)工程後、前記マスク層をエッチングマスクとして用いて、前記第1絶縁層を異方性エッチングする工程、
を有し、
前記(c2)工程では、前記第1溝は前記半導体基板に到達せず、
前記(c3)工程で、前記第1溝は前記半導体基板に到達する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(c)工程で形成された前記第1溝は、テーパを有している、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(f)工程後で、前記(g)工程前に、
(f1)前記一対の第2溝から露出する前記第1半導体層の側面を酸化する工程、
(f2)前記(f1)工程で前記第1半導体層の側面に形成された酸化膜を除去する工程、
を1サイクル以上行う、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
(j)前記第1絶縁層上に、前記第1半導体層および前記ゲート電極を覆うように、第2絶縁層を形成する工程、
(k)前記第1半導体層上に前記第2絶縁層を貫通して前記第1半導体層に達する第1コンタクトホールを形成する工程、
(l)前記第1コンタクトホール内に、前記第2ベース領域と前記エミッタ領域とに電気的に接続される第1電極部を形成する工程、
を更に有する、半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において、
前記第1コンタクトホールの底面の深さ位置における前記第1半導体層の第1の幅をW1とし、
前記第2ベース領域の下でかつ一対の前記ゲート電極によって挟まれた部分の前記第1半導体層の第2の幅をW2としたときに、
W1>W2が成り立つ、半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において、
前記(c)工程では、前記第1絶縁層に、前記第1溝と離間しかつ前記第1絶縁層を貫通する第3溝も形成され、
前記(d)工程では、前記第3溝の底部で露出する前記半導体基板上に、前記第3溝内を埋めるように、前記第1導電型の第2半導体層も形成され、
前記(e)工程および前記(f)工程では、前記第2半導体層に隣接して前記第2半導体層の側面を露出させる溝は形成されず、
前記(i)工程では、前記第2半導体層の上部に、前記第2導電型の半導体領域が形成され、
前記(k)工程では、前記第2半導体層上に前記第2絶縁層を貫通して前記第2半導体層に達する第2コンタクトホールも形成され、
前記(l)工程では、前記第2コンタクトホール内に、前記半導体領域と電気的に接続される第2電極部も形成され、
前記第2半導体層に隣接するゲート電極は形成されず、
前記第1電極部と前記第2電極部とは、導体で繋がっている、半導体装置の製造方法。
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