JPWO2012077617A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JPWO2012077617A1 JPWO2012077617A1 JP2012547837A JP2012547837A JPWO2012077617A1 JP WO2012077617 A1 JPWO2012077617 A1 JP WO2012077617A1 JP 2012547837 A JP2012547837 A JP 2012547837A JP 2012547837 A JP2012547837 A JP 2012547837A JP WO2012077617 A1 JPWO2012077617 A1 JP WO2012077617A1
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Abstract
Description
図1および図2は、実施の形態1に係る半導体装置の構成を示す図である。ここでは半導体装置の一例として、炭化珪素(SiC)半導体装置であるトレンチゲート型MOSFETを示す。図1は当該MOSFETの平面図である。図2(a)は、図1のA−A線に沿った断面図であり、MOSFETセルの形成領域(MOSFETセル領域)を示している。一方、図2(b)は図1のB−B線に沿った断面図であり、保護拡散層に接続するコンタクト(保護コンタクト)の形成領域20(保護コンタクト領域)を含んでいる。保護コンタクト領域20の詳細については後述する。
実施の形態1で説明したように、ゲート電極7は、パターニングおよびエッチバックのいずれの手法でも形成できる。しかし、保護コンタクト領域20のトレンチ5がテーパー状に形成された場合、エッチバックによりゲート電極7を形成しようとすると、保護コンタクト領域20のトレンチ5内に配設されるゲート電極7が完全に除去される恐れがある。
図13は、本発明の実施の形態3に係る半導体装置の構成を示す断面図であり、当該半導体装置のMOSFETセルアレイの最外周部の断面を示している。本実施の形態では、最外周のMOSFETセルのさらに外側に隣り合うように、MOSFETとして機能しないダミーセル30を配設している。ダミーセル30は、MOSFETセルアレイを囲うように配置される。MOSFETセルアレイ(保護コンタクト領域20を含む)の最外周部以外の構成は、実施の形態1または2と同様である。
図14は、本発明の実施の形態4に係る半導体装置の構成を示す断面図であり、当該半導体装置のMOSFETセルアレイの最外周部の断面を示している。本実施の形態では、最外周のMOSFETセルの外側を囲うように、保護コンタクト21が配設される最外周保護コンタクト領域40を設けている。MOSFETセルアレイ(保護コンタクト領域20を含む)の最外周部以外の構成は、実施の形態1または2と同様である。
Claims (10)
- 第1導電型の半導体層と、
前記半導体層の上部に形成された第2導電型のベース領域と、
前記ベース領域を貫通するように前記半導体層に埋め込み形成され、平面視で格子状に配設されたゲート電極と、
前記ゲート電極の側面および底面に形成されたゲート絶縁膜と、
前記ベース領域の上部において前記ゲート絶縁膜を介して前記ゲート電極と接するように形成された第1導電型のソース領域と、
前記ソース領域および前記ベース領域の上面に接続するソース電極と、
前記ゲート電極で区切られた複数の区画のうち少なくとも1区画において、前記ベース領域を貫通するように形成された開口部と、
前記半導体層において前記ゲート絶縁膜を介した前記ゲート電極の底部および前記開口部の底部に渡って形成された第2導電型の保護拡散層と、
前記開口部を通して前記保護拡散層と前記ソース電極とを接続する保護コンタクトと、
前記保護コンタクトと前記ゲート電極との間に介在する層間絶縁膜とを備える
ことを特徴とする半導体装置。 - 前記保護コンタクトは、前記層間絶縁膜を介して前記ゲート電極に隣接している
請求項1記載の半導体装置。 - 前記開口部が配設された区画を規定する前記ゲート電極は、端部が前記半導体層の上面に位置しており、
前記開口部が配設された区画以外の区画を規定する前記ゲート電極は、全体が前記半導体層に埋め込まれている、
請求項1または請求項2記載の半導体装置。 - 前記開口部が配設された区画を除く前記複数の区画のそれぞれは、トランジスタセルであり、
前記複数の区画が配設された領域の外周に、トランジスタとして機能しないダミーセルがさらに配設され、
前記ダミーセルは、前記ベース領域を貫通するように前記半導体層に埋め込み形成された絶縁膜を備えており、
前記半導体層に埋め込み形成された前記絶縁膜は、平面視で、格子状のゲート電極の外周に、当該ゲート電極と共に格子状のパターンを形成するように配設されている
請求項1から請求項3のいずれか一項記載の半導体装置。 - 格子状に配設されたゲート電極の最外周部分は、前記ベース領域を貫通するように形成された最外周トレンチ内に形成されており、
前記最外周トレンチの内周側の側面には、前記ゲート絶縁膜を介して前記ゲート電極が形成されており、
前記最外周トレンチの外周側の側面には、フィールド絶縁膜を介して前記ゲート電極が形成されており、
前記保護拡散層は、前記最外周トレンチの底部にまで延在しており、
前記最外周トレンチの内周側の前記ゲート電極と前記最外周トレンチの外周側の前記ゲート電極との間の領域に、前記最外周トレンチの底部の前記保護拡散層と前記ソース電極とを接続する最外周保護コンタクトをさらに備える
請求項1から請求項3のいずれか一項記載の半導体装置。 - 前記半導体層は、ワイドバンドギャップ半導体である
請求項1から請求項5のいずれか一項記載の半導体装置。 - 第1導電型の半導体層を有する半導体基板を用意する工程と、
前記半導体層の上部に第2導電型のベース領域を形成する工程と、
前記ベース領域の上部に第1導電型で格子状のソース領域を形成する工程と、
前記半導体層上に少なくとも一箇所が欠けたマトリクス状のエッチングマスクを形成する工程と、
前記エッチングマスクを用いたエッチングにより、前記ソース領域および前記ベース領域を貫通する格子状のトレンチを形成すると共に、前記マトリクス状の欠けた部分に前記ソース領域および前記ベース領域を貫通する開口部を形成する工程と、
前記トレンチおよび前記開口部の底部に第2導電型の保護拡散層を形成する工程と、
前記トレンチおよび前記開口部の内面にゲート絶縁膜を形成した後、前記トレンチ内および前記開口部の外周部にゲート電極を形成する工程と、
前記ゲート電極を覆う層間絶縁膜を形成する工程と、
前記層間絶縁膜に、前記ソース領域および前記ベース領域に達する第1コンタクトホール並びに前記開口部の底の前記保護拡散層に達する第2コンタクトホールを形成する工程と、
前記層間絶縁膜上並びに前記第1および第2コンタクトホール内に電極を形成する工程とを備える
ことを特徴とする半導体装置の製造方法。 - 前記保護拡散層は、前記エッチングマスクを使用したイオン注入によって形成される
請求項7記載の半導体装置の製造方法。 - 前記ゲート電極を形成する工程において、
前記トレンチ内に形成する前記ゲート電極は、当該ゲート電極の材料膜をエッチバックすることによって形成され、
前記開口部の外周部に形成するゲート電極は、当該ゲート電極の材料膜をパターニングすることによって形成される
請求項7または請求項8記載の半導体装置の製造方法。 - 前記半導体層は、ワイドバンドギャップ半導体である
請求項7から請求項9のいずれか一項記載の半導体装置の製造方法。
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