Classifications

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  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
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  • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
  • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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  • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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  • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
  • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
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  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
  • H01L21/30604—Chemical etching
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  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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  • H10D30/0217—Manufacture or treatment of FETs having insulated gates [IGFET] forming self-aligned punch-through stoppers or threshold implants under gate regions
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  • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
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  • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
  • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
  • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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  • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
  • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
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  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
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  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
  • H10D30/663—Vertical DMOS [VDMOS] FETs having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS
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  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
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  • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
  • H10D62/109—Reduced surface field [RESURF] PN junction structures
  • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
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  • H10D62/113—Isolations within a component, i.e. internal isolations
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  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
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  • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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  • H10D62/156—Drain regions of DMOS transistors
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  • H10D64/311—Gate electrodes for field-effect devices
  • H10D64/411—Gate electrodes for field-effect devices for FETs
  • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
  • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
  • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
  • H10D64/311—Gate electrodes for field-effect devices
  • H10D64/411—Gate electrodes for field-effect devices for FETs
  • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
  • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
  • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

• the present invention relates to electronic devices, and more particularly to a semiconductor device adapted to sustain high voltages.
• SJ SuperJunction
• a SJ device structure
• R sp specific on-resistance
• the widths of the n-type and p-type pillars set a limit on the cell pitch and the scaling down of the structure.
• drawbacks associated with the manufacturing of a SJ structure such as the requirement to grow multiple epitaxial layers and to perform a number of implant and diffusion steps.
• a need continues to exist for a semiconductor device that has a high breakdown voltage, a low R sp , low capacitances and low reverse recovery charge (Qrr), is easily scaled down and is easier to manufacture.
• a semiconductor structure in accordance with one embodiment of the present invention, includes, in part, a number of semiconductor regions, at least a pair of dielectric regions and a pair of terminals.
• the first and second regions of the semiconductor structure are respectively coupled to the first and second terminals.
• the third region of the semiconductor structure is of a single conductivity type and is disposed between the first and second regions.
• the dielectric regions extend into the third region.
• a concentration of doping impurities present in the third region and a distance between the dielectric regions define an electrical characteristic of the semiconductor structure.
• the electrical characteristic of the semiconductor structure is independent of the width of the dielectric regions width.
• the first and second regions are of opposite conductivity types.
• the dielectric regions extend into the first and second regions.
• the integrated density of doping impurities in the third region along a line parallel to a surface of the dielectric regions ranges from about 1x10 12 / cm 2 to about 5xlO 12 /cm 2 .
• each dielectric region further includes a second material.
• the second material in each dielectric region includes, in part, aluminum fluoride.
• each dielectric region further includes, in part, a third material that is a dielectric material.
• the second and third materials in each dielectric region are the same material.
• the first and second regions are respectively p+ type and n+ type regions, and the first and second terminals are respectively anode and cathode terminals.
• the third region is a p-type region. In another embodiment, the third region is an n-type region. In one embodiment, the third region is formed above the second region, and said first region is formed above the third region. In one embodiment, the dielectric regions are isolated from one another.
• the semiconductor structure further includes, in part, a fourth region disposed between the second and the third regions.
• the second and fourth regions are of the same conductivity type.
• the first and second regions are respectively n+ type and p+ type regions, and the first and second terminals are respectively cathode and anode terminals.
• the third region is a p-type region.
• the third region is an n-type region.
• the third region is formed above the second region, and the first region is formed above the third region.
• the third region is formed above the second region and the first region is formed above the third region.
• each of the dielectric region is tapered so as to have a larger width near one end of the dielectric region than another end of the dielectric region.
• the first, second and third regions are formed along the same surface of a semiconductor substrate in which the semiconductor structure is formed.
• the semiconductor structure includes a fourth region in which the second region is formed.
• the third region is adjacent the first and fourth regions.
• the first region is a p+ type region
• the second region is an n+ type region
• the third region is a p-type region
• the fourth region is an n-type region.
• the first region is a p+-type region
• the second region is an n+-type region
• the third region is an n-type region
• the fourth region is a p-type region.
• a semiconductor structure in accordance with another embodiment of the present invention, includes, in part, a number of semiconductor regions, at least a pair of dielectric regions and a pair of terminals.
• the first and second regions of the semiconductor structure are respectively coupled to the first and second terminals.
• the third and fourth regions are disposed between and adjacent the first and second regions.
• the dielectric regions extend into the third region.
• the fourth region extends into the third region, has a conductivity type opposite a conductivity type of the third region, and surrounds a portion of the at least first and second dielectric regions.
• a concentration of doping impurities present in the third region and a distance between the dielectric regions define an electrical characteristic of the semiconductor structure.
• the electrical characteristic of the semiconductor structure is independent of the width of the dielectric regions width.
• the first and second regions are of opposite conductivity types.
• the interface region between the dielectric regions and the fourth region includes intentionally induced charges.
• the dielectric regions extend into the first and second regions.
• the integrated density of doping impurities in the third region along a line parallel to a surface of the dielectric regions ranges from about 1x10 12 / cm 2 to about 5x10 1 /cm .
• each dielectric region further includes a second material.
• the second material in each dielectric region includes, in part, aluminum fluoride.
• each dielectric region further includes, in part, a third material that is a dielectric material.
• the second and third materials in each dielectric region are the same material.
• the first and second regions are respectively p+ type and n+ type regions, and the first and second terminals are respectively anode and cathode terminals.
• the third region is a p-type region. In another embodiment, the third region is an n-type region. In one embodiment, the third region is formed above the second region, and said first region is formed above the third region. In one embodiment, the dielectric regions are isolated from one another.
• the semiconductor structure further includes, in part, a fourth region disposed between the second and the third regions.
• the second and fourth regions are of the same conductivity type.
• the first and second regions are respectively n+ type and p+ type regions, and the first and second terminals are respectively cathode and anode terminals.
• the third region is a p-type region. In one embodiment, the third region is a p-type region. In another embodiment, the third region is an n-type region. In one embodiment, the third region is formed above the second region, and the first region is formed above the third region. In one embodiment, the third region is formed above the second region and the first region is formed above the third region. In one embodiment, each of the dielectric region is tapered so as to have a larger width near one end of the dielectric region than another end of the dielectric region.
• the first, second and third regions are formed along the same surface of a semiconductor substrate in which the semiconductor structure is formed.
• the semiconductor structure includes a fourth region in which the second region is formed.
• the third region is adjacent the first and fourth regions.
• the first region is a p+ type region
• the second region is an n+ type region
• the third region is a p-type region
• the fourth region is an n-type region.
• the first region is a p+-type region
• the second region is an n+-type region
• the third region is an n-type region
• the fourth region is a p-type region.
• Figure 1 is a cross-sectional view of a SuperJunction device, as known in the prior art.
• Figure 2A is a cross-sectional view of an exemplary voltage sustaining semiconductor structure, in accordance with one embodiment of the present invention.
• Figure 2B is a cross-sectional view of an exemplary voltage sustaining semiconductor structure, in accordance with one embodiment of the present invention.
• Figures 2C, 2D, 2E, 2F are exemplary top views of the device of Figure 2A, in accordance with one embodiment of the present invention.
• Figure 3 is a cross-sectional view of an exemplary voltage sustaining semiconductor structure, in accordance with another embodiment of the present invention.
• Figure 4 is a cross-sectional view of an exemplary voltage sustaining semiconductor structure, in accordance with another embodiment of the present invention.
• Figure 5 is a cross-sectional view of an exemplary voltage sustaining semiconductor structure, in accordance with another embodiment of the present invention.
• Figure 6A is a cross-sectional view of an exemplary voltage sustaining semiconductor structure, in accordance with another embodiment of the present invention.
• Figure 6B is a cross-sectional view of an exemplary voltage sustaining semiconductor structure, in accordance with another embodiment of the present invention.
• Figure 7 is a cross-sectional view of an exemplary voltage sustaining semiconductor structure, in accordance with another embodiment of the present invention.
• Figure 8 is a cross-sectional view of an exemplary voltage sustaining semiconductor structure, in accordance with another embodiment of the present invention.
• Figure 9 is a cross-sectional view of an exemplary voltage sustaining semiconductor structure, in accordance with another embodiment of the present invention.
• Figure 10 is a cross-sectional view of an exemplary voltage sustaining structure component, in accordance with another embodiment of the present invention.
• Figure 11 is a cross-sectional view of an exemplary voltage sustaining semiconductor structure, in accordance with another embodiment of the present invention.
• Figure 12A is a top view of a lateral voltage sustaining semiconductor structure, in accordance with another embodiment of the present invention.
• Figures 12B and 12C are various cross-sectional view of the device shown in Figure 12 A.
• Figure 13A is a top view of a lateral voltage sustaining semiconductor structure, in accordance with another embodiment of the present invention.
• Figures 13B, 13C and 13D are various cross-sectional view of the device shown in Figure 13 A.
• Figure 14 is a top view of a lateral voltage sustaining semiconductor structure, in accordance with another embodiment of the present invention.
• Figures 15A and 15B are computer simulations showing equipotential lines at breakdown voltages respectively for a conventional structure, and a structure in accordance with one exemplary embodiment of the present invention.
• Figure 15C shows the electric field along cross-sectional line AA' for the structures shown in Figures 15A-B.
• Figure 15D shows the reverse bias current-vs-voltage characteristics for the structures shown in Figures 15A-B.
• a semiconductor structure in accordance with one exemplary embodiment of the present invention, is characterized, in part, by a relatively high breakdown voltage V B .
• the semiconductor structure includes dielectric layers that have intentionally introduced charge (Q f ). By alternating dielectric and silicon layers that are charge balanced, the structure sustains a higher breakdown voltage for a given voltage sustaining region doping concentration and/or thickness than conventional devices.
• the silicon layers disposed between the dielectric layers are formed using epitaxial growth, implantation or lightly doped epitaxial growth followed by implantation, or the like.
• fixed charge(s) refers to the charge intentionally introduced using processes such as ion implantation, diffusion, deposition and the like in addition to the charge that results as a by-product of fabrication processes.
• interfacial charges i.e., charges in the interface region between the dielectric and the semiconductor region, it is understood that such charges may also be present both in the dielectric as well as in the semiconductor region in which the dielectric regions are formed.
• dielectric layer's charge is balanced by charges in the depletion region.
• the dielectric layer's charge is balanced, in part, by the charges present in an inversion layer that forms at the semiconductor-dielectric layer interface.
• the charge in the dielectric layer in one embodiment, is located at or close to the semiconductor-dielectric interface for maximum effectiveness. In one embodiment, the charge is immobile at typical device operating temperatures. Both negative or positive charges can be used to provide the required charge to balance the depletion charge of the ionized impurities of the semiconductor layer. This results in a more uniform electric field along the voltage sustaining region and therefore a higher breakdown voltage.
• the present invention provides a number of advantages over conventional semiconductor structures that depend primarily on the permittivity and width of a dielectric layer adjacent the semiconductor region.
• the fixed charge provided for charge balance is not a function of the trench width. Therefore, to achieve a higher breakdown voltage, the width of the dielectric layer is only limited by the steps needed to introduce the fixed charge and refill the trench, which enables smaller cell pitches than that which can be obtained by conventional SJ or non-SJ type structures.
• charge balance by using charges in dielectric layers and not p-n junctions or field plates, lower capacitances are achieved.
• the structures of the present invention as described herein are easier and more cost effective to fabricate.
• Both negative or positive charges may be used to provide the required charge balance.
• the charge balance achieved using charges in dielectric layers, in accordance with the present invention provides lower capacitance values than other charge balance techniques.
• a structure, in accordance with the present invention, is easier and more cost effective to fabricate.
• negative charges near the semiconductor-dielectric interface of trenches balance the positive depletion charges in the n-type semiconductor layers to sustain higher voltages.
• the negative dielectric charges may be generated using compound insulating layer , for example, silicon dioxide and aluminum fluoride (AlF 3 or AlF x ) or by implanting ions such as iodine, bromine, chlorine, chromium, aluminum, or other suitable ions.
• positive charges near the semiconductor-dielectric interface of trenches balance the negative depletion charges in p-type semiconductor layers to sustain higher voltages.
• the positive charges may be generated, for example, by implanting positive ions such as cesium or potassium into the dielectric layer that is formed along the walls and the bottom of trenches.
• another dielectric layer that contains positive charges such as silicon-nitride or silicon-oxynitride, is deposited on the dielectric layer that is formed along the walls and the bottom of trenches.
• Another approach of generating positive or negative charges in dielectric layers, for example oxide is diffusion of impurities into the oxide using techniques such as vapor deposition of impurities on the oxide layer followed by a drive-in or annealing step.
• FIG. 2A is a cross-sectional view of a semiconductor structure (referred to herein alternatively as device) 200, in accordance with one embodiment of the present invention.
• Device 200 is shown as including a cathode terminal coupled to an n+ region 202, an anode terminal coupled to p+ region 208, a p region 204 disposed between p+ region 208 and n+ region 202, and a number of trenches 2061, 206 2 ...206 N , collectively and alternatively referred herein below to as trenches 206, formed in a p region 204.
• the p- region positioned to the left of trench 206 1 is identified with reference numeral 204 1
• the p- region positioned to the right of trench 206 2 is identified with reference numeral 204 3
• the p-region positioned between trenches 20O 1 and 206 2 is identified with reference numeral 204 2 .
• FIG 2 Although only two trenches 206 1 , 206 2 are shown in Figure 2, it is understood that a high breakdown voltage device in accordance with the present invention may include any number of trenches 206.
• trenches 206 are shown as extending into n+ region 202.
• Figure 2B is a cross-sectional view of a semiconductor 250, in accordance with another embodiment of the present invention.
• Device 250 is similar to device 200 except that in device 250, an n-type region 252 is disposed between n+ region 202 and p-region 204.
• trenches 206 extend into n-type region 252.
• different instances of similar elements are alternatively identified by similar reference numerals having different indices—the indices appear as subscripts to the reference numerals.
• the two shown instances of trenches 206 are alternatively identified as 206 1 , and 206 2 .
• each trench 206 includes one or more dielectric layers 210.
• the interface region disposed between each dielectric filled trench 206 and p-region 204 includes positive charges. It is understood that the positive charges may reside inside trenches 206, in a transition region (not shown) between the trench and p-type region 204, in the P-region 204, or a combination thereof.
• the positive interface charges present across the opposing surfaces 212] and 212 2 of trenches 206 1 206 2 are sufficient to cause p region 204 2 disposed between these two trenches to partially or fully deplete under reverse bias.
• the partial or full depletion of p- region 204 2 causes the electric field along line xx' shown in Figure 2B to remain relatively uniform under externally applied reverse bias between these two terminals.
• the positive charges are balanced by the charges in the depleted semiconductor voltage sustaining region.
• the positive charges are, in one embodiment, immobile at typical device operating temperatures.
• a semiconductor structure, in accordance with the present invention achieves cell pitches that are smaller and with thinner voltage sustaining layer than many conventional SJ structures. Furthermore, by using charges in dielectric layers in contrast to conventional p-n junctions lower capacitances are achieved and less charge stored under reverse recovery conditions.
• the structures of the present invention are also easier and more cost effective to fabricate.
• p-region 204 2 is depleted due to the positive charges present in the interface regions between trenches 206 and p-region204 2 .
• line xx' crosses through the center of p-region204 2 .
• the positive charges present near the surface 212i are balanced by the negative charges present to the left of line xx' in p-region 204 2 .
• the positive charges present near the surface 212 2 are balanced by the negative charges present to the right of line xx' in p-region204 2 . Accordingly, the electric field along line xx' is nearly uniform.
• p+ region 208, p-region 204 2 , and n+ region 206 2 collectively define a structure that inhibits or otherwise reduces the termination of electric field lines into p-region 204 2 from reverse voltage applied between the cathode and anode terminals of device 200.
• the positive charge may be realized, for example, by implanting positive ions such as cesium or potassium into an oxide layer that covers the trench walls and bottom.
• device 200 is characterized by trenches each having a width of 1 ⁇ m and a depth of 10 ⁇ m.
• the distance between neighboring trenches may be 2 ⁇ m
• p-type region 204 may have a doping concentration of 10 16 atoms/cm 3
• the charge at the interface of trench-semiconductor has a density (Qf/q) of 10 12 cm "2 , where q is the electron charge.
• Qf/q density of 10 16 atoms/cm 3
• q the electron charge.
• a reverse breakdown voltage of 220 volts may be achieved. Without the charge at the interface of trench-semiconductor, the breakdown voltage is only 34 volts.
• Figure 2C is an exemplary top view of device 200 viewed along line yy' shown in Figure 2 A. Three of the trenches 206 1 , 206 2 and 206 3 are shown as being formed in p-region 204, although it is understood that device 200 may include many more trenches that are not shown in this Figure.
• Figure 2D is an exemplary top view of device 200 viewed along line yy' shown in Figure 2A. In accordance with this example, p-region 204 is shown as including nine trenches 206 that have rectangular top views.
• Figure 2E is another exemplary top view of device 200, in accordance with which trenches 206 are shown as having circular top views. It is understood that trenches 206 may have any other top views, such as hexagonal, etc.
• Figure 2F is another exemplary top view of device 200 viewed along line yy'.
• the trenches divide p-region 204 into a multitude of isolated regions, as seen in Figure 2F.
• Figure 3 is a cross-sectional view of an exemplary semiconductor device 300, in accordance with another embodiment of the present invention.
• Device 300 is similar to device 200 except that in device 300, trenches 206 extend to the top surface of P+ region 208.
• Device 300 has breakdown characteristics that are otherwise similar to those of device 200.
• Figure 4 is a cross-sectional view of an exemplary semiconductor device 400, in accordance with another embodiment of the present invention.
• Device 400 is similar to device 200 except that in device 400, the cathode terminal is coupled to an n+-type region 408, and the anode terminal is coupled to a p+ type region 402.
• Device 400 has breakdown characteristics that are otherwise similar to those of device 200.
• Figure 5 is a cross-sectional view of an exemplary semiconductor device 500, in accordance with another embodiment of the present invention.
• Device 500 is similar to device 400 except that in device 500, trenches 206 extend to the top surface of n+ type region 408.
• Device 500 has breakdown and on-resistance characteristics that are otherwise similar to those of device 400.
• FIG. 6A is a cross sectional view of an exemplary semiconductor device 600, in accordance with another embodiment of the present invention.
• multiple trenches 206 are formed in multiple n-type regions (pillars) 602, which in turn, are formed in P-type region (pillar) 204.
• pillars n-type regions
• pillar 204 P-type region
• trench 206 1 is shown as having been formed in n-type pillar 602 1
• trench 206 2 is shown as having been formed in n-type pillar 602 2 .
• the alternating P and N pillars 204, 602 form a Superjunction structure such that the sum of charges in opposing surfaces of neighboring trenches and their depleted N-regions is equal to the negative charges in the depleted P-region.
• the sum of positive charges in the opposing surfaces of trenches 206 1 and 206 2 and the depletion regions of N- regions 602 1 and 602 2 is substantially equal to the sum of negative charges in the depletion region of the P-region 204 disposed between these two N-regions.
• a significant amount of the positive charges are supplied by the fixed trench-semiconductor interface charges, therefore it is easier to achieve charge balance in device 600 using n pillars compared to conventional SJ devices.
• the n pillars may be formed using ion-implantation or vapor phase doping.
• device 600 may provide improved carrier mobility over existing structures
• the trenches are formed in N-regions 602, which in turn, are formed in P-region 204.
• Figure 6B is a cross sectional view of an exemplary semiconductor device 650, in accordance with another embodiment of the present invention In embodiment 650, the trenches are formed in P-type regions 604, which are in turn, formed in N-type region 608.
• Figure 7 is a cross sectional view of an exemplary semiconductor device 700, in accordance with another embodiment of the present invention.
• Device 700 is similar to device 600 except that in device 700, trenches 206 extend to the top surface of p+ region 208.
• Device 700 has breakdown and on-resistance characteristics that are otherwise similar to those of device 600.
• FIG 8 is a cross sectional view of an exemplary semiconductor device 800, in accordance with another embodiment of the present invention.
• Device 800 is similar to device 300 except that in device 800 the trenches are tapered so as to be wider near the top of the trench than they are at the bottom of the trench.
• the trenches are tapered either by design or as a result of the processing steps or equipments, such as etching, that may be used to form the trenches. Accordingly, in device 800, the electric field is higher near the bottom of the trenches 206 than it is near the top of the trenches 206 unless the doping profile of the impurities in the semiconductor is adjusted to eliminate this effect.
• FIG. 9 is a cross sectional view of an exemplary semiconductor device 900, in accordance with another embodiment of the present invention.
• each trench 206 is shown as including two different layers, namely a first layer 902, and a second layer 904.
• Second layer 904 is used either to generate a fixed charge or as a cap layer to ensure that the charges used to deplete p-region 204 are maintained near the surfaces 212 during device fabrication.
• the trenches include materials that include negative charges adapted to deplete the N regions in which the trenches are partly formed.
• Figure 10 is a cross-sectional view of a semiconductor device 1000, in accordance with one embodiment of the present invention.
• Device 1000 is shown as including a cathode terminal coupled to an n+ region 202, an anode terminal coupled to p+ region 208 overlaying p region 1014, and a number of trenches 100O 1 , 1006 2 ...1006 N , collectively and alternatively referred herein below to as trenches 1006, formed in N region 1004 overlaying N+ region 202.
• trenches 1006i, 1006 2 and 1006 2 are shown in Figure 10, it is understood that a high breakdown voltage device in accordance with the present invention may include any number of trenches 1006. Furthermore, although trenches 1006 are shown as extending into n+ region 202, it is understood that in other embodiments, trenches 1006 may not extend into n+ region 202.
• each trench 1006 is shown as including a first dielectric layer 1008, a second layer 1010.
• the second layer 1010 includes a number of materials that may or may not include dielectric materials.
• the interface region disposed between each trench 1006 and the adjacent N region 1004 includes negative charges.
• the negative interface charges present across the opposing surfaces of the neighboring trenches is sufficient to cause the N region 1004 disposed between such neighboring trenches to fully or partially deplete under reverse bias.
• the negative charges present in neighboring trenches 1006j and 106 2 is sufficient to cause the N region 1004 disposed between these two trenches to deplete at reverse bias.
• N region 1004 2 provides an effective semiconductor-insulator-semiconductor structure between the anode and cathode terminals, thereby limiting the electric field lines that would otherwise terminate into the depleted N regions 1004 from an externally applied reverse voltage between these two terminals.
• n-type region 1004 is an epitaxial layer grown over a heavily doped n+ substrate 202.
• the n-type epitaxial layer 1004 is uniformly doped.
• the n-type epitaxial layer 1004 is non-uniformly doped.
• the doping profile can be graded to have higher doping at the substrate relative to the surface or vice versa.
• a first dielectric material 1008 for example, a thermally grown oxide layer, is formed along the bottom and the walls of the trenches.
• the first dielectric material ranges in thickness from about 2 nm to about 200 nm.
• the thickness of the first dielectric material may be about 30 nm.
• Trenches 1006 are shown as including a second material 1010, which may include one or more materials/compound layers, in the interior regions of the trenches and enclosed within the first dielectric material 1008.
• Second material 1010 which may be aluminum fluoride, provides negative charges at the interface between the AlF x layer and the first dielectric material 1008.
• FIG 11 is a cross-sectional view of a semiconductor device 1100, in accordance with another embodiment of the present invention.
• Device 1100 is similar to device 1000 except that in device 1100, each trench 1006 is shown as including a first dielectric layer
• each third layer 1024 includes a number of materials that may or may not include dielectric materials.
• Embodiment 1100 is otherwise similar to embodiment 1000.
• each trench 1006 includes a first layer 1020 that is a dielectric layer, a second layer 1022, and a third layer 1024 that is a dielectric layer.
• First layer 1020 is formed on the walls and bottom of the trenches.
• Second layer 1022 which may include more than one material — is formed so as to be enclosed within the first layer 1020.
• Third layer 1024 is formed so as to be enclosed within second layer 1022.
• third layer 1024 is formed from the same material as the first layer 1020.
• the first and second dielectric layers are formed using different materials.
• Disposing layer 1022 which may include, for example, aluminum fluoride, between the two dielectric layers 1020 and 1024 provides negative charges at the interfaces between the dielectric layers 1020, 1024 and layer 1022.
• the various n+, p+, n and p-type layers of device 1100 are formed using conventional fabrication processes such as implantation, diffusion, annealing, and the like.
• FIG. 12A is a simplified top view of a lateral high voltage semiconductor device 1200, in accordance with another embodiment of the present invention.
• Device 1200 is shown as including a cathode terminal coupled to an n+ region 202, an anode terminal coupled to p+ region 208, a p-type region 204 disposed between p+ region 208 and n+ region 202, and a number of trenches 206i, 206 2 ...206 N , collectively and alternatively referred herein below to as trenches 206, formed in a p region 204.
• trenches 206i, 206 2 and 206 3 are shown in Figure 12A, it is understood that a high breakdown voltage device in accordance with the present invention may include any number of trenches 206.
• each trench 206 includes one or more dielectric layers 210.
• positive charges are intentionally introduced into trenches 206. Such charges may reside in the trenches, in a transition region between the trench and p-type region 204, in the P-region 204, or a combination thereof, and are collectively and alternatively referred to herein as interface charges. Such positive interface charges present across the opposing surfaces of the trenches is sufficient to cause the p region 204 disposed between such two trenches to partially or fully deplete at a reverse bias.
• the charges present near opposing surfaces 212 1 and 212 2 of trenches 206], 206 2 are sufficient to cause p-type region 204 2 disposed between these two trenches to partially or fully deplete at a reverse bias.
• the charges present near opposing surfaces 212 3 and 212 4 of trenches 206 2 , 206 3 are sufficient to cause p-type region 204 disposed between these two trenches to partially or fully deplete at a reverse bias.
• the partial or full depletion of p- type regions 204 at a reverse bias causes the electric field along, for example, a plane perpendicular to line AA' positioned at the midpoint of opposing surfaces 212] and 212 2 to remain relatively uniform under an externally applied reverse bias between the cathode and anode terminals.
• the positive interface charges are balanced by the charges in the depleted charge of the P-type regions 204.
• the positive charges are, in one embodiment, immobile at typical device operating temperatures.
• Figures 12B is a simplified cross-sectional view of structure 1200 along lines AA'. Referring to Figure 12B, p-type region 204 is fully or partially depleted under a reverse bias. Dielectric layer 220 covers the entire structure and is used to passivate the semiconductor device.
• Figures 12C is a simplified cross-sectional view of structure 1200 along lines BB' showing trench 20O 3 and various other regions of device 1200.
• Figure 13A is a simplified top view of a lateral high voltage semiconductor device 1300, in accordance with another embodiment of the present invention.
• Device 1300 is shown as including a cathode terminal coupled to an n+ region 202, an anode terminal coupled to a n+ region 208, an n-type region 1302 disposed between n+ regions 208, 202, and a number of trenches 2061, 206 2 . ..206 N , collectively and alternatively referred hereinbelow to as trenches 206, formed in n-type region 1302.
• FIG. 13 A is a cross- sectional view of structure 1300 along lines AA'. Referring to Figure 13B, n-type region 1302 is fully or partially depleted under a reverse bias. Dielectric layer 220 covers the entire structure and is used to passivate the semiconductor device.
• FIGS 13C and 13D are cross-sectional views of semiconductor device 1300 along lines BB' and CC.
• Device 1300 is similar to device 1200 except that in device 1300, each trench 1006 is shown as including a first dielectric layer 1020, a second layer 1022, and a third layer 1024 ( Figure 13D).
• the trenches are formed so as to include negative charges to deplete N-region 1302.
• each third layer 1024 includes a number of materials that may or may not include dielectric materials.
• each trench 1006 includes a first layer 1020 that is a dielectric layer, a second layer 1022, and a third layer 1024 that is a dielectric layer.
• First layer 1020 is formed on the walls and bottom of the trenches.
• Second layer 1022 which may include more than one material—is formed so as to be enclosed within the first layer 1020.
• Third layer 1024 is formed so as to be enclosed within second layer 1022.
• third layer 1024 is formed from the same material as the first layer 1020.
• the first and second dielectric layers are formed using different materials.
• Disposing layer 1022 which may include, for example, aluminum fluoride, between the two dielectric layers 1020 and 1024 provides negative charges at the interfaces between the dielectric layers 1020, 1024 and layer 1022.
• the various layers of device 1300 are formed using conventional fabrication processes such as implantation, diffusion, annealing, and the like.
• Figure 14 is a simplified top view of a lateral high voltage semiconductor device 1400, in accordance with another embodiment of the present invention.
• Device 1400 is similar to device 1200 except that in device 1400 the trenches are tapered so as to be have wider widths near the anode terminal than near the cathode terminal to compensate for the depletion charge generated in the p-substrate.
• Figures 15A and 15B show the equipotential lines at breakdown voltages respectively for a conventional structure 1510, and a structure 1520 in accordance with one exemplary embodiment of the present invention. Each iso-contour represents 10 volts in this simulation.
• Structure 1510 includes a semiconductor region 1502 disposed between the diode's associated anode and cathode terminals.
• Structure 1520 is shown as including trenches 206. Positive interface charges having a charge density (Qf/q) of 1x10 12 cm "2 (q is the electron charge) are present at the interface of the trenches 206 and P-region 204, in accordance with the present invention.
• the breakdown voltage of conventional structure 1510 is approximately 34 volts, whereas the breakdown voltage of structure 1520 of the present invention is 220 volts.
• Figure 15C shows the electric field along cross-sectional line AA' for the structures shown in Figures 15A-B.
• the electric field distribution for structure 1510 is shown using plot 1530.
• the significantly improved electric field distribution for structure 1520 is shown using plot 1535.
• the partial or full depletion of p-type regions 204 at a reverse bias causes the electric field along cross-sectional line AA' positioned at the midpoint of opposing surfaces 212 and 212 to remain relatively uniform under an externally applied reverse bias between the cathode and anode terminals.
• the electric field from ionized dopants in region 1502 terminate at the anode, thereby causing the electric field to have a triangular profile.
• Figure 15D shows the reverse bias current- v- voltage characteristics for structures 1510 (plot 1540) and 1520 (plot 1545). As is shown, the breakdown voltage of structure 1510 is 34 volts, and the breakdown voltage of structure 1520 is 220 volts.

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