JP2022502863A - 荷電平衡(cb)トレンチ−金属酸化物半導体−電界効果トランジスタ(mosfet)デバイスの製作技法 - Google Patents
荷電平衡(cb)トレンチ−金属酸化物半導体−電界効果トランジスタ(mosfet)デバイスの製作技法 Download PDFInfo
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Abstract
Description
Claims (23)
- 荷電平衡(CB)トレンチ−金属酸化物半導体(MOS)デバイスであって、
第1エピタキシャル(エピ)層内に定められ、第1導電型を有する荷電平衡(CB)層であって、第2導電型を有する複数の荷電平衡(CB)領域を含む、CB層と、
第2エピ層内に定められ、前記第1導電型を有し、前記CB層上に配置されたデバイス層であって、
前記第1導電型を有し、前記第2エピ層の上面に配置されたソース領域と、
前記第2導電型を有し、前記ソース領域の下に配置されたベース領域と、
前記第2エピ層の上面から前記ベース領域より下の深さまで達するトレンチ構造と、
前記第2導電型を有し、前記トレンチ構造の底面に少なくとも部分的に配置された防御領域と、
を含む、デバイス層と、
前記第2導電型を有し、前記CB層の複数のCB領域間を延び、前記複数のCB領域を、前記第2導電型を有する前記デバイス層の少なくとも1つの領域に電気的に結合する、荷電平衡(CB)バス領域と、
を備える、荷電平衡(CB)トレンチ−金属酸化物半導体(MOS)デバイス。 - 請求項1記載のCB MOSデバイスにおいて、前記CBバス領域が、前記ソース領域上に配置されたソース・コンタクトからのオーム接触を介して、前記複数のCB領域に電気的に結合する、デバイス。
- 請求項1記載のCB MOSデバイスにおいて、前記防御領域が、前記トレンチ構造の幅よりも大きい幅を有し、前記トレンチ構造の深さが、前記トレンチ構造の幅よりも大きい、デバイス。
- 請求項1記載のCB MOSデバイスにおいて、前記CB MOSデバイスと関連付けられたピッチが、2.5マイクロメートル(μm)および4μmの間であり、前記トレンチ構造が1μmおよび1.5μmの範囲を取る幅を有する、デバイス。
- 請求項1記載のCB MOSデバイスにおいて、前記ベース領域が、前記CB MOSデバイスのアクティブ・エリア内に配置される、デバイス。
- 請求項1記載のCB MOSデバイスにおいて、前記CBバス領域が、第2注入領域と実質的に整合された第1注入領域を含む、デバイス。
- 請求項1記載のCB MOSデバイスにおいて、前記CBバス領域が、前記ソース領域上に配置されたソース・コンタクトからのオーム接触を介して、前記複数のCB領域に電気的に結合する、デバイス。
- 請求項1記載のCB MOSデバイスであって、前記ベース領域の下に配置されたエンハンス・ドーピング領域を備える、デバイス。
- 請求項1記載のCB MOSデバイスにおいて、前記CBバス領域が、前記複数のCB領域間を延び、前記複数のCB領域を、前記CB MOSデバイスのアクティブ・エリア内にある本体領域に電気的に結合する、デバイス。
- 請求項1記載のCB MOSデバイスにおいて、前記CBバス領域が、前記CB MOSデバイスのオーバーヘッド・エリア内に形成され、同様に前記CB MOSデバイスのオーバーヘッド・エリア内に形成された本体領域に電気的に結合される、デバイス。
- 請求項1記載のCB MOSデバイスにおいて、前記第1導電型がp−型ドーパントによって作られる、デバイス。
- 請求項1記載のCB MOSデバイスであって、追加のトレンチ構造を備える、デバイス。
- 請求項1記載のCB MOSデバイスにおいて、前記防御領域が前記トレンチ構造の下に部分的にのみ配置される、デバイス。
- 荷電平衡(CB)トレンチ−金属酸化物半導体(MOS)デバイスの製造方法であって、
複数の荷電平衡(CB)領域を、第1導電型を有する第1エピタキシャル(エピ)層内に注入することによって、荷電平衡(CB)層を前記第1エピ層から形成するステップと、
前記CB層上に配置された第2エピ層からデバイス層を形成するステップと、
前記デバイス層の上方に高エネルギ注入マスクを形成するステップと、
第2導電型を有し、前記デバイス層およびCB層の一部に貫入する深さを有する荷電平衡(CB)バス領域を形成するために注入を実行するステップであって、前記CBバス領域が、前記複数のCB領域を、前記第2導電型を有する前記デバイス層の領域に電気的に結合する、ステップと、
を含む、荷電平衡(CB)トレンチ−金属酸化物半導体(MOS)デバイスの製造方法。 - 請求項14記載の方法において、前記深さが1マイクロメートル(μm)よりも大きい、方法。
- 請求項14記載の方法において、前記CBバス領域が、前記CB MOSデバイスのアクティブ・エリア内に形成される、方法。
- 請求項14記載の方法であって、前記CB MOSデバイスと関連付けられたオーバーヘッド・エリア内に、前記CBバス領域を形成するステップを含む、方法。
- 請求項14記載の方法において、前記第1導電型がp−型ドーパントから作られる、方法。
- システムであって、
荷電平衡(CB)トレンチ−金属酸化物半導体(MOS)デバイスであって、
第1導電型を有する第1エピタキシャル(エピ)層内に定められた荷電平衡(CB)層であって、第2導電型を有する複数の荷電平衡(CB)領域を含む、CB層と、
前記CB層上に配置された第2エピ層内に定められたデバイス層上に配置されたソース・コンタクトと、
を含む、荷電平衡(CB)トレンチ−金属酸化物半導体(MOS)デバイスと、
前記CBトレンチ−MOSデバイスを含むアクティブ・エリアと、
前記第2導電型を有し、前記アクティブ・エリアに隣接して配置されたオーバーヘッド・エリアと、
前記第2導電型を有し、前記第1エピ層と前記第2エピ層との間を延び、前記CB層の複数のCB領域を前記ソース・コンタクトに、前記第2導電型を有する前記デバイス層の領域を介して、電気的に結合する荷電平衡(CB)バス領域であって、前記アクティブ・エリア、前記オーバーヘッド・エリア、またはその組み合わせの内部に配置される、CBバス領域と、
を備える、システム。 - 請求項19記載のシステムにおいて、前記デバイス層が、
第1導電型を有し、前記第2エピ層の上面に配置されたソース領域と、
前記第2導電型を有し、前記ソース領域に隣接して配置されたベース領域と、
前記第2エピ層の上面から、前記ベース領域の下の深さまで達し、ゲートを含むトレンチ構造と、
前記第2導電型を有し、前記トレンチ構造の底面に配置された防御領域と、
を含む、システム。 - 請求項19記載のシステムにおいて、前記CBバス領域、前記ベース領域、および前記防御領域が、前記ソース・コンタクトに対するオーム接続を有する、システム。
- 請求項19記載のシステムにおいて、前記第2導電型が、p−型ドーパントを使用する注入によって作られる、システム。
- 請求項19記載のシステムにおいて、前記CBトレンチ−MOSデバイスが、前記アクティブ・エリア内に配置された防御領域を含む、システム。
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