CN101689562A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN101689562A
CN101689562A CN200880001945A CN200880001945A CN101689562A CN 101689562 A CN101689562 A CN 101689562A CN 200880001945 A CN200880001945 A CN 200880001945A CN 200880001945 A CN200880001945 A CN 200880001945A CN 101689562 A CN101689562 A CN 101689562A
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zone
semiconductor structure
type
area
dielectric regions
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CN101689562B (zh
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M·N·达维希
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MaxPower Semiconductor Inc
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MaxPower Semiconductor Inc
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Abstract

一种半导体结构包括多个半导体区域，一对介电区域以及一对终端。该结构的第一和第二区域分别被耦联至第一和第二终端。该结构的第三区域设置在第一和第二区域之间。该介电区域延伸进第三区域内。存在于第三区域的掺杂杂质的浓度以及介电区域间的距离限定了该结构的电特性。该结构的电特性与介电区域的宽度的宽度无关。第一和第二区域具有相反的导电类型。该结构可选地包括延伸入第三区域内并且包围部分该对介电区域的第四区域。介电区域和第四区域之间的界面区包括有意导入电荷。

Description

半导体器件
相关申请的交叉引用
[01]本申请声明要求基于第35部美国法典119(e)节下的于2007年1月9日提交的名称为“Power MOS Transistor-功率MOS晶体管”，申请号为60/879,434的美国临时专利申请的权益，将其内容通过引用方式整体并入本文。
技术领域
[02]本发明涉及电子器件，并且更具体地涉及适用于维持高电压的半导体器件。
背景技术
[03]在电子系统中，经常需要维持相对高的电压通过一对节点。半导体p-n结二极管被广泛使用在反向偏置模式下来维持高电压。为了维持高击穿电压穿过p-n结，要求以下轻微掺杂区域：其相对厚且形成电压维持层。这种p-n结在许多半导体器件(诸如MOSFET，IGBT和JFET)中提供相对较高的击穿电压。而且，这种半导体器件特别需要在连通状态下具有相对低的导通电阻(Ron)以及在反向偏置状态下具有相对高的击穿电压VB。众所公知的，同时具有高击穿电压VB以及低Ron带来许多挑战性的任务。在常规器件里，用以增加击穿电压的诸如掺杂密度或者层厚度的设计参数会导致导通电阻增大，反之亦然。
[04]一种用于达到同时具有低导通电阻以及高击穿电压的公知器件通常称为超级结(SJ)器件。如图1所示，SJ器件(结构)经常包括许多交错的电荷平衡式p型和n型层或者柱状物。在SJ结构中，希望通过在给定单位面积内集聚同样多的柱状物或者单元(cells)来降低特定的导通电阻，RSP，其被定义为Ron＊A，其中的A是器件面积。
[05]在SJ结构中，n型和p型柱状物的宽度对该结构的单元节距和按比例缩小都有限制。还有许多与制造SJ结构有关的缺陷，诸如需要生长多重外延层以及执行许多注入和扩散步骤。对能够容易按比例缩小和更容易制造的并具有高击穿电压、低RSP、低电容和低反向恢复电荷(Orr)的半导体器件的需求一直持续存在。
发明内容
[06]一种半导体结构，根据本发明的一个实施方式，部分地包括，多个半导体区域，至少一对介电区域和一对终端。半导体结构的第一和第二区域分别耦联至该第一和第二终端。半导体结构的第三区域具有单一的导电型并且被设置在第一和第二区域之间。该介电区域延伸入第三区域内。在第三区域内的掺杂杂质的浓度以及介电区域之间的距离限定该半导体结构的电特性。该半导体结构的电特性与介电区域的宽度无关。第一和第二区域具有相反的导电类型。
[07]在一个实施方式中，介电区域延伸入第一和第二区域内。在一个实施方式中，在第三区域内沿着平行于介电区域表面的线的掺杂杂质的积分密度范围从大约1×1012/cm2到大约5×1012/cm2。在一个实施方式中，每块介电区域进一步包括第二材料。在一个实施方式中，在每块介电区域内的第二材料部分地包括铝氟化物。在一个实施方式中，每块介电区域进一步部分地包括作为介电材料的第三材料。在一个实施方式中，在每个介电区域内的第二和第三材料为同一种材料。
[08]在一个实施方式中，第一和第二区域分别为P+型和n+型区域，并且第一和第二终端分别为阳极和阴极终端。在一个实施方式中，第三区域是p型区域。在另一个实施方式中，第三区域是n型区域。在一个实施方式中，第三区域形成在第二区域上方，并且所述第一区域形成在第二区域上方。在一个实施方式中，介电区域彼此隔离。
[09]在一个实施方式中，半导体结构进一步部分地包括被设置在第二和第三区域之间的第四区域。第二和第四区域具有相同的导电类型。
[10]在一个实施方式中，第一和第二区域分别是n+型和p+型区域，并且第一和第二终端分别为阴极和阳极终端。在一个实施方式中，第三区域是p型区域。在另一个实施方式中，第三区域是n型区域。在一个实施方式中，第三区域形成在第二区域上方，并且第一区域形成在第三区域上方。在一个实施方式中，第三区域形成在第二区域上方，并且第一区域形成在第三区域上方。在一个实施方式中，每个介电区域被锥形化，以便使得靠近介电区域的一端与另一端相比具有更大的宽度。
[11]在一个实施方式中，沿着形成有半导体结构的半导体衬底的同一表面上形成第一、第二和第三区域。在一个这种实施方式中，半导体结构包括在其中形成第二区域的第四区域。在一个这种实施方式中，第三区域靠近第一和第四区域。在一个这种实施方式中，第一区域是p+型区域，第二区域是n+型区域，第三区域是p型区域并且第四区域是n型区域。在另外一个这种实施方式中，第一区域是p+型区域，第二区域是n+型区域，第三区域是n型区域以及第四区域是p型区域。
[12]一种半导体结构，根据本发明的另一个实施方式，部分地包括多个半导体区域，至少一对介电区域以及一对终端。半导体结构的第一和第二区域分别耦联至第一和第二终端。第三和第四区域设置在第一和第二区域之间并靠近第一和第二区域。介电区域延伸入第三区域内。第四区域延伸入第三区域内，具有与第三区域相反的导电类型，并且包围至少第一和第二介电区域的部分区域。在第三区域内存在的掺杂杂质的浓度以及介电区域之间的距离限定该半导体结构的电特性。该半导体结构的电特性与介电区域宽度的宽度无关。第一和第二区域具有相反的导电类型。介电区域和第四区域的界面区包含有意感应电荷。
[13]在一个实施方式中，介电区域延伸入第一和第二区域内。在一个实施方式中，在第三区域内沿着平行于介电区域表面的线的掺杂杂质的积分密度范围从大约1×1012/cm2到大约5×1012/cm2。在一个实施方式中，每一介电区域进一步包括第二材料。在一个实施方式中，每一介电区域内的第二材料部分地包括铝氟化物。在一个实施方式中，每一介电区域进一步部分地包括第三材料，所述第三材料为介电材料。在一个实施方式中，在每一介电区域内的该第二和第三材料为同一种材料。
[14]在一个实施方式中，第一和第二区域分别是p+型和n+型区域，并且第一和第二终端分别是阳极和阴极终端。在一个实施方式中，第三区域是p型区域。在另一个实施方式中，第三区域是n型区域。在一个实施方式中，第三区域形成在第二区域上方，并且所述第一区域形成在第三区域上方。在一个实施方式中，介电区域彼此隔离。
[15]在一个实施方式中，半导体结构进一步部分地包括，设置在第二和第三区域之间的第四区域。第二和第四区域具有相同的导电类型。
[16]在一个实施方式中，第一和第二区域分别是n+型和p+型区域，并且第一和第二终端分别是阴极和阳极终端。在一个实施方式中，第三区域是p型区域。在一个实施方式中，第三区域是p型区域。在另一个实施方式中，第三区域是n型区域。在一个实施方式中，第三区域形成在第二区域上方，第一区形成在第三区域上方。在一个实施方式中，第三区域形成在第二区域上方，并且第一区域形成在第三区域上方。在一个实施方式中，每块介电区域被锥形化，以便靠近介电区域的一端与另一端相比具有更大的宽度。
[17]在一个实施方式中，在形成有半导体结构的半导体衬底的同一表面上形成第一、第二和第三区域。在一个这种实施方式中，半导体结构包括在其中形成第二区域的第四区域。在一个这种实施方式中，第三区域靠近第一和第四区域。在一个这种实施方式中，第一区域是p+型区域，第二区域是n+型区域，第三区域是p型区域，并且第四区域是n型区域。在另外的这种实施方式中，第一区域是p+型区域，第二区域是n+型区域，第三区域是n型区域，以及第四区域是p型区域。
附图说明
[18]图1是现有技术中公知的超级结器件的横截面视图。
[19]图2A是根据本发明的一个实施方式的示例性电压维持式半导体结构的横截面视图。
[20]图2B是根据本发明的一个实施方式的示例性电压维持式半导体结构的横截面视图。
[21]图2C，2D，2E，2F是根据本发明的一个实施方式的图2A所示器件的示例性俯视示意图。
[22]图3是根据本发明另一实施方式的示例性电压维持式半导体结构的横截面视图。
[23]图4是根据本发明另一实施方式的示例性电压维持式半导体结构的横截面视图。
[24]图5是根据本发明另一实施方式的示例性电压维持式半导体结构的横截面视图。
[25]图6A是根据本发明另一实施方式的示例性电压维持式半导体结构的横截面视图。
[26]图6B是根据本发明另一实施方式的示例性电压维持式半导体结构的横截面视图。
[27]图7是根据本发明另一实施方式的示例性电压维持式半导体结构的横截面视图。
[28]图8是根据本发明另一实施方式的示例性电压维持式半导体结构的横截面视图。
[29]图9是根据本发明另一实施方式的示例性电压维持式半导体结构的横截面视图。
[30]图10是根据本发明另一实施方式的示例性电压维持式半导体结构的横截面视图。
[31]图11是根据本发明另一实施方式的示例性电压维持式半导体结构的横截面视图。
[32]图12A是根据本发明另一实施方式的横向电压维持式半导体结构的俯视图。
[33]图12B和12C是图12A所示器件的不同的横截面视图。
[34]图13A是根据本发明另一实施方式的横向电压维持式半导体结构的俯视图。
[35]图13B，13C和13D是图13A所示器件的不同的横截面视图。
[36]图14是根据本发明的另一实施方式的横向电压维持式半导体结构的俯视图。
[37]图15A和15B是分别显示的常规结构和根据本发明一个示例性实施方式的结构的击穿电压等位线的电脑仿真图。
[38]图15C示出沿着图15A-B所示结构中的横截线AA’的电场图。
[39]图15D示出在图15A-B所示结构的反偏电流对电压的特性图。
具体实施方式
[40]一种半导体结构，根据本发明的一个示例性实施方式，其部分特征在于具有相对高的击穿电压VB。该半导体结构包括具有有意导入电荷的介电层(Qf)。通过电荷平衡的交替的介电层和硅层，该结构对于给定的电压维持区域掺杂浓度和/或厚度维持比常规器件更高的击穿电压。在一些实施方式中，使用外延生长、注入或者轻度掺杂式外延生长，然后进行注入等形成设置在介电层之间的硅层。对于同样掺杂和厚度的外延层或者电压维持层，由本发明实施方式提供的器件性能超过了一维硅击穿电压限制。
[41]在以下描述中，固定电荷除指在制造过程中产生的副产品电荷外，还指使用诸如离子注入、扩散、沉积等工艺有意导入的电荷。此外，通常当参考以下关于界面的电荷(即介电区域和半导体区域之间界面区内的电荷)时，人们理解这种电荷也可以存在于介电区域以及在其中形成介电区域的半导体区域中。
[42]在反向偏置下，介电层的电荷由耗尽区域的电荷平衡。在零偏压下，介电层的电荷部分由在半导体-介电层界面形成的逆变层中的电荷平衡。在一个实施方式中，介电层中的电荷位于或者靠近半导体-介电的界面来获得最大效果。在一个实施方式中，在典型的器件运转温度下电荷是固定的。负电荷和正电荷都可以用来提供所需电荷来平衡半导体层中的电离杂质中的耗尽电荷。这使得沿电压维持区域的电场更均匀，从而使得击穿电压更高。
[43]本发明主要依靠靠近半导体区域的介电层的介电常数和宽度来提供很多优于常规半导体结构的优点。根据本发明，为电荷平衡而提供的固定电荷不是开槽宽度的函数。因此为了获得更高的击穿电压，介电层的宽度仅受到引入固定电荷和回填槽所需引入的步骤的限制，其使得与通过常规SJ或非SJ型结构能够获得的单元节距相比具有更小的单元节距。此外，通过利用介电层而非p-n结或者场板中的电荷来实现电荷平衡，可以获得较低的电容。如本文所述的，本发明的结构制造起来更简单且成本更低。
[44]正电荷或者负电荷都可以用于提供所需电荷平衡。根据本发明，使用介电层中的电荷获得的电荷平衡与其它的电荷平衡技术相比，提供更低的电容值。根据本发明的结构制造起来更简单且成本更低。
[45]在一些实施方式中，在槽的半导体-介电界面附近的负电荷平衡n型半导体层内的正耗尽电荷以维持更高的电压。可以利用复合绝缘层产生负介电电荷，例如二氧化硅和铝氟化物(AlF3或者AlFX)，或者通过注入例如碘、溴、氯、铬、铝，或者其它适合的离子产生负介电电荷。利用二氧化硅和铝氟化物(AlF3或者AlFX)的复合绝缘层产生负电荷的效果已经经实验核实，其中发现负界面电荷是分数x的强函数。在又一实施方式中，在槽的半导体-介电界面附近的正电荷平衡p型半导体层的负耗尽电荷来维持更高的电压。例如正电荷可通过将如铯或钾的正离子注入沿着槽壁和槽底部形成的介电层中而产生。可选地，包含有正电荷(诸如硅氮化物或者硅氧氮化物)的另一介电层被沉积在沿着槽壁和槽底部形成的介电层上。在例如氧化物的介电层中产生正电荷或者负电荷的另一种方法是利用诸如在氧化物层上气相沉积杂质，然后进行推入或者退火步骤的技术将杂质扩散入氧化物中。
[46]图2A是根据本发明的一个实施方式的半导体结构(在这里可选地称为器件)200的横截面视图。如图所示，器件200包括耦联至n+区域202的阴极终端，耦联至p+区域208的阳极终端，被设置在p+区域208和n+区域202之间的p区域204，以及形成在p区域204中的很多槽2061，2062…206N，它们共同且可选地在以下被表示为槽206。为了简明起见，设置在槽2061左边的p区域采用参考数字2041识别，设置在槽2062右边的p区域采用参考数字2043识别，同时设置在槽2061和2062之间的p区域采用参考数字2042识别。尽管在图2中仅示出两个槽2061、2062，但是据此理解根据本发明的高击穿电压式器件应该包括许多槽206。此外，如图中所示，槽206延伸入n+区域202内。
[47]图2B是根据本发明另一实施方式的半导体250的横截面视图。器件250与器件200相似，不同之处是：在器件250中，n型区域252被设置在n+区域202和p区域204之间。在这种实施方式中，槽206延伸进n型区域252中。在下文中，相似元件的不同实例可选地采用具有不同指数(indices)的相似参考数字识别--该指数作为参考数字的下标。例如，两个所示的槽206的实例可选地采用2061，和2062识别。
[48]在一个实施方式中，每个槽206包括一个或多个介电层210。根据本发明，设置在每个介电填充槽206和p区域204之间的界面区域包含正电荷。据此理解正电荷居于槽206中，或者在槽和p型区域204之间的过渡区域中(未示出)，或者在P区域204中，或者它们之间的组合中。根据本发明，横跨槽20612062的相对表面2121和2122存在的正界面电荷足够导致设置在这两个槽之间的p区域2042部分地或者全部地在反向偏置状态下耗尽。p区域2042部分地或者全部地耗尽使得沿着图2B中示出的线xx′的电场在这两个终端之间外部施加反向偏置的情况下保持相对均匀。
[49]在反向偏置的条件下，正电荷由耗尽半导体电压维持区域的电荷平衡。如上所述，在一个实施方式中，该正电荷在典型的器件运转温度下是固定的。根据本发明的半导体结构获得了更小的单元节距以及具有比很多常规SJ结构更薄的电压维持层。此外，通过使用介电层电荷获得了相比常规p-n结更低的电容以及在反向恢复条件下储存更少的电荷。本发明的结构制造起来也更简单且成本更低。
[50]参见图2A，p区域2042被槽206和p区域2042间的界面区域中存在的正电荷耗尽。假设线xx′穿过p区域2042的中心。从而，在表面2121附近存在的正电荷被在p区域内至2042线xx′左边存在的负电荷平衡。类似地，在表面2122内存在的正电荷被在p区域内至2042线xx’右边存在的负电荷平衡。因此，沿着线xx′的电场基本均匀。结果，p+区域208，p区域2042，以及n+区域2062共同限定一结构，该结构抑制或者以其它方式减少电场线从施加在器件200的阴极和阳极终端之间的反向电压终止进入p区域2042。获得正电荷的方法可以是，例如，通过将诸如铯或者钾的正离子注入覆盖槽壁和槽底部的氧化物层中。在一个实例中，器件200的特征是每个槽都具有1μm宽度和10μm深度。在这种实例中，相邻槽之间的距离可以是2μm，p型区域204可以具有1016个原子/cm3的掺杂浓度，并且在槽-半导体界面的电荷的密度为(Qf/q)1012cm-2，其中q是电子电荷。在这种实施方式中，可以获得220伏的反向击穿电压。在没有槽-半导体界面的电荷的情况下，击穿电压仅为34伏。
[51]图2C是沿着图2A所示线yy’显示的器件200的示例性俯视示意图。图中所示的三个槽2061，2062以及2063形成在p区域204内，尽管据此可以理解器件200可能包括更多的该图中未示的槽。图2D是沿着图2A所示线yy’显示的器件200的示例性俯视示意图。根据该实例，如图所示，p区域204包括俯视图呈矩形的九个槽206。图2E是根据显示为具有圆形俯视图的槽206的另一器件200的示例性俯视示意图。据此理解槽206可以包括任一其它俯视图，例如六边形等等。
[52]图2F是沿着线yy’显示的器件200的另一示例性俯视示意图。根据这个实例，如图2F所示，槽将p区域204分割为众多隔离区域。
[53]图3是根据本发明的另一个实施方式的示例性半导体器件300的横截面视图。器件300与器件200相似，除了在器件300中，槽206延伸入P+区域208的上表面。器件300具有击穿特性并且其其它特性与器件200中的那些特性相似。
[54]图4是根据本发明的另一实施方式的示例性半导体器件400的横截面视图。器件400与器件200相似，除了在器件400中，阴极终端耦联至n+型区域408，并且阳极终端耦联至p+型区域402。器件400具有击穿特性并且其其它特性与器件200中的那些特性相似。
[55]图5是根据本发明的另一实施方式的示例性半导体器件500的横截面视图。器件500与器件400相似，除了在器件500中，槽206延伸至n+型区域408的上表面。器件500具有击穿特性和导通电阻特性并且其其它特性与器件400中的那些特性近似。
[56]图6A是根据本发明的另一实施方式的示例性半导体器件600的横截面视图。在器件600中，多个槽206形成在多个n型区域(柱状物)602中，依次地，形成在p型区域(柱状物)204中。例如，如图所示，槽2061已形成在n型柱状体6021内，并且槽2062形成在n型柱状体6022内。交替的P和N型柱状体204，602形成超级结结构，从而在相邻槽和它们的耗尽N区域的相对表面上的电荷总数与耗尽P区域内的负电荷相等。例如，在槽2061和2062以及N区域6021和6022的耗尽区域的相对表面上的正电荷总数与被设置在这两个N区域间的P区域204的负电荷总数基本相等。在器件600中，相当数量的正电荷是由槽-半导体界面的固定电荷所供给，因此相比于常规SJ器件很容易通过n柱状体在器件600中获得电荷平衡。可以使用离子注入或者气相掺杂形成该n柱状体。此外，器件600还可以提供比现有的结构改良的载流子迁移率。如图6A所示，槽依次在N区域602和P区域204内形成。图6B是根据本发明的另一实施方式的示例性半导体器件650的横截面视图。在实施方式650中，槽依次形成在P型区域604和N型区域608中。
[57]图7是根据本发明的另一实施例的示例性半导体器件700的横截面视图。器件700与器件600相似，除了在器件700中，槽206延伸至P+区域208的上表面。器件700具有击穿和导通电阻特性并且其它特性与器件600相似。
[58]图8是根据本发明的另一实施例的示例性半导体器件800的横截面视图。器件800与器件300类似，除了在器件800中，槽被锥形化以使得槽顶部附近的宽度比槽底部的更宽。对槽的锥形化或通过设计或由处理步骤或者处理装备的结果实现，例如可用于形成槽的蚀刻技术。因此，在器件800中，在槽206的底部附近的电场比槽206的顶部附近的电场更高，除非调节杂质在半导体中的掺杂分布以消除该效应。
[59]图9是根据本发明的另一实施方式的示例性半导体器件900的横截面视图。在器件900中，所示的每个槽206包括两个不同的层，即第一层902，和第二层904。第二层904用于产生固定电荷或者作为保护层以确保用于耗尽P区域204的电荷在器件制造过程中被维持在表面212附近。
[60]根据本发明的一些实施例，槽包括具有适用于耗尽其内形成部分槽的N区域内的负电荷的材料。图10是根据本发明的一个实施方式的半导体器件1000的横截面视图。所示的器件1000包括耦联至n+区域202的阴极终端，耦联至位于p区域1014上的p+区域208的阳极终端，以及许多形成在覆盖N+区域202的N区域1004内的槽10061，10062…1006N，这些槽共同地且可选地在下文采用槽1006表示。尽管在图10中仅示出三个槽10061，10062和10062，但是据此应该理解根据本发明的高击穿电压式器件可以包括许多槽1006。此外，尽管槽1006显示延伸入n+区域202内，但是据此应该理解在其它实施方式中，槽1006也可以不延伸入n+区域202内。
[61]在图10所示的示例性实施方式中，所示的每个槽1006包括第一介电层1008，第二层1010。在一个实施例中，第二层1010包括许多可能包括或者不包括介电材料的材料。如图10所示，设置在每个槽1006和相邻的N区域1004间的界面区包含负电荷。进一步根据本发明，横跨相邻槽的相对表面存在的负界面电荷足够导致被设置在这种相邻槽间的N区域1004在反向偏置的情况下全部地或者部分地耗尽。例如，在相邻槽10061和1062的负电荷足够导致在这两个槽之间的N区域1004在反向偏置的情况下耗尽。N区域10042的耗尽在阳极终端和阴极终端之间提供了有效的半导体-绝缘体-半导体结构，因此限制了由在这两个终端外部间施加的反向电压采用其它方式终止进入耗尽N区域1004内的电场线。
[62]在一个实施方式中，n型区域1004是在重度掺杂的n+衬底202上生长的外延层。在一个实施方式中，对n型外延层1004均匀掺杂。在另一实施方式中，对n型外延层1004非均匀掺杂。例如，可使掺杂分布缓变以在衬底上具有比表面高的掺杂，反之亦然。
[63]在图10所示的实施方式中，第一介电材料1008，例如，热生长氧化物层，沿着槽壁和槽底部形成。在一个实施方式中，第一介电材料的厚度范围从大约2nm到大约200nm。例如，第一介电材料的厚度可大约为30nm。如图所示，槽1006包括第二材料1010，其可以包括一种或多种材料/复合层，其在槽的内部区域且完全被包围在第一介电材料1008内。第二材料1010，其可以是铝氟化物，在AlFX层和第一介电材料1008间的界面上提供负电荷。
[64]图11是根据本发明的另一实施方式的半导体器件1100的横截面视图。器件1100与器件1000类似，除了在器件1100中，所示的每个槽1006包括第一介电层1020，第二层1022，以及第三层1024。在一个实施方式中，每个第三层1024包括很多可能包括或者可能不包括介电材料的材料。器件1100的其它方面与器件1000相似。
[65]在器件1100中，每个槽1006包括第一层1020(其为介电层)，第二层1022，以及第三层1024(其为介电层)。第一层1020形成在槽壁和槽底部上。形成可能包括不止一种材料的第二层1022，以便其被包围在第一层1020内。形成第三层1024以便其被包围在第二层1022内。在一个实施方式中，由与第一层1020相同的材料形成第三层1024。在另一个实施方式中，使用不同的材料形成第一和第二介电层。在这两个介电层1020和1024之间的沉积层1022可以包含，例如，铝氟化物，其在介电层1020，1024和1022间的界面上提供负电荷。利用传统制造工艺例如注入、扩散、退火，以及其它类似的制造工艺形成器件1100的各种n+型，p+型，n和p型层。
[66]图12A根据本发明的另一个实施方式的横向高电压式半导体器件1200的简化俯视图。如图所示，器件1200包括耦联至n+区域202的阴极终端，耦联至p+区域208的阳极终端，设置在p+区域208和n+区域202之间的p型区域204，以及很多形成在p区域204中的槽2061，2062，……206N，它们共同地且可选地在下文中以槽206表示。尽管在图12A中只显示了三个槽2061、2062和2063，据此应该理解根据本发明的高击穿电压器件可以包括许多槽206。
[67]在一个实施方式中，每个槽206包括一个或多个介电层210。根据本发明，正电荷被有意导入到槽206中。这种电荷可以居于槽中，或者在槽和p型区域204间的过渡区域中，或者p区域204中，或者它们之间的组合中，并且这种电荷共同地并可选地在此被称为界面电荷。这种横跨槽的相对表面存在的正界面电荷足够导致被设置在这两个槽之间的p区域204在反向偏置情况下部分地或者全部地耗尽。例如，在槽2061、2062的相对表面2121和2122附近存在的电荷足够导致被设置在这两个槽之间的p型区域2042在反向偏置的情况下部分地或者全部地耗尽。类似地，在槽2062，2063的相对表面2123和2124附近存在的电荷足够导致被设置在这两个槽之间的区域204在反向偏置的情况下部分地或者全部的耗尽。在反向偏置的情况下p型区域204部分地或者全部地耗尽导致电场沿着，例如，垂至于位于相对表面2121和2122中点的线AA′的平面，在阴极和阳极终端之间外部施加反向电压的情况下保持相对均匀。在反向偏置情况下，正界面电荷被P型区域204的耗尽电荷平衡。如上所述，在一个实施方式中，正电荷在典型的器件运转温度下是固定的。
[68]图12B是沿着线AA′的结构1200的简化横截面视图。参考图12B，p型区域204在反向偏置的情况下被全部地或者部分地耗尽。介电层220覆盖整个结构并用于钝化半导体器件。图12C是沿着线BB’的结构1200的横截面视图，其示出了槽2063以及器件1200的各种其它区域。
[69]图13A是根据本发明的另一实施方式的横向高电压式半导体器件1300的简化俯视图。如图所示，器件1300包括耦联至n+区域202的阴极终端，耦联至n+区域208的阳极终端，设置在n+区域208，202之间的n型区域1302，以及形成在n型区域1302中的许多槽2061，2062…206N，它们共同地且可选地在下文中被表示为槽206。尽管在图13A中仅显示了两个槽2061，2062，但是据此理解根据本发明的高击穿电压式器件可以包括许多槽206。图13B是沿着线AA′的结构1300的横截面视图。参考图13B，n型区域1302在反向偏置的情况下全部地或者部分地被耗尽。介电层220覆盖整个结构并用于钝化半导体器件。
[70]图13C和13D是沿着线BB’和CC’的半导体器件1300的横截面视图。器件1300与器件1200类似，除了在器件1300中，每个槽1006被显示为包括第一介电层1020，第二层1022，和第三层1024(图13D)。此外，不同于器件1200，在器件1300中形成槽从而包括负电荷以耗尽N区域1302。在一个实施方式中，每个第三层1024包括许多可能含有或者可能不含有介电材料的材料。
[71]在器件1300中并如上所述，每个槽1006包括为介电层的第一层1020，第二层1022，以及为介电层的第三层1024。第一层1020形成在槽壁和槽底部上。形成可能含有不止一种材料的第二层1022，以便其被包围在第一层1020中。形成第三层1024从而使其被包围在第二层1022内。在一个实施方式中，由与第一层1020相同的材料形成第三层1024。在另一实施方式中，利用不同材料形成第一和第二介电层。在这两个介电层1020和1024之间的沉积层1022可能包括，例如，铝氟化物，并在介电层1020，1024和层1022之间的界面上提供负电荷。利用传统制造工艺例如注入，扩散，退火，以及类似的工艺形成器件1300的各种层。
[72]图14是根据本发明的另一实施方式的横向高电压式半导体器件1400的简化俯视图。器件1400类似于器件1200，除了在器件1400中，槽被锥形化以便使在阳极终端附近的宽度比阴极终端附近的宽，以补偿在p型衬底中产生的耗尽电荷。
[73]图15A和15B分别显示的是常规结构1510，和根据本发明的一个示例性实施方式的结构1520的在击穿电压下的等势线。在该仿真中，每个等高线代表10伏特。结构1510包括被设置在二极管相关阳极和阴极终端之间的半导体区域1502。结构1520被显示包括槽206。根据本发明，电荷密度(Qf/q)为1×1012cm-2的(q是电子电荷)的正界面电荷存在于槽206和P区域204的界面上。在该仿真中，槽206的宽度1μm并且阳极距阴极10μm。半导体区域1502和204的掺杂水平是2×1016cm3。根据该仿真，常规结构1510的击穿电压大约为34伏，而本发明的结构1520的击穿电压为220伏。
[74]图15C显示了沿着图15A-B所示结构的横截线AA’的电场图。使用曲线1530显示结构1510的电场分布。通过使用显示结构1535显示对于结构1520有显著改进的电场分布。在反向偏置的情况下p型区域204部分的或者全部的耗尽导致沿着设置在相对面212和212中点处的横截线AA’的电场在阴极终端和阳极终端之间外部施加反向偏置的情况下保持相对均匀。对于结构1510，在反向偏置的情况下，在区域1502内的离子化掺杂物的电场终止于正极，因此导致电场具有三角形轮廓。
[75]图15D显示了对于结构1510(曲线1540)以及1520(曲线1545)的反偏电流对电压的特性图。如图所示，结构1510的击穿电压是34伏，并且结构1520的击穿电压是220伏。
[76]本发明的上述实施方式只具有说明性并非是限制性的。不同可选方案以及等同方案都是可行的。本发明不限于具有本发明揭露技术的器件或者集成电路的类型。也不限于任一特定类型的处理技术，例如可以用于生产已有技术的CMOS，双极晶体管或者BICMOS。另外附加的，对于本发明所揭示的内容来说明显的删减或改变也都落入所附的权利要求的保护范围中。

Claims (71)

1.一种半导体结构，其包括：
耦联至所述结构的第一终端的第一区域；
耦联至所述结构的第二终端的第二区域；
设置在所述第一和第二区域之间具有单一导电类型的第三区域；以及
沿着所述第三区域的深度延伸第一距离的至少第一和第二介电区域，其中在所述第三区域中存在的掺杂杂质的浓度以及所述至少第一和第二介电区域之间的距离限定了所述半导体结构的电特性，其中所述电特性与所述介电区域的宽度无关，并且其中所述第一和第二区域具有相反的导电类型。
2.根据权利要求1所述半导体结构，其中所述至少第一和第二介电区域延伸入所述第一和第二区域内。
3.根据权利要求1所述半导体结构，其中在所述第三区域中沿着平行于所述至少第一和第二介电区域表面的线的掺杂杂质的积分密度的范围从大约1×1012/cm2到大约5×1012/cm2。
4.根据权利要求1所述的半导体结构，其中所述至少第一和第二介电区域的每一个进一步包括第一和第二材料。
5.根据权利要求1所述的半导体结构，其中每个所述至少第一和第二介电区域进一步包括注入的正电荷。
6.根据权利要求1所述的半导体结构，其中每个所述至少第一和第二介电区域进一步包括注入的负电荷。
7.根据权利要求4所述的半导体结构，其中在每个所述至少第一和第二介电区域中的所述第二材料包括铝氟化物。
8.根据权利要求4所述的半导体结构，其中每个所述至少第一和第二介电区域进一步包括第三材料，所述第三材料是介电材料。
9.根据权利要求8所述的半导体结构，其中在每个介电区域中的所述第一和第三材料是同一种材料。
10.根据权利要求1所述的半导体结构，其中所述第一和第二区域分别是p+型和n+型区域，所述第一和第二终端分别是阳极和阴极终端，并且所述第三区域是p型区域。
11.根据权利要求10所述的半导体结构，其中所述第三区域形成在所述第二区域之上，并且所述第一区域形成在所述第三区域之上。
12.根据权利要求1所述的半导体结构，其中所述第一和第二区域分别是p+型和n+型区域，所述第一和第二终端分别是阳极和阴极终端，并且所述第三区域是n型区域
13.根据权利要求12所述的半导体结构，其中所述第三区域形成在所述第二区域之上，并且所述第一区域形成在所述第三区域之上。
14.根据权利要求1所述的半导体结构，其中所述至少第一和第二介电区域彼此隔离。
15.根据权利要求1所述的半导体结构，其中所述半导体结构进一步包括设置在所述第二和所述第三区域之间的第四区域，所述第二和第四区域具有相同的导电类型。
16.根据权利要求1所述的半导体结构，其中所述第一和第二区域分别是n+型和p+型区域，所述第一和第二终端分别是阴极和阳极终端，并且所述第三区域是p型区域。
17.根据权利要求14所述的半导体结构，其中所述第三区域形成在所述第二区域之上，并且所述第一区域形成在所述第三区域之上。
18.根据权利要求1所述的半导体结构，其中所述第一和第二区域分别是n+型和p+型区域，所述第一和第二终端分别是阴极和阳极终端，并且所述第三区域是n型区域。
19.根据权利要求16所述的半导体结构，其中所述第三区域形成在所述第二区域之上，并且所述第一区域形成在所述第三区域之上。
20.根据权利要求1所述的半导体结构，其中每个所述至少第一和第二介电区域被锥形化以使靠近所述介电区域的一端相比该介电区域另一端具有较大的宽度。
21.根据权利要求1所述的半导体结构，其中沿着形成所述半导体结构的半导体衬底的同一表面上形成所述第一、第二和第三区。
22.根据权利要求21所述的半导体结构，进一步包括：
在其中形成所述第二区域的第四区域，所述第三区域相邻所述第一和第四区域。
23.根据权利要求22所述的半导体结构，其中所述第一区域是p+型区域，所述第二区域是n+型区域，所述第三区域是p型区域，并且所述第四区域是n型区域。
24.根据权利要求22所述的半导体结构，其中所述第一区域是p+型区域，所述第二区域是n+型区域，所述第三区域是n型区域，并且所述第四区域是p型区域。
25.一种半导体结构，其包括：
耦联至所述结构的第一终端的第一区域；
耦联至所述结构的第二终端的第二区域；
设置在所述第一和第二区域之间的第三区域；以及
沿着所述第三区域的深度延伸第一距离的至少第一和第二介电区域，其中所述第一和第二区域具有相反的导电类型，并且其中所述至少第一和第二介电区域或者在每个所述至少第一和第二介电区域和所述第三区域之间的界面区包含有意导入电荷。
26.根据权利要求25所述的半导体结构，其中所述至少第一和第二介电区域延伸入所述第一和第二区域内。
27.根据权利要求25所述的半导体结构，其中在所述第三区域内沿着平行于所述至少第一和第二介电区域表面的线的掺杂杂质的积分密度的范围从大约1×1012/cm2到大约5×1012/cm2。
28.根据权利要求25所述的半导体结构，其中每个所述至少第一和第二介电区域进一步包括第一和第二材料。
29.根据权利要求25所述的半导体结构，其中所述有意导入电荷是注入的正电荷。
30.根据权利要求25所述的半导体结构，其中所述有意导入电荷是注入的负电荷。
31.根据权利要求28所述的半导体结构，其中在每个所述至少第一和第二介电区域内的所述第二材料包括铝氟化物。
32.根据权利要求28所述的半导体结构，其中每个所述至少第一和第二介电区域进一步包括第三材料，所述第三材料是介电材料。
33.根据权利要求32所述的半导体结构，其中在每个介电区域内的所述第一和第三材料是同一材料。
34.根据权利要求25所述的半导体结构，其中所述第一和第二区域分别是p+型和n+型区域，所述第一和第二终端分别是阳极和阴极终端，并且所述第三区域是p型区域。
35.根据权利要求34所述的半导体结构，其中所述第三区域形成在所述第二区域之上，并且所述第一区域形成在所述第三区域之上。
36.根据权利要求25所述的半导体结构，其中所述第一和第二区域分别是p+型和n+型区域，所述第一和第二终端分别是阳极和阴极终端，并且所述第三区域是n型区域。
37.根据权利要求36所述的半导体结构，其中所述第三区域形成在所述第二区域之上，并且所述第一区域形成在所述第三区域之上。
38.根据权利要求25所述的半导体结构，其中所述至少第一和第二介电区域彼此隔离。
39.根据权利要求25所述的半导体结构，其中所述半导体结构进一步包括设置在所述第二和所述第三区域之间的第四区域，所述第二和第四区域具有相同的导电类型。
40.根据权利要求25所述的半导体结构，其中所述第一和第二区域分别是n+型和p+型区域，所述第一和第二终端分别是阴极和阳极终端，并且所述第三区域是p型区域。
41.根据权利要求34所述的半导体结构，其中所述第三区域形成在所述第二区域之上，并且所述第一区域形成在所述第三区域之上。
42.根据权利要求25所述的半导体结构，其中所述第一和第二区域分别是n+型和p+型区域，所述第一和第二终端分别是阴极和阳极终端，并且所述第三区域是n型区域。
43.根据权利要求34所述的半导体结构，其中所述第三区域形成在所述第二区域之上，并且所述第一区域形成在所述第三区域之上。
44.根据权利要求34所述的半导体结构，其中每个所述至少第一和第二介电区域被锥形化以便使得靠近所述介电区域一端与该介电区域的另外一端相比具有更大的宽度。
45.根据权利要求34所述的半导体结构，其中沿着形成所述半导体结构的半导体衬底的同一表面上形成所述第一、第二和第三区域。
46.根据权利要求45所述的半导体结构，进一步包括：
在其中形成所述第二区域的第四区域，所述第三区域相邻所述第一和第四区域。
47.根据权利要求46所述的半导体结构，其中所述第一区域是p+型区域，所述第二区域是n+型区域，所述第三区域是p型区域，并且所述第四区域是n型区域。
48.根据权利要求46所述的半导体结构，其中所述第一区域是p+型区域，所述第二区域是n+型区域，所述第三区域是n型区域并且所述第四区域是p型区域。
49.一种半导体结构，其包括：
耦联至所述结构的第一终端的第一区域；
耦联至所述结构的第二终端的第二区域；
设置在所述第一和第二区域之间的第三区域；
沿着所述第三区域的深度延伸第一距离，并且具有与所述第三区域的导电类型相反的导电类型的第四区域，所述第四区域靠近所述第一和第二区域；以及
沿着所述第三区域的深度延伸第二距离的至少第一和第二介电区域，其中所述第一和第二区域具有相反的导电类型，其中所述第四区域包围所述至少第一和第二介电区域的一部分，并且其中所述至少第一和第二介电区域或者在每个所述至少第一和第二介电区域和所述第四区域之间的界面区包含有意导入电荷。
50.根据权利要求49所述的半导体结构，其中所述至少第一和第二介电区域延伸进所述第一和第二区域内。
51.根据权利要求49所述的半导体结构，其中每个所述至少第一和第二介电区域进一步包括第一和第二材料。
52.根据权利要求49所述的半导体结构，其中所述有意导入电荷是注入的正电荷。
53.根据权利要求49所述的半导体结构，其中所述有意导入电荷是注入的负电荷。
54.根据权利要求51所述的半导体结构，其中在每个所述至少第一和第二介电区域中的所述第二材料包括铝氟化物。
55.根据权利要求51所述的半导体结构，其中每个所述至少第一和第二介电区域进一步包括第三材料，所述第三材料是介电材料。
56.根据权利要求55所述的半导体结构，其中在每个介电区域内的所述第一和第三材料是同一种材料。
57.根据权利要求49所述的半导体结构，其中所述第一和第二区域分别是p+型和n+型区域，所述第一和第二终端分别是阳极和阴极终端，并且所述第三区域是p型区域。
58.根据权利要求57所述的半导体结构，其中所述第三区域形成在所述第二区域之上，并且所述第一区域形成在所述第三区域之上。
59.根据权利要求49所述的半导体结构，其中所述第一和第二区域分别是p+型和n+型区域，所述第一和第二终端分别是阳极和阴极终端，并且所述第三区域是n型区域。
60.根据权利要求59所述的半导体结构，其中所述第三区域形成在所述第二区域之上，并且所述第一区域形成在所述第三区域之上。
61.根据权利要求49所述的半导体结构，其中所述至少第一和第二介电区域彼此隔离。
62.根据权利要求49所述的半导体结构，其中所述半导体结构进一步包括设置在所述第二、所述第三、和所述第四区域之间的第五区域，所述第二和第五区域具有相同的导电类型。
63.根据权利要求49所述的半导体结构，其中所述第一和第二区域分别是n+型和p+型区域，所述第一和第二终端分别是阴极和阳极终端，并且所述第三区域是p型区域。
64.根据权利要求63所述的半导体结构，其中所述第三区域形成在所述第二区域之上，并且所述第一区域形成在所述第三区域之上。
65.根据权利要求49所述的半导体结构，其中所述第一和第二区域分别是n+型和p+型区域，所述第一和第二终端分别是阴极和阳极终端，并且所述第三区域是n型区域。
66.根据权利要求65所述的半导体结构，其中所述第三区域形成在所述第二区域之上，并且所述第一区域形成在所述第三区域之上。
67.根据权利要求49所述的半导体结构，其中每个所述至少第一和第二介电区域被锥形化以便使得靠近所述介电区域一端与该介电区域的另外一端相比具有更大的宽度。
68.根据权利要求49所述的半导体结构，其中沿着形成所述半导体结构的半导体衬底的同一表面上形成所述第一，第二和第三区域。
69.根据权利要求68所述的半导体结构，进一步包括：
在其中形成所述第二区域的第五区域，所述第三区域靠近所述第一和第五区域。
70.根据权利要求69所述的半导体结构，其中所述第一区域是p+型区域，所述第二区域是n+型区域，所述第三区域是p型区域，并且所述第四区域是n型区域。
71.根据权利要求69所述的半导体结构，其中所述第一区域是p+型区域，所述第二区域是n+型区域，所述第三区域是n型区域，并且所述第四区域是p型区域。
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US20140203354A1 (en) 2014-07-24
US8618599B2 (en) 2013-12-31
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US8344451B2 (en) 2013-01-01
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JP5479915B2 (ja) 2014-04-23
US20080164520A1 (en) 2008-07-10
US8420483B2 (en) 2013-04-16
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US8962426B2 (en) 2015-02-24
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US7964913B2 (en) 2011-06-21
KR20090116702A (ko) 2009-11-11
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US20120161226A1 (en) 2012-06-28
US20140070308A1 (en) 2014-03-13
CN101641763A (zh) 2010-02-03
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US20080164516A1 (en) 2008-07-10
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US8058682B2 (en) 2011-11-15
US20130168762A1 (en) 2013-07-04
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