US20090039410A1 - Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing - Google Patents

Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing Download PDF

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Publication number
US20090039410A1
US20090039410A1 US11/834,574 US83457407A US2009039410A1 US 20090039410 A1 US20090039410 A1 US 20090039410A1 US 83457407 A US83457407 A US 83457407A US 2009039410 A1 US2009039410 A1 US 2009039410A1
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United States
Prior art keywords
gate
erase
floating gate
region
insulated
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US11/834,574
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English (en)
Inventor
Xian Liu
Amitay Levi
Alexander Kotov
Yuri Tkachev
Viktor Markov
James Yingbo Jia
Chien-Sheng Su
Yaw Wen Hu
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Silicon Storage Technology Inc
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Silicon Storage Technology Inc
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Priority to US11/834,574 priority Critical patent/US20090039410A1/en
Assigned to SILICON STORAGE TECHNOLOGY, INC. reassignment SILICON STORAGE TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HU, YAW WEN, JIA, JAMES YINGBO, KOTOV, ALEXANDER, LEVI, AMITAY, LIU, XIAN, MARKOV, VICTOR, SU, CHIEN SHENG, TKACHEV, YURI
Priority to TW097127416A priority patent/TWI393263B/zh
Priority to KR1020080075628A priority patent/KR20090014967A/ko
Priority to CN2011102379841A priority patent/CN102403274A/zh
Priority to CN2008101352676A priority patent/CN101364614B/zh
Priority to CN2011104494755A priority patent/CN102522409A/zh
Priority to JP2008225276A priority patent/JP5361292B2/ja
Publication of US20090039410A1 publication Critical patent/US20090039410A1/en
Priority to US12/618,632 priority patent/US7868375B2/en
Priority to US12/961,193 priority patent/US7927994B1/en
Priority to US13/023,443 priority patent/US20110127599A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Definitions

  • the present invention relates to a non-volatile flash memory cell which has a select gate, a floating gate, a control gate, and an erase gate having an overhang with the floating gate in a certain dimensional ratio.
  • the present invention also relates to an array of such flash memory cells, and methods of manufacturing such cell and array.
  • a split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate.
  • the cell has a select gate insulated and spaced apart from a first portion of the channel region.
  • the cell further has a floating gate insulated and spaced apart from a second portion of the channel region.
  • the floating gate has a first end closest to the select gate and a second end furthest away from the select gate.
  • An erase gate is insulated and spaced apart from the substrate and is closest to the second end of the floating gate.
  • a control gate is insulated and spaced apart from the floating gate, the select gate and the erase gate and is positioned above the floating gate and is between the erase gate and the select gate.
  • the erase gate further has two electrically connected portions: a first portion laterally adjacent to and insulated from the second end of the floating gate and a second portion overlying and insulated from the floating gate and is adjacent to the control gate.
  • the second portion of the erase gate is separated from the floating gate by a first length measured in a direction substantially perpendicular to the direction from the first region to the second region.
  • the second portion of the erase gate has an end closest to the control gate, and the first portion of the erase gate has an end closest to the floating gate.
  • the second portion of the erase gate overlies the floating gate by a second length measured from the end of the second portion of the erase gate closest to the control gate to the end of the first portion of the erase gate closest to the floating gate in a direction substantially perpendicular to the first length direction.
  • the ratio of the second length to the first length is between approximately 1.0 and 2.5.
  • the present invention also relates to an array of the foregoing memory cells.
  • FIG. 1A is a cross sectional view of an improved non-volatile memory cell of the present invention.
  • FIG. 1B is an enlarged view of a portion of the cell shown in FIG. 1A , wherein the dimensional relationship between the overhang of the erase gate to the floating gate is shown in greater detail.
  • FIG. 2 is a graph showing the improvement to erase efficiency by the improved cell of the present invention.
  • FIGS. 3(A-L) are cross sectional views of one process to make one embodiment the memory cell of the present invention.
  • FIGS. 4(A-L) are cross sectional views of another process to make another embodiment of the memory cell of the present invention.
  • FIG. 1A there is shown a cross-sectional view of an improved non-volatile memory cell 10 of the present invention.
  • the memory cell 10 is made in a substantially single crystalline substrate 12 , such as single crystalline silicon, which is of P conductivity type.
  • a first region 14 of a second conductivity type Within the substrate 12 is a first region 14 of a second conductivity type. If the first conductivity type is P then the second conductivity type is N. Spaced apart from the first region is a second region 16 of the second conductivity type. Between the first region 14 and the second region 16 is a channel region 18 , which provides for the conduction of charges between the first region 14 and the second region 16 .
  • a select gate 20 Positioned above, and spaced apart and insulated from the substrate 12 is a select gate 20 , also known as the word line 20 .
  • the select gate 20 is positioned over a first portion of the channel region 18 .
  • the first portion of the channel region 18 immediately abuts the first region 14 .
  • the select gate 20 has little or no overlap with the first region 14 .
  • a floating gate 22 is also positioned above and is spaced apart and is insulated from the substrate 12 .
  • the floating gate 22 is positioned over a second portion of the channel region 18 and a portion of the second region 16 .
  • the second portion of the channel region 18 is different from the first portion of the channel region 18 .
  • the floating gate 22 is laterally spaced apart and is insulated from and is adjacent to the select gate 20 .
  • An erase gate 24 is positioned over and spaced apart from the second region 16 , and is insulated from the substrate 12 .
  • the erase gate 24 is laterally insulated and spaced apart from the floating gate 22 .
  • the select gate 20 is to one side of the floating gate 22 , with the erase gate 24 to another side of the floating gate 22 .
  • a control gate 26 positioned above the floating gate 22 and insulated and spaced apart therefrom is a control gate 26 .
  • the control gate 26 is insulated and spaced apart from the erase gate 24 and the select gate 20 and is positioned between the erase gate 24 and the select gate 20 .
  • the erase gate 24 has a portion that overhangs the floating gate 22 . This is shown in greater detail in FIG. 1B .
  • the erase gate 24 comprises of two parts that are electrically connected. In the preferred embodiment, the two parts form a monolithic structure, although it is within the present invention that the two parts can be separate parts and electrically connected.
  • a first part of the erase gate 24 is immediately laterally adjacent to the floating gate 22 and is above the second region 16 .
  • the first part of the erase gate 24 has an end 32 that is closest to the floating gate 22 .
  • the second part of the erase gate 24 is laterally adjacent to the control gate 26 and overhangs a portion of the floating gate 22 .
  • the second part of the erase gate has an end 34 that is closest to the control gate 26 .
  • the horizontal distance (as measured in the direction between the first region 14 and the second region 16 ) between the end 34 and the end 32 is called “EG Overhang” as shown in FIG. 1B .
  • the second part of the erase gate 24 which is laterally adjacent to the control gate 26 and overhangs the floating gate 22 is also vertically spaced apart from the floating gate 22 .
  • the vertical distance between the floating gate 22 and the second part of the erase gate 24 , as measured in the “vertical” direction is called “Tox” as shown in FIG. 1B .
  • the vertical distance of “Tox” is measured in a direction that is substantially perpendicular to the horizontal distance “EG Overhang”.
  • the memory cell 10 erases by electrons tunneling through the Fowler-Nordheim mechanism, from the floating gate 22 to the erase gate. Further, to improve the erase mechanism, the floating gate 22 may have a sharp corner closest to the erase gate 24 to enhance the local electrical field during erase and in turn enhance the flow of electrons from the corner of the floating gate 22 to the erase gate 24 . It has been found that erase efficiency is enhanced when the ratio of “EG Overhang” to “Tox” is between approximately 1.0 and 2.5. This is shown in FIG. 2 . Referring to FIG. 2 , there is shown a graph 30 of FTV, CR, and Verase as functions of the ratio of “EG overhang”/“Tox”.
  • C total is the total capacitance between the floating gate 22 and all surrounding nodes.
  • CR is the coupling ratio between the erase gate 24 and the floating gate 22 .
  • CR C EG-FG /C total , where C EG-FG is the capacitance between the erase gate 24 and the floating gate 22 .
  • Q FG is the net charge on the floating gate which corresponds to “1” state.
  • FTV is the voltage difference between the erase gate 24 and the floating gate 22 required to erase the cell to “1” state.
  • the electron tunneling barrier in the tunnel oxide adjacent to the corner of floating gate 22 is electrically exposed to the lower potential of the nearby coupling gate 26 , resulting in an increase of FTV, and in turn an increase of Verase.
  • CR is increased, which also in turn increases Verase.
  • the graph 30 shows a minimum of Verase when “EG Overhang”/“Tox” is at approximately 1.6. With Verase requirement reduced, the requirement on the charge pump is similarly reduced. Thus, erase efficiency is enhanced.
  • the select gate 20 of the memory cell 10 is separated from the floating gate by an insulating region W 1 .
  • the region W 1 is silicon dioxide. This is called the cell 10 option A.
  • the region W 1 is a composite layer comprising silicon dioxide, silicon nitride, and silicon dioxide, and this embodiment is called the cell 10 option B.
  • FIGS. 3(A-L) there is shown cross-sectional views of the steps in the process to make a cell 10 option A of the present invention.
  • a layer of silicon dioxide 40 on the substrate 12 of P type single crystalline silicon.
  • the layer 40 of silicon dioxide is on the order of 80-100 angstroms.
  • a first layer 42 of polysilicon (or amorphous silicon) is deposited or formed on the layer 40 of silicon dioxide.
  • the first layer 42 of polysilicon is on the order of 300-800 angstroms.
  • the first layer 42 of polysilicon is subsequently patterned in a direction perpendicular to the select gate 20 .
  • FIG. 3B there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention.
  • Another insulating layer 44 such as silicon dioxide (or even a composite layer, such as ONO) is deposited or formed on the first layer 42 of polysilicon. Depending on whether the material is silicon dioxide or ONO, the layer 44 can be on the order of 100-200 angstroms.
  • a second layer 46 of polysilicon is then deposited or formed on the layer 44 .
  • the second layer 46 of polysilicon is on the order of 500-4000 angstroms thick.
  • Another layer 48 of insulator is deposited or formed on the second layer 46 of polysilicon and used as a hard mask during subsequent dry etching.
  • the layer 48 is a composite layer, comprising silicon nitride 48 a , silicon dioxide 48 b , and silicon nitride 48 c .
  • the dimensions are 200-600 angstroms for layer 48 a , 200-600 angstroms for layer 48 b , and 500-3000 angstroms for layer 48 c.
  • FIG. 3C there is shown a cross sectional view of the next step in the process of making the cell 10 option A of the present invention.
  • Photoresist material (not shown) is deposited on the structure shown in FIG. 3B , and a masking step is formed exposing selected portions of the photoresist material.
  • the photoresist is developed and using the photoresist as a mask, the structure is etched.
  • the composite layer 48 , the second layer 46 of polysilicon, the insulating layer 44 are then anisotropically etched, until the first layer 42 of polysilicon is exposed.
  • the resultant structure is shown in FIG. 3C .
  • S 1 and S 2 are shown, it should be clear that there are number of such “stacks” that are separated from one another.
  • FIG. 3D there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention.
  • Silicon dioxide 49 is deposited or formed on the structure. This is followed by the deposition of silicon nitride layer 50 .
  • the silicon dioxide 49 and silicon nitride 50 are anisotropically etched leaving a spacer 51 (which is the combination of the silicon dioxide 49 and silicon nitride 50 ) around each of the stacks S 1 and S 2 .
  • the resultant structure is shown in FIG. 3D .
  • FIG. 3E there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention.
  • a photoresist mask is formed over the regions between the stacks S 1 and S 2 , and other alternating pairs stacks.
  • this region between the stacks S 1 and S 2 will be called the “inner region” and the regions not covered by the photoresist, shall be referred to as the “outer regions”.
  • the exposed first polysilicon 42 in the outer regions is anisotropically etched.
  • the oxide layer 40 is similarly anisotropically etched.
  • the resultant structure is shown in FIG. 3E .
  • FIG. 3F there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention.
  • the photoresist material is removed from the structure shown in FIG. 3E .
  • a layer of oxide 52 is then deposited or formed.
  • the oxide layer 52 is then subject to an anisotropical etch leaving spacers 52 , adjacent to the stacks S 1 and S 2 .
  • the resultant structure is shown in FIG. 3F .
  • FIG. 3G there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention.
  • Photoresist material is then deposited and is masked leaving openings in the inner regions between the stacks S 1 and S 2 .
  • the photoresist is between other alternating pairs of stacks.
  • the polysilicon 42 in the inner regions between the stacks S 1 and S 2 (and other alternating pairs of stacks) is anisotropically etched.
  • the silicon dioxide layer 40 beneath the polysilicon 42 may also be anisotropically etched.
  • the resultant structure is subject to a high voltage ion implant forming the second regions 16 .
  • the resultant structure is shown in FIG. 3G .
  • FIG. 3H there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention.
  • the oxide spacer 52 adjacent to the stacks S 1 and S 2 in the inner region is removed by e.g. a wet etch or a dry isotropic etch.
  • the resultant structure is shown in FIG. 3H .
  • FIG. 3I there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention.
  • the photoresist material in the outer regions of the stacks S 1 and S 2 is removed.
  • Silicon dioxide 54 is deposited or formed everywhere.
  • the resultant structure is shown in FIG. 3I .
  • FIG. 3J there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention.
  • the structure is once again covered by photoresist material and a masking step is performed exposing the outer regions of the stacks S 1 and S 2 and leaving photoresist material covering the inner region between the stacks S 1 and S 2 .
  • An oxide anisotropical etch is performed, to reduce the thickness of the spacer 54 in the outer regions of the stack S 1 and S 2 , and to completely remove silicon dioxide from the exposed silicon substrate 12 in the outer regions.
  • the resultant structure is shown in FIG. 3J .
  • FIG. 3K there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention.
  • This oxide layer 56 is the gate oxide between the select gate and the substrate 12 .
  • the resultant structure is shown in FIG. 3K .
  • FIG. 3L there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention.
  • Polysilicon 60 is deposited everywhere.
  • the layer 60 of polysilicon is then subject to an anisotropical etch forming spacers in the outer regions of the stack S 1 and S 2 which form the select gates 20 of two memory cells 10 adjacent to one another sharing a common second region 16 .
  • the spacers within the inner regions of the stacks S 1 and S 2 are merged together forming a single erase gate 24 which is shared by the two adjacent memory cells 10 .
  • a layer of insulator 62 is deposited on the structure, and etched anisotropically to form spacers 62 next to the select gates 20 .
  • insulator 62 is a composite layer comprising silicon dioxide and silicon nitride. Thereafter, an ion implant step is performed forming the first regions 14 . Each of these memory cells on another side share a common first region 14 . Insulators and metallization layers are subsequently deposited and patterned to form bit line 70 and bit line contacts 72 .
  • FIGS. 4(A-L) there is shown cross-sectional views of the steps in the process to make a cell 10 option B of the present invention.
  • the steps and the description set forth hereinafter are similar to the steps and description above for the method of forming the memory cells 10 option A shown and described in FIGS. 3(A-L) .
  • the same numbers will be used for the same parts.
  • FIG. 4A there is shown the formation of a layer of silicon dioxide 40 on the substrate 12 of P type single crystalline silicon.
  • the layer 40 of silicon dioxide is on the order of 80-100 angstroms.
  • a first layer 42 of polysilicon is deposited or formed on the layer 40 of silicon dioxide.
  • the first layer 42 of polysilicon is on the order of 300-800 angstroms.
  • the first layer 42 of polysilicon is subsequently patterned in a direction perpendicular to the select gate 20 .
  • FIG. 4B there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention.
  • Another insulating layer 44 such as silicon dioxide (or even a composite layer, such as ONO) is deposited or formed on the first layer 42 of polysilicon. Depending on whether the material is silicon dioxide or ONO, the layer 44 can be on the order of 100-200 angstroms.
  • a second layer 46 of polysilicon is then deposited or formed on the layer 44 .
  • the second layer 46 of polysilicon is on the order of 500-4000 angstroms thick.
  • Another layer 48 of insulator is deposited or formed on the second layer 46 of polysilicon and used as a hard mask during subsequent dry etching.
  • the layer 48 is a composite layer, comprising silicon nitride 48 a , silicon dioxide 48 b , and silicon nitride 48 c .
  • the dimensions are 200-600 angstroms for layer 48 a , 200-600 angstroms for layer 48 b , and 500-3000 angstroms for layer 48 c.
  • FIG. 4C there is shown a cross sectional view of the next step in the process of making the cell 10 option B of the present invention.
  • Photoresist material (not shown) is deposited on the structure shown in FIG. 4B , and a masking step is formed exposing selected portions of the photoresist material.
  • the photoresist is developed and using the photoresist as a mask, the structure is etched.
  • the composite layer 48 , the second layer 46 of polysilicon, the insulating layer 44 are then anisotropically etched, until the first layer 42 of polysilicon is exposed.
  • the resultant structure is shown in FIG. 4C . Although only two “stacks”: S 1 and S 2 are shown, it should be clear that there are number of such “stacks” that are separated from one another.
  • FIG. 4D there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention.
  • a photoresist mask is formed over the regions between the stacks S 1 and S 2 , and other alternating pairs stacks.
  • this region between the stacks S 1 and S 2 will be called the “inner region” and the regions not covered by the photoresist, shall be referred to as the “outer regions”.
  • the exposed first polysilicon 42 in the outer regions is anisotropically etched.
  • the oxide layer 40 is similarly anisotropically etched.
  • the resultant structure is shown in FIG. 4D .
  • FIG. 4E there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention.
  • Silicon dioxide 49 is deposited or formed on the structure. This is followed by the deposition of silicon nitride layer 50 .
  • the silicon dioxide 49 and silicon nitride 50 are anisotropically etched leaving a spacer 51 (which is the combination of the silicon dioxide 49 and silicon nitride 50 ) around each of the stacks S 1 and S 2 (and all the other spaced apart stacks which are not shown).
  • the resultant structure is shown in FIG. 4E .
  • FIG. 4F there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention.
  • a layer of oxide 52 is then deposited or formed.
  • the oxide layer 52 is then subject to an anisotropical etch leaving spacers 52 , adjacent to the stacks S 1 and S 2 .
  • the resultant structure is shown in FIG. 4F .
  • FIG. 4G there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention.
  • Photoresist material is then deposited and is masked leaving openings in the inner regions between the stacks S 1 and S 2 . Again, the photoresist is between other alternating pairs of stacks.
  • the polysilicon 42 in the inner regions between the stacks S 1 and S 2 (and other alternating pairs of stacks) is anisotropically etched.
  • the silicon dioxide layer 40 beneath the polysilicon 42 may also be anisotropically etched.
  • the resultant structure is subject to a high voltage ion implant forming the second regions 16 .
  • the resultant structure is shown in FIG. 4G .
  • FIG. 4H there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention.
  • the oxide spacer 52 adjacent to the stacks S 1 and S 2 in the inner region is removed by e.g. a wet etch or a dry isotropic etch.
  • the resultant structure is shown in FIG. 4H .
  • FIG. 4I there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention.
  • the photoresist material in the outer regions of the stacks S 1 and S 2 is removed.
  • Silicon dioxide 54 is deposited or formed everywhere.
  • the resultant structure is shown in FIG. 4I .
  • FIG. 4J there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention.
  • the structure is once again covered by photoresist material and a masking step is performed exposing the outer regions of the stacks S 1 and S 2 and leaving photoresist material covering the inner region between the stacks S 1 and S 2 .
  • An oxide anisotropical etch is performed, to reduce the thickness of the oxide spacer 54 in the outer regions of the stack S 1 and S 2 , and to completely remove silicon dioxide from the exposed silicon substrate 12 in the outer regions.
  • the resultant structure is shown in FIG. 4J .
  • FIG. 4K there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention.
  • This oxide layer 56 is the gate oxide between the select gate and the substrate 12 .
  • the resultant structure is shown in FIG. 4J .
  • FIG. 4L there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention.
  • Polysilicon 60 is deposited everywhere.
  • the layer 60 of polysilicon is then subject to an anisotropical etch forming spacers in the outer regions of the stack S 1 and S 2 which form the select gates 20 of two memory cells 10 adjacent to one another sharing a common second region 16 .
  • the spacers within the inner regions of the stacks S 1 and S 2 are merged together forming a single erase gate 24 which is shared by the two adjacent memory cells 10 .
  • a layer of insulator 62 is deposited on the structure, and etched anisotropically to form spacers 62 next to the select gates 20 .
  • insulator 62 is a composite layer comprising silicon dioxide and silicon nitride. Thereafter, an ion implant step is performed forming the first regions 14 . Each of these memory cells on another side share a common first region 14 . Insulators and metallization layers are subsequently deposited and patterned to form bit line 70 and bit line contacts 72 .
  • the operating conditions may also be different.
  • the following voltages may be applied.
  • a negative voltage on the order of ⁇ 6 to ⁇ 9 volts may be applied to the select control gate 26 .
  • the voltage applied to the select erase gate 24 may be lowered to approximately 7-9 volts.
  • the “overhang” of the erase gate 24 shields the tunneling barrier from the negative voltage applied to the select control gate 26 .
  • the following voltages may be applied.
  • the selected cell is programmed through efficient hot-electron injection with the portion of the channel under the floating gate in inversion.
  • the medium voltage of 3-6 volts is applied to the select SL to generate the hot electrons.
  • the select control gate 26 and erase gate 24 are biased to a high voltage (6-9 volts) to utilize the high coupling ratio and to maximize the voltage coupling to the floating gate.
  • the high voltage coupled to the floating gate induces FG channel inversion and concentrates lateral field in the split area to generate hot electrons more effectively.
  • the voltages provide a high vertical field to attract hot electron into the floating gate and reduce injection energy barrier.
  • the voltages on the select control gate 26 and the select erase gate 24 can be balanced because each is coupled to the floating gate.
  • the voltages applied to each of the select control gate 26 and select erase gate 24 can be a combination of voltages ranging from 0 to 3.7V to achieve optimum window.
  • voltages on the select erase gate 24 can result in a faster read operation.

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US11/834,574 2007-08-06 2007-08-06 Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing Abandoned US20090039410A1 (en)

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US11/834,574 US20090039410A1 (en) 2007-08-06 2007-08-06 Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing
TW097127416A TWI393263B (zh) 2007-08-06 2008-07-18 具有浮動閘、控制閘、選擇閘及具有在該浮動閘上方之突出部的抹除閘之改良分裂閘極非依電性快閃記憶體晶胞、陣列及製造方法
KR1020080075628A KR20090014967A (ko) 2007-08-06 2008-08-01 부동 게이트, 제어 게이트, 선택 게이트 및 부동 게이트위로 돌출부를 갖는 소거 게이트를 구비한 개선된 분할게이트 비휘발성 플래시 메모리 셀, 배열 및 제조 방법
CN2011104494755A CN102522409A (zh) 2007-08-06 2008-08-05 非易失性闪速存储单元、阵列及其制造方法
CN2008101352676A CN101364614B (zh) 2007-08-06 2008-08-05 非易失性闪速存储单元、阵列及其制造方法
CN2011102379841A CN102403274A (zh) 2007-08-06 2008-08-05 非易失性闪速存储单元、阵列及其制造方法
JP2008225276A JP5361292B2 (ja) 2007-08-06 2008-08-06 浮遊ゲート、制御ゲート、選択ゲート、及び浮遊ゲートの上にオーバーハングをもつ消去ゲートを有する、改善されたスプリット・ゲート型不揮発性フラッシュメモリ・セル、アレイ、及び製造方法
US12/618,632 US7868375B2 (en) 2007-08-06 2009-11-13 Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing
US12/961,193 US7927994B1 (en) 2007-08-06 2010-12-06 Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing
US13/023,443 US20110127599A1 (en) 2007-08-06 2011-02-08 Split Gate Non-volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing

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US12/618,632 Active US7868375B2 (en) 2007-08-06 2009-11-13 Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing
US12/961,193 Active US7927994B1 (en) 2007-08-06 2010-12-06 Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing
US13/023,443 Abandoned US20110127599A1 (en) 2007-08-06 2011-02-08 Split Gate Non-volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing

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US12/961,193 Active US7927994B1 (en) 2007-08-06 2010-12-06 Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing
US13/023,443 Abandoned US20110127599A1 (en) 2007-08-06 2011-02-08 Split Gate Non-volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing

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US7868375B2 (en) 2011-01-11
US7927994B1 (en) 2011-04-19
CN102403274A (zh) 2012-04-04
KR20090014967A (ko) 2009-02-11
US20110076816A1 (en) 2011-03-31
US20100054043A1 (en) 2010-03-04
TW200917495A (en) 2009-04-16

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