JP5936959B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 190
- 238000004519 manufacturing process Methods 0.000 title claims description 67
- 230000015654 memory Effects 0.000 claims description 200
- 238000000034 method Methods 0.000 claims description 108
- 239000010410 layer Substances 0.000 claims description 101
- 239000000758 substrate Substances 0.000 claims description 91
- 229910021332 silicide Inorganic materials 0.000 claims description 69
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 69
- 239000004020 conductor Substances 0.000 claims description 56
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- LPQOADBMXVRBNX-UHFFFAOYSA-N ac1ldcw0 Chemical compound Cl.C1CN(C)CCN1C1=C(F)C=C2C(=O)C(C(O)=O)=CN3CCSC1=C32 LPQOADBMXVRBNX-UHFFFAOYSA-N 0.000 description 86
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 79
- 229910052814 silicon oxide Inorganic materials 0.000 description 79
- 229910052581 Si3N4 Inorganic materials 0.000 description 66
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 66
- 239000003990 capacitor Substances 0.000 description 37
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- 238000005229 chemical vapour deposition Methods 0.000 description 11
- 230000000149 penetrating effect Effects 0.000 description 9
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- 238000000206 photolithography Methods 0.000 description 8
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 239000010941 cobalt Substances 0.000 description 4
- 229910017052 cobalt Inorganic materials 0.000 description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
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- 238000001039 wet etching Methods 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- -1 Metal Oxide Nitride Chemical class 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
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Description
本実施の形態の半導体装置は、半導体基板上に形成するスプリットゲート型の不揮発性メモリセルであるMONOSメモリセルを微細化するとともに、半導体装置の信頼性を向上させるものである。
前記実施の形態1では、図19を用いて説明した工程において、シリサイド層S1を研磨して除去する工程を含む半導体装置の製造方法について説明した。これに対し、本実施の形態では、上記研磨工程において、シリサイド層を研磨しない場合の半導体装置の製造方法について、以下に図27〜図31を用いて説明する。図27〜図31は、本実施の形態の半導体装置の製造方法を説明するための、製造工程中の半導体装置を示す断面図である。
B1 給電部形成領域
C1 容量素子形成領域
C2 コンタクトプラグ
CG コントロールゲート電極
CGa コントロールゲート電極
D1 低耐圧素子形成領域
D2〜D4 溝
DP ダミーゲート電極
EI 素子分離領域
ES エッチングストッパ膜
EX エクステンション領域
G1 ゲート電極
GF ゲート絶縁膜
IF 絶縁膜
L1、L2 層間絶縁膜
MG、MGa メモリゲート電極
N1、N2 窒化シリコン膜
OS オフセットスペーサ
P1、P2 ポリシリコン膜
PR1〜PR4 フォトレジスト膜
S1、S2 シリサイド層
SB 半導体基板
SL 拡散層
SW サイドウォール
WS ウエル給電部
X1〜X4 酸化シリコン膜
Claims (9)
- (a1)半導体基板を用意する工程と、
(b1)前記半導体基板の上面の第1領域上に、第1絶縁膜を介して第1導体膜を形成する工程と、
(c1)前記第1導体膜を加工して、前記第1導体膜からなり、互いに離れて隣り合う第2導体膜および第3導体膜を形成する工程と、
(d1)前記半導体基板上に、第2絶縁膜、電荷蓄積膜および第4導体膜を順に形成することで、隣り合う前記第2導体膜および前記第3導体膜の間を埋め込む工程と、
(e1)エッチバックにより前記第3導体膜の直上の前記第4導体膜を含む前記第4導体膜の一部を除去し、前記第2導体膜の側壁のうち、前記第3導体膜と隣接していない方の側壁に、前記第4導体膜からなる第5導体膜を残す工程と、
(f1)前記第5導体膜を除去する工程と、
(g1)前記(f1)工程の後、前記第3導体膜を除去する工程と、
(h1)前記第2導体膜と、その側壁の前記第4導体膜とからなる構造体の横の、前記半導体基板の上面にソース・ドレイン領域を形成する工程と、
を有する、半導体装置の製造方法。 - (f2)前記(f1)工程の後、前記(g1)工程の前に、前記第4導体膜の側壁および底面に隣接している前記電荷蓄積膜を残して、その他の領域の前記電荷蓄積膜を除去する工程と、
(g2)前記(g1)工程の後、前記(h1)工程の前に、前記第4導体膜の側壁および底面に隣接している前記第2絶縁膜を残して、その他の領域の前記第2絶縁膜を除去する工程と、
をさらに有する、請求項1記載の半導体装置の製造方法。 - 前記(h1)工程では、前記半導体基板の上方から、前記半導体基板の上面に対して不純物を打ち込むことにより、前記ソース・ドレイン領域を形成する、請求項1記載の半導体装置の製造方法。
- 前記第2導体膜に隣接する前記第4導体膜の側壁であって、前記第2導体膜と隣接していない方の側壁は、前記半導体基板の主面に対して垂直に形成されている、請求項1記載の半導体装置の製造方法。
- (i1)前記ソース・ドレイン領域の上面に第1シリサイド層を形成する工程と、
(j1)前記(i1)工程の後、前記半導体基板上に第1層間絶縁膜を形成する工程と、
(k1)前記第1層間絶縁膜、前記第2導体膜および前記第4導体膜の上面を平坦化することで、前記第2導体膜からなるコントロールゲート電極と、前記コントロールゲート電極に隣接する前記第4導体膜からなるメモリゲート電極とを形成する工程と、
をさらに有する、請求項1記載の半導体装置の製造方法。 - (l1)前記(k1)工程の後、前記コントロールゲート電極の第1給電部および前記メモリゲート電極の第2給電部のそれぞれの上面に第2シリサイド層を形成する工程と、
(m1)前記コントロールゲート電極および前記メモリゲート電極を覆うように、前記半導体基板上に第2層間絶縁膜を形成する工程と、
(n1)前記第2層間絶縁膜を貫通し、前記コントロールゲート電極の前記第1給電部、前記メモリゲート電極の前記第2給電部および前記ソース・ドレイン領域と電気的に接続された接続部材をそれぞれ形成する工程と、
をさらに有する、請求項5記載の半導体装置の製造方法。 - (g3)前記(g1)工程の後、前記(h1)工程の前に、前記第2導体膜と隣接する前記第4導体膜の上面を一部除去することで、前記第4導体膜の上面を後退させ、前記第4導体膜の直上に溝を形成する工程と、
(h2)前記(i1)工程の前に、前記溝の側壁に、第3絶縁膜からなるサイドウォールを形成することで、前記サイドウォールにより、前記第4導体膜上の上面を覆う工程と、
をさらに有し、
前記(i1)工程では、前記第4導体膜の上面に前記第1シリサイド層を形成しない、請求項5記載の半導体装置の製造方法。 - 前記(b1)工程では、前記半導体基板の上面の第2領域上に、前記第1絶縁膜を介して前記第1導体膜を形成し、
前記(c1)工程では、前記第2領域の前記第1導体膜を加工して、前記第1導体膜からなり、前記半導体基板の上面に沿う第1方向に直交する第2方向に延在し、互いに離れて隣り合う複数の第6導体膜を前記第1方向に並べて形成し、
前記(d1)工程では、前記半導体基板上に、前記第2絶縁膜、前記電荷蓄積膜および前記第4導体膜を順に形成することで、隣り合う前記複数の第6導体膜同士の間を埋め込み、
前記(e1)工程では、前記エッチバックにより前記複数の第6導体膜のそれぞれの直上の前記第4導体膜を除去して、前記第4導体膜からなり、前記第2方向に延在する複数の第7導体膜を形成することで、
前記第1方向に交互に並び、前記第2絶縁膜および前記電荷蓄積膜を介して互いに絶縁された、前記複数の第6導体膜と、前記複数の第7導体膜とを含む容量素子を形成する、請求項1記載の半導体装置の製造方法。 - (j2)前記(e1)工程の後、前記第1領域および前記第2領域の前記半導体基板上に第1層間絶縁膜を形成する工程と、
(k2)前記第1領域および前記第2領域の前記第1層間絶縁膜、前記第2導体膜、前記第4導体膜、前記複数の第6導体膜および前記複数の第7導体膜のそれぞれの上面を平坦化することで、前記第2導体膜からなるコントロールゲート電極と、前記コントロールゲート電極に隣接する前記第4導体膜からなるメモリゲート電極とを形成し、
上記平坦化により、前記コントロールゲート電極、前記メモリゲート電極、前記複数の第6導体膜および前記複数の第7導体膜のそれぞれの上面の高さを揃える工程と、
をさらに有する、請求項8記載の半導体装置の製造方法。
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