CN108292516A - 金属浮栅在非易失性存储器中的集成 - Google Patents
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- 239000000758 substrate Substances 0.000 claims abstract description 28
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims description 27
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 20
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- 239000003989 dielectric material Substances 0.000 claims description 9
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 229910004200 TaSiN Inorganic materials 0.000 claims description 6
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 6
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 6
- 229910052593 corundum Inorganic materials 0.000 claims description 6
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
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- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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Abstract
本发明公开了一种非易失性存储器单元，所述非易失性存储器单元包括硅衬底、形成在所述硅衬底中的源极区和漏极区（其中所述衬底的沟道区被限定在所述源极区与所述漏极区之间）、设置在所述沟道区的第一部分上方并且与所述沟道区的第一部分绝缘的金属浮栅、设置在所述金属浮栅上方并且与所述金属浮栅绝缘的金属控制栅、设置在所述源极区上方并且与所述源极区绝缘的多晶硅擦除栅、以及设置在所述沟道区的第二部分上方并且与所述沟道区的第二部分绝缘的多晶硅字线栅。
Description
相关专利申请
本专利申请要求2015年11月3日提交的美国临时专利申请No. 62/250,002的权益，并且该专利申请以引用方式并入本文。
技术领域
本发明涉及非易失性存储器单元以及它们的制造。
背景技术
非易失性存储器器件在本领域中是公知的。例如，美国专利7,868,375（出于所有目的以引用方式并入本文）公开了具有浮栅、选择栅、擦除栅和控制栅的存储器单元。这些导电栅由多晶硅形成。当此类存储器单元与逻辑器件形成在同一晶圆上时，需要降低该存储器单元的总高度，使得该存储器单元的高度更好地匹配该逻辑器件的较低高度（即，该存储器单元和它们的形成与该逻辑器件和它们的形成更加相容）。因此，不断努力缩小存储器堆叠的高度（其包括浮栅和控制栅）。然而，对这些多晶硅栅极的尺寸进行缩小可能是有问题的。例如，缩小多晶硅浮栅的厚度可以导致在编程和/或擦除操作期间电子通过浮栅并进入多晶硅层间电介质的弹道传输，从而引起可靠性问题。
发明内容
上述问题和需求通过一种非易失性存储器单元来处理，其包括硅衬底、形成在该硅衬底中的源极区和漏极区（其中该衬底的沟道区被限定在该源极区与该漏极区之间）、设置在该沟道区的第一部分上方并且与沟道区的第一部分绝缘的金属浮栅、设置在该金属浮栅上方并且与金属浮栅绝缘的金属控制栅、设置在该源极区上方并且与源极区绝缘的多晶硅擦除栅以及设置在该沟道区的第二部分上方并且与沟道区的第二部分绝缘的多晶硅字线栅。
一种形成非易失性存储单元的方法，包括：在硅衬底中形成源极区和漏极区，其中该衬底的沟道区限定在该源极区与该漏极区之间；在该衬底上形成第一绝缘层；在该第一绝缘层上和该沟道区的第一部分上方形成金属浮栅；在该金属浮栅上形成第二绝缘层；在该第二绝缘层上和该金属浮栅上方形成金属控制栅；在该源极区上方形成并且与源极区绝缘的多晶硅擦除栅；并且在该沟道区的第二部分上方形成并且与沟道区的第二部分绝缘的多晶硅字线栅。
通过查看说明书、权利要求书和附图，本发明的其他目的和特征将变得显而易见。
附图说明
图1至图11为示出形成本发明的非易失性存储器单元的步骤的侧面剖视图。
具体实施方式
本发明提供以降低通过浮栅的弹道传输的方式缩小存储器单元高度的能力。图1示出了形成该存储器单元的工艺的开端。从硅衬底10开始，通过在衬底10上方形成氧化物层16以及在氧化物层16上方形成氮化物层18，从而在该衬底中形成隔离区12（其间限定有源区14）。除了保留暴露的隔离区12之外，使用光刻掩模步骤来覆盖具有光致抗蚀剂的结构，由此氧化物、氮化物和衬底硅被蚀刻以形成向下延伸到衬底10中的沟槽20。这些沟槽然后通过氧化物沉积和氧化物CMP（化学机械抛光）和氧化物退火而填充有氧化物22，如图1所示。这种形成STI（浅沟槽隔离）氧化物的隔离区的技术在本领域中是公知的，并且不会进一步讨论。
下面讨论的存储器单元的形成在相邻STI隔离区12之间的有源区14中执行。在移除氮化物18和氧化物16之后，在衬底10上方形成浮栅(FG)绝缘层24。绝缘层24可以是SiO2、SiON、高K电介质（即，介电常数K大于氧化物的绝缘材料，氧化物诸如HfO2、ZrO2、TiO2、Ta2O5、Al2O3、氮化处理的氧化物或其他适当的材料等）或IL/HK堆叠（其中该界面层(IL)是设置在该衬底上的薄氧化硅层，并且HK层设置在该IL层上）。使用IL/HK堆叠将抑制从浮栅到沟道的隧穿泄漏，并且从而提高数据保留性能。然后在绝缘层24上沉积浮栅(FG)金属层26。该金属层26可以是具有接近硅导带的功函数WF的任何类型的金属/合金。用于金属层26的优选材料的示例包括TaN、TaSiN、TiN/TiAl/TiN（即TiN、TiAl和TiN的子层）、TiN/AlN/TiN（即TiN、AlN和TiN的子层）等。当IL/HK用于绝缘层24时，由于工艺兼容性，TiN对于金属层26是优选的。金属层26的厚度可以约为100A以获得更好的WF稳定性和工艺控制。金属层26不含多晶硅。所得结构（在有源区14中）示于图2中。
应当指出的是，TiN具有适用于PMOS (4.4 eV)的有效WF (EWF)。然而，随着铝(Al)掺入TiN层，EWF可以降低。可以引入钛铝(TiAl)、Al和一层或多层AlN以降低EWF。例如，用于TiN/TiAl/TiN的EWF可以降低至约1eV。AlN/TiN也可以将EWF降低至约0.5eV。TaN具有约3.75eV的有效WF，其更适合NMOS，并且可通过掺入Al来调整。
然后在金属层26上方形成栅极间电介质(IGD)层28。IGD层28可以使用一种或多种高K电介质材料，因为这将有效地降低弹道泄漏电流和相关的可靠性问题。高K IGD层28也将增加控制栅(CG)至浮栅(FG)的耦合比率以改善该程序性能。IGD层28的厚度可以约为100A-200A。可以施加后沉积RTP退火来使膜致密化，以改善其质量并改善可靠性。三子层IGD层28（即，HfO2/Al2O3/HfO2）是优选的，因为如果随后的退火温度高于其结晶温度，则仅使用HfO2可能具有较高的泄漏电流。然后在IGD层28上方沉积控制栅(CG)金属层30。CG金属层30可以是诸如TaN、TaSiN、TiN/TiAl/TiN、TiN/AlN/TiN、W等的n种类型的一种或多种金属的任何类型。CG金属层30的厚度可以约为200A。GC金属层30不含多晶硅。硬掩模层(HM)32然后形成在CG金属层30上。HM层32可以是氮化物、氮化物/氧化物/氮化物三层堆叠或任何其他适当的绝缘体。在CG/IGD/FG堆叠蚀刻期间，层32将防止干蚀刻损失。所得结构示于图3中。
执行光刻掩模步骤以在该结构上方形成光致抗蚀剂，并且选择性地移除该光致抗蚀剂以使下面HM层32的部分暴露。执行蚀刻工艺以移除HM层32和CG金属层30的暴露部分。对于氮化物HM层32，该蚀刻可以使用氮化物和金属TaN的蚀刻配方，使用IGD层28作为蚀刻停止层。然后通过定时干蚀刻移除IGD层28的暴露部分（HK或ONO）。所得结构示于图4中（在移除光致抗蚀剂之后）。该结构包括成对的存储器堆叠结构S1和S2。
氧化物和氮化物沉积在该结构上，之后进行氧化物和氮化物蚀刻以移除这些材料，除了沿着堆叠S1和S2的侧面的间隔物34之外。沿间隔物34形成牺牲间隔物36（例如，通过TEOS氧化物沉积和各向异性蚀刻），如图5所示。光致抗蚀剂38然后形成在堆叠S1与S2之间的区域（在此称为内叠层区域）中，并且部分地在堆叠S1和S2本身上方延伸。在堆叠S1和S2之外的那些区域（本文称为外堆叠区域）被光致抗蚀剂38保留暴露。然后执行WL Vt注入，之后进行氧化物蚀刻，以移除外部堆叠区域中的牺牲间隔物36，如图6所示。在移除光致抗蚀剂38之后，执行金属蚀刻以移除FG金属层26的那些暴露部分（即，未被堆叠S1和S2保护的那些部分）。然后优选通过HTO沉积、退火和蚀刻在堆叠S1和S2的侧面上形成氧化物间隔物40，如图7所示。可以在此时执行用于在同一晶圆上形成低压和高压（LV和HV）逻辑器件的工序。例如，可以使用掩模步骤来用光致抗蚀剂覆盖存储器单元区域和LV逻辑器件区域，同时保持HV逻辑器件区域的开放。然后可以执行RTO氧化物、HTO沉积、逻辑阱注入和LV阱激活步骤。
在外部堆叠区域上方然后形成光致抗蚀剂，并部分地在堆叠S1和S2上方形成光致抗蚀剂，以使内部堆叠区域保留暴露。然后对该内部堆叠区域执行HVII注入以形成源极区44（源极线SL）。然后使用氧化物蚀刻以从内部堆叠区域移除氧化物间隔物40和氧化物间隔物36以及氧化物层24。在移除光致抗蚀剂之后，然后执行HVII注入退火以完成源极区44的形成。通过在整个结构上沉积氧化物，如图8所示（其增加了间隔物40和氧化物层24的厚度），然后在内部堆叠区域和堆叠S1和S2上形成隧道氧化物层46。可以在此时执行用于形成LV和HV逻辑器件的附加工序。例如，可以执行掩模步骤和栅极氧化物层形成步骤，以在LV和HV逻辑器件区域中形成不同厚度的氧化物的层，从而准备形成逻辑栅。
在该结构上方沉积厚的多晶硅层（多晶硅）48，之后进行化学机械抛光以降低多晶硅层48到堆叠S1和S2的顶部的高度。使用进一步的多晶硅回蚀刻降低堆叠S1和S2顶部下方的多晶硅层48的高度。然后在该结构上沉积硬掩模（如，氮化物）层50，如图9所示。执行一系列掩模步骤以选择性地暴露逻辑区域中的氮化物和多晶硅的部分，之后进行氮化物/多晶硅蚀刻以形成导电多晶硅逻辑栅，并且选择性地暴露外部堆叠区域的部分，之后进行氮化物/多晶硅蚀刻以移除HM层50和多晶硅48的暴露部分，其限定最终将成为字线(WL)的其余多晶硅块48a的外边缘，如图10所示。移除光致抗蚀剂之后，执行MCEL掩模步骤，之后进行注入步骤。
通过氧化物和氮化物的沉积和蚀刻，在存储器区域中的结构旁边形成间隔物52。执行掩模和注入步骤以在存储器堆叠S1和S2的任一侧面上形成漏极区（也称为位线接触区）54。最终结构示于图11中。存储器单元成对形成，并且共享单一源极区44。每个存储器单元包括衬底10中的源极区44和漏极区54（其间限定沟道区56），设置在该沟道区的第一部分上方的金属浮栅26，设置在该源极区44上方并且与该源极区绝缘的多晶硅擦除栅48b，设置在该浮栅26上方并且与之绝缘的金属控制栅30，以及设置在该沟道区的第二部分上方并且与该沟道区的第二部分绝缘的多晶硅字线栅48a。通过使用金属浮栅和控制栅26/30来降低堆叠S1和S2的总高度，单元高度可以从大约1200A降低到大约600A-700A。
应当理解，本发明不限于上述和本文所示的一个或多个实施方案。例如，本文中对本发明的提及并不旨在限制任何权利要求或权利要求术语的范围，而是仅参考可由一项或多项权利要求涵盖的一个或多个特征。上文所述的材料、工艺和数值的示例仅为示例性的，而不应视为限制权利要求。此外，并非所有方法步骤都需要以所示出的确切顺序来执行，而是可按允许恰当形成本发明的存储器单元的任何顺序来执行。有些方法步骤可能会被忽略。控制栅可替代地由多晶硅而不是金属形成。最后，单个材料的层可以被形成为多个此类或类似材料的层，反之亦然。
应当指出，如本文所用，术语“在…上方”和“在…上”两者包容地包含“直接在…上”（之间未设置中间材料、元件或空间）和“间接在…上”（之间设置有中间材料、元件或空间）。类似地，术语“相邻”包括“直接相邻”（之间没有设置中间材料、元件或空间）和“间接相邻”（之间设置有中间材料、元件或空间），“安装到”包括“直接安装到”（之间没有设置中间材料、元件或空间）和“间接安装到”（之间设置有中间材料、元件或空间），并且“电耦合至”包括“直接电耦合至”（之间没有将元件电连接在一起的中间材料或元件）和“间接电耦合至”（之间有将元件电连接在一起的中间材料或元件）。例如，“在衬底上方”形成元件可包括在之间没有中间材料/元件的情况下在衬底上直接形成元件，以及在之间有一个或多个中间材料/元件的情况下在衬底上间接形成元件。
Claims (23)
1.一种非易失性存储器单元，包括：
硅衬底；
源极区和漏极区，所述源极区和所述漏极区形成在所述硅衬底中，其中所述衬底的沟道区限定在所述源极区与所述漏极区之间；
金属浮栅，所述金属浮栅设置在所述沟道区的第一部分上方并且与所述沟道区的第一部分绝缘；
金属控制栅，所述金属控制栅设置在所述金属浮栅上方并且与所述金属浮栅绝缘；
多晶硅擦除栅，所述多晶硅擦除栅设置在所述源极区上方并且与所述源极区绝缘；以及
多晶硅字线栅，所述多晶硅字线栅设置在所述沟道区的第二部分上方并且与所述沟道区的第二部分绝缘。
2.根据权利要求1所述的非易失性存储器单元，其中所述金属浮栅通过高K电介质材料的层与所述衬底绝缘。
3.根据权利要求2所述的非易失性存储器单元，其中所述高K电介质材料是HfO2、ZrO2、TiO2、Ta2O5、Al2O3、和氮化处理的氧化物中的至少一个。
4.根据权利要求2所述的非易失性存储器单元，其中所述金属浮栅还通过氧化物的层与所述衬底绝缘。
5.根据权利要求4所述的非易失性存储器单元，其中所述金属浮栅包括TiN。
6.根据权利要求1所述的非易失性存储器单元，其中所述金属浮栅包括TaN、TaSiN、TiN/TiAl/TiN、以及TiN/AlN/TiN中的至少一个。
7.根据权利要求1所述的非易失性存储器单元，其中所述金属浮栅包括Al以及TiN和TaN中的至少一个。
8.根据权利要求1所述的非易失性存储器单元，其中所述金属浮栅包括AlN和TiN。
9.根据权利要求1所述的非易失性存储器单元，其中所述金属控制栅通过一种或多种高K电介质材料与所述金属浮栅绝缘。
10.根据权利要求1所述的非易失性存储器单元，其中所述金属控制栅通过设置在HfO2的层之间的Al2O3的层与所述金属浮栅绝缘。
11.根据权利要求1所述的非易失性存储器单元，其中所述金属控制栅包括TaN、TaSiN、TiN/TiAl/TiN、TiN/AlN/TiN和W中的至少一个。
12.一种形成非易失性存储器单元的方法，包括：
在硅衬底中形成源极区和漏极区，其中所述衬底的沟道区限定在所述源极区与所述漏极区之间；
在所述衬底上形成第一绝缘层；
在所述第一绝缘层上和所述沟道区的第一部分上方形成金属浮栅；
在所述金属浮栅上形成第二绝缘层；
在所述第二绝缘层上和所述金属浮栅上方形成金属控制栅；
在所述源极区上方形成并且与所述源极区绝缘的多晶硅擦除栅；并且
在所述沟道区的第二部分上方形成并且与所述沟道区的第二部分绝缘的多晶硅字线栅。
13.根据权利要求12所述的方法，其中所述第一绝缘层包括高K电介质材料。
14.根据权利要求13所述的方法，其中所述高K电介质材料是HfO2、ZrO2、TiO2、Ta2O5、Al2O3、和氮化处理的氧化物中的至少一个。
15.根据权利要求12所述的方法，其中所述第一绝缘层包括氧化物层和高K电介质材料的层。
16.根据权利要求15所述的方法，其中所述金属浮栅包括TiN。
17.根据权利要求12所述的方法，其中所述金属浮栅包括TaN、TaSiN、TiN/TiAl/TiN、以及TiN/AlN/TiN中的至少一个。
18.根据权利要求12所述的方法，其中所述金属浮栅包括Al以及TiN和TaN中的至少一个。
19.根据权利要求12所述的方法，其中所述金属浮栅包括AlN和TiN。
20.根据权利要求12所述的方法，其中所述第二绝缘层的形成包括：
在所述金属浮栅上沉积绝缘材料；并且
使所述沉积的绝缘材料退火。
21.根据权利要求12所述的方法，其中所述第二绝缘层包括一个或多个高K电介质材料。
22.根据权利要求12所述的方法，其中所述第二绝缘层包括设置在HfO2的层之间的Al2O3的层。
23.根据权利要求12所述的方法，其中所述金属控制栅包括TaN、TaSiN、TiN/TiAl/TiN、TiN/AlN/TiN和W中的至少一个。
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| US10943996B2 (en) | 2016-11-29 | 2021-03-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing semiconductor device including non-volatile memories and logic devices |
| US10283512B2 (en) | 2016-11-29 | 2019-05-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US10325918B2 (en) * | 2016-11-29 | 2019-06-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US10714634B2 (en) | 2017-12-05 | 2020-07-14 | Silicon Storage Technology, Inc. | Non-volatile split gate memory cells with integrated high K metal control gates and method of making same |
| CN110010606B (zh) | 2018-01-05 | 2023-04-07 | 硅存储技术公司 | 衬底沟槽中具有浮栅的双位非易失性存储器单元 |
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