US20110127599A1 - Split Gate Non-volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing - Google Patents
Split Gate Non-volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing Download PDFInfo
- Publication number
- US20110127599A1 US20110127599A1 US13/023,443 US201113023443A US2011127599A1 US 20110127599 A1 US20110127599 A1 US 20110127599A1 US 201113023443 A US201113023443 A US 201113023443A US 2011127599 A1 US2011127599 A1 US 2011127599A1
- Authority
- US
- United States
- Prior art keywords
- gate
- floating gate
- region
- erase
- cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000004519 manufacturing process Methods 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 104
- 235000012239 silicon dioxide Nutrition 0.000 claims description 33
- 239000000377 silicon dioxide Substances 0.000 claims description 33
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- 239000002131 composite material Substances 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 6
- 230000005641 tunneling Effects 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims 4
- 239000002178 crystalline material Substances 0.000 claims 1
- 238000000926 separation method Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 34
- 230000008569 process Effects 0.000 description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 28
- 229920005591 polysilicon Polymers 0.000 description 28
- 229920002120 photoresistant polymer Polymers 0.000 description 23
- 239000000463 material Substances 0.000 description 15
- 125000006850 spacer group Chemical group 0.000 description 14
- 239000012212 insulator Substances 0.000 description 8
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 239000002784 hot electron Substances 0.000 description 4
- 239000007943 implant Substances 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
Definitions
- the present invention relates to a non-volatile flash memory cell which has a select gate, a floating gate, a control gate, and an erase gate having an overhang with the floating gate in a certain dimensional ratio.
- the present invention also relates to an array of such flash memory cells, and methods of manufacturing such cell and array.
- a split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate.
- the cell has a select gate insulated and spaced apart from a first portion of the channel region.
- the cell further has a floating gate insulated and spaced apart from a second portion of the channel region.
- the floating gate has a first end closest to the select gate and a second end furthest away from the select gate.
- An erase gate is insulated and spaced apart from the substrate and is closest to the second end of the floating gate.
- a control gate is insulated and spaced apart from the floating gate, the select gate and the erase gate and is positioned above the floating gate and is between the erase gate and the select gate.
- the erase gate further has two electrically connected portions: a first portion laterally adjacent to and insulated from the second end of the floating gate and a second portion overlying and insulated from the floating gate and is adjacent to the control gate.
- the second portion of the erase gate is separated from the floating gate by a first length measured in a direction substantially perpendicular to the direction from the first region to the second region.
- the second portion of the erase gate has an end closest to the control gate, and the first portion of the erase gate has an end closest to the floating gate.
- the second portion of the erase gate overlies the floating gate by a second length measured from the end of the second portion of the erase gate closest to the control gate to the end of the first portion of the erase gate closest to the floating gate in a direction substantially perpendicular to the first length direction.
- the ratio of the second length to the first length is between approximately 1.0 and 2.5.
- the present invention also relates to an array of the foregoing memory cells.
- FIG. 1A is a cross sectional view of an improved non-volatile memory cell of the present invention.
- FIG. 1B is an enlarged view of a portion of the cell shown in FIG. 1A , wherein the dimensional relationship between the overhang of the erase gate to the floating gate is shown in greater detail.
- FIG. 2 is a graph showing the improvement to erase efficiency by the improved cell of the present invention.
- FIGS. 3(A-L) are cross sectional views of one process to make one embodiment the memory cell of the present invention.
- FIGS. 4(A-L) are cross sectional views of another process to make another embodiment of the memory cell of the present invention.
- FIG. 1A there is shown a cross-sectional view of an improved non-volatile memory cell 10 of the present invention.
- the memory cell 10 is made in a substantially single crystalline substrate 12 , such as single crystalline silicon, which is of P conductivity type.
- a first region 14 of a second conductivity type Within the substrate 12 is a first region 14 of a second conductivity type. If the first conductivity type is P then the second conductivity type is N. Spaced apart from the first region is a second region 16 of the second conductivity type. Between the first region 14 and the second region 16 is a channel region 18 , which provides for the conduction of charges between the first region 14 and the second region 16 .
- a select gate 20 Positioned above, and spaced apart and insulated from the substrate 12 is a select gate 20 , also known as the word tine 20 .
- the select gate 20 is positioned over a first portion of the channel region 18 .
- the first portion of the channel region 18 immediately abuts the first region 14 .
- the select gate 20 has little or no overlap with the first region 14 .
- a floating gate 22 is also positioned above and is spaced apart and is insulated from the substrate 12 .
- the floating gate 22 is positioned over a second portion of the channel region 18 and a portion of the second region 16 .
- the second portion of the channel region 18 is different from the first portion of the channel region 18 .
- the floating gate 22 is laterally spaced apart and is insulated from and is adjacent to the select gate 20 .
- An erase gate 24 is positioned over and spaced apart from the second region 16 , and is insulated from the substrate 12 .
- the erase gate 24 is laterally insulated and spaced apart from the floating gate 22 .
- the select gate 20 is to one side of the floating gate 22 , with the erase gate 24 to another side of the floating gate 22 .
- a control gate 26 positioned above the floating gate 22 and insulated and spaced apart therefrom is a control gate 26 .
- the control gate 26 is insulated and spaced apart from the erase gate 24 and the select gate 20 and is positioned between the erase gate 24 and the select gate 20 .
- the erase gate 24 has a portion that overhangs the floating gate 22 . This is shown in greater detail in FIG. 1B .
- the erase gate 24 comprises of two parts that are electrically connected. In the preferred embodiment, the two parts form a monolithic structure, although it is within the present invention that the two parts can be separate parts and electrically connected.
- a first part of the erase gate. 24 is immediately laterally adjacent to the floating gate 22 and is above the second region 16 .
- the first part of the erase gate 24 has an end 32 that is closest to the floating gate 22 .
- the second part of the erase gate 24 is laterally adjacent to the control gate 26 and overhangs a portion of the floating gate 22 .
- the second part of the erase gate has an end 34 that is closest to the control gate 26 .
- the horizontal distance (as measured in the direction between the first region 14 and the second region 16 ) between the end 34 and the end 32 is called “EG Overhang” as shown in FIG. 1B .
- the second part of the erase gate 24 which is laterally adjacent to the control gate 26 and overhangs the floating gate 22 is also vertically spaced apart from the floating gate 22 .
- the vertical distance between the floating gate 22 . and the second part of the erase gate 24 , as measured in the “vertical” direction is called “Tax” as shown in FIG. 1B .
- the vertical distance of “Tox” is measured in a direction that is substantially perpendicular to the horizontal distance “EG Overhang”.
- the memory cell 10 erases by electrons tunneling through the Fowler-Nordheim mechanism, from the floating gate 22 to the erase gate. Further, to improve the erase mechanism, the floating gate 22 may have a sharp corner closest to the erase gate 24 to enhance the local electrical field during erase and in turn enhance the flow of electrons from the corner of the floating gate 22 to the erase gate 24 . It has been found that erase efficiency is enhanced when the ratio of “EG Overhang” to “Tox” is between approximately 1.0 and 2.5. This is shown in FIG. 2 . Referring to FIG. 2 , there is shown a graph 30 of FTV, CR, and Verase as functions of the ratio of “EG overhang”/“Tox”.
- C total is the total capacitance between the floating gate 22 and all surrounding nodes.
- CR is the coupling ratio between, the erase gate 24 and the floating gate 22 .
- CR C EG ⁇ FG /C total , where C EG ⁇ FG is the capacitance between the erase gate 24 and the floating gate 22 .
- Q FG is the net charge on the floating gate which corresponds to “1” state.
- FTV is the voltage difference between the erase gate 24 and the floating gate 22 required to erase the cell to “1” state.
- the electron tunneling barrier in the tunnel oxide adjacent to the corner of floating gate 22 is electrically exposed to the lower potential of the nearby coupling gate 26 , resulting in an increase of FTV, and in turn an increase of Verase.
- CR is increased, which also in turn increases Verase.
- the graph 30 shows a minimum of Verase when “EG Overhang”/“Tox” is at approximately 1.6. With Verase requirement reduced, the requirement on the charge pump is similarly reduced. Thus, erase efficiency is enhanced.
- the select gate 20 of the memory cell 10 is separated from the floating gate by an insulating region W 1 .
- the region W 1 is silicon dioxide. This is called the cell 10 option A.
- the region W 1 is a composite layer comprising silicon dioxide, silicon nitride, and silicon dioxide, and this embodiment is called the cell 10 option B.
- FIGS. 3(A-L) there is shown cross-sectional views of the steps in the process to make a cell 10 option A of the present invention.
- a layer of silicon dioxide 40 on the substrate 12 of P type single crystalline silicon.
- the layer 40 of silicon dioxide is on the order of 80-100 angstroms.
- a first layer 42 of polysilicon (or amorphous silicon) is deposited or formed on the layer 40 of silicon dioxide.
- the first layer 42 of polysilicon is on the order of 300-800 angstroms.
- the first layer 42 of polysilicon is subsequently patterned in a direction perpendicular to the select gate 20 .
- the layer 48 is a composite layer, comprising silicon nitride 48 a , silicon dioxide 48 b , and silicon nitride 48 c .
- the dimensions are 200-600 angstroms for layer 48 a, 200-600 angstroms for layer 48 b , and 500-3000 angstroms for layer 48 c.
- FIG. 3C there is shown a cross sectional view of the next step in the process of making the cell 10 option A of the present invention.
- Photoresist material (not shown) is deposited on the structure shown in FIG. 3B , and a masking step is formed exposing selected portions of the photoresist material.
- the photoresist is developed and using the photoresist as a mask, the structure is etched.
- the composite layer 48 , the second layer 46 of polysilicon, the insulating layer 44 are then anisotropically etched, until the first layer 42 of polysilicon is exposed.
- the resultant structure is shown in FIG. 3C .
- S 1 and S 2 are shown, it should be clear that there are number of such “stacks” that are separated from one another.
- FIG. 3D there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention.
- Silicon dioxide 49 is deposited or formed on the structure. This is followed by the deposition of silicon nitride layer 50 .
- the silicon dioxide 49 and silicon nitride 50 are anisotropically etched leaving a spacer 51 (which is the combination of the silicon dioxide 49 and silicon nitride 50 ) around each of the stacks S 1 and S 2 .
- the resultant structure is shown in FIG. 3D .
- FIG. 3E there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention.
- a photoresist mask is formed over the regions between the stacks S 1 and S 2 , and other alternating pairs stacks.
- this region between the stacks S 1 and S 2 will be called the “inner region” and the regions not covered by the photoresist, shall be referred to as the “outer regions”.
- the exposed first polysilicon 42 in the outer regions is anisotropically etched.
- the oxide layer 40 is similarly anisotropically etched.
- the resultant structure is shown in FIG. 3E .
- FIG. 3F there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention.
- the photoresist material is removed from the structure shown in FIG. 3E .
- a layer of oxide 52 is then deposited or formed.
- the oxide layer 52 is then subject to an anisotropical etch leaving spacers 52 , adjacent to the stacks S 1 and S 2 .
- the resultant structure is shown in FIG. 3F .
- FIG. 3G there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention.
- Photoresist material is then deposited and is masked leaving openings in the inner regions between the stacks S 1 and S 2 .
- the photoresist is between other alternating pairs of stacks.
- the polysilicon 42 in the inner regions between the stacks S 1 and S 2 (and other alternating pairs of stacks) is anisotropically etched.
- the silicon dioxide layer 40 beneath the polysilicon 42 may also be anisotropically etched.
- the resultant structure is subject to a high voltage ion implant forming the second regions 16 .
- the resultant structure is shown in FIG. 3G .
- FIG. 3H there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention.
- the oxide spacer 52 adjacent to the stacks S 1 and S 2 in the inner region is removed by e.g. a wet etch or a dry isotropic etch.
- the resultant structure is shown in FIG. 3H .
- FIG. 3I there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention.
- the photoresist material in the outer regions of the stacks S 1 and S 2 is removed.
- Silicon dioxide 54 is deposited or formed everywhere.
- the resultant structure is shown in FIG. 31 .
- FIG. 3J there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention.
- the structure is once again covered by photoresist material and a masking step is performed exposing the outer regions of the stacks S 1 and S 2 and leaving photoresist material covering the inner region between the stacks S 1 and S 2 .
- An oxide anisotropical etch is performed, to reduce the thickness of the spacer 54 in the outer regions of the stack S 1 and S 2 , and to completely remove silicon dioxide from the exposed silicon substrate 12 in the outer regions.
- the resultant structure is shown in FIG. 3J .
- FIG. 3K there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention.
- This oxide layer 56 is the gate oxide between the select gate and the substrate 12 .
- the resultant structure is shown in FIG. 3K .
- FIG. 3L there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention.
- Polysilicon 60 is deposited everywhere.
- the layer 60 of polysilicon is then subject to an anisotropical etch forming spacers in the outer regions of the stack S 1 and S 2 which form the select gates 20 of two memory cells 10 adjacent to one another sharing a common second region 16 .
- the spacers within the inner regions of the stacks S 1 and S 2 are merged together forming a single erase gate 24 which is shared by the two adjacent memory cells 10 .
- a layer of insulator 62 is deposited on the structure, and etched anisotropically to form spacers 62 next to the select gates 20 .
- insulator 62 is a composite layer comprising silicon dioxide and silicon nitride. Thereafter, an ion implant step is performed forming the first regions 14 . Each of these memory cells on another side share a common first region 14 . Insulators and metallization layers are subsequently deposited and patterned to form bit line 70 and bit line contacts 72 .
- FIGS. 4(A-L) there is shown cross-sectional views of the steps in the process to make a cell 10 option B of the present invention.
- the steps and the description set forth hereinafter are similar to the steps and description above for the method of forming the memory cells 10 option A shown and described in FIGS. 3(A-L) .
- the same numbers will be used for the same parts.
- FIG. 4A there is shown the formation of a layer of silicon dioxide 40 on the substrate 12 of P type single crystalline silicon.
- the layer 40 of silicon dioxide is on the order of 80-100 angstroms.
- a first layer 42 of polysilicon is deposited or formed on the layer 40 of silicon dioxide.
- the first layer 42 of polysilicon is on the order of 300-800 angstroms.
- the first layer 42 of polysilicon is subsequently patterned in a direction perpendicular to the select gate 20 .
- FIG. 4B there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention.
- Another insulating layer 44 such as silicon dioxide (or even a composite layer, such as ONO) is deposited or formed on the first layer 42 of polysilicon. Depending on whether the material is silicon dioxide or ONO, the layer 44 can be on the order of 100-200 angstroms.
- a second layer 46 of polysilicon is then deposited or formed on the layer 44 .
- the second layer 46 of polysilicon is on the order of 500-4000 angstroms thick.
- Another layer 48 of insulator is deposited or formed on the second layer 46 of polysilicon and used as a hard mask during subsequent dry etching.
- the layer 48 is a composite layer, comprising silicon nitride 48 a , silicon dioxide 48 b , and silicon nitride 48 c .
- the dimensions are 200-600 angstroms for layer 48 a, 200-600 angstroms for layer 48 b , and 500-3000 angstroms for layer 48 c.
- FIG. 4C there is shown a cross sectional view of the next step in the process of making the cell 10 option B of the present invention.
- Photoresist material (not shown) is deposited on the structure shown. in FIG. 4B , and a masking step is formed exposing selected portions of the photoresist material.
- the photoresist is developed and using the photoresist as a mask, the structure is etched.
- the composite layer 48 , the second layer 46 of polysilicon, the insulating layer 44 are then anisotropically etched, until the first layer 42 of polysilicon is exposed.
- the resultant structure is shown in FIG. 4C .
- S 1 and S 2 are shown, it should be clear that there are number of such “Stacks” that are separated from one another.
- FIG. 4D there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention.
- a photoresist mask is formed over the regions between the stacks S 1 and S 2 , and other alternating pairs stacks.
- this region between the stacks S 1 and S 2 will be called the “inner region” and the regions not covered by the photoresist, shall be referred to as the “outer regions”.
- the exposed first polysilicon 42 in the outer regions is anisotropically etched.
- the oxide layer 40 is similarly anisotropically etched.
- the resultant structure is shown in FIG. 4D .
- FIG. 4F there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention.
- a layer of oxide 52 is then deposited or formed.
- the oxide layer 52 is then subject to an anisotropical etch leaving spacers 52 , adjacent to the stacks S 1 and S 2 .
- the resultant structure is shown in FIG. 4F .
- FIG. 4H there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention.
- the oxide spacer 52 adjacent to the stacks S 1 and S 2 in the inner region is removed by e.g. a wet etch or a dry isotropic etch.
- the resultant structure is shown in FIG. 4H .
- FIG. 4I there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention.
- the photoresist material in the outer regions of the stacks S 1 and S 2 is removed.
- Silicon dioxide 54 is deposited or formed everywhere.
- the resultant structure is shown in FIG. 4I .
- FIG. 4J there is shown. cross sectional view of the next steps in the process of making the cell 10 option B of the present invention.
- the structure is once again covered by photoresist material and a masking step is performed exposing the outer regions of the stacks S 1 and S 2 and leaving photoresist material covering the inner region between the stacks S 1 and S 2 .
- An oxide anisotropical etch is performed, to reduce the thickness of the oxide spacer 54 in the outer regions of the stack S 1 and S 2 , and to completely remove silicon dioxide from the exposed silicon substrate 12 in the outer regions.
- the resultant structure is shown in FIG. 4J .
- FIG. 4K there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention.
- This oxide layer 56 is the gate oxide between the select gate and the substrate 12 .
- the resultant structure is shown in FIG. 4J .
- FIG. 4L there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention.
- Polysilicon 60 is deposited everywhere.
- the layer 60 of polysilicon is then subject to an anisotropiesl etch forming spacers in the outer regions of the stack S 1 and S 2 which form the select gates 20 of two memory cells 10 adjacent to one another sharing a common second region 16 .
- the spacers within the inner regions of the stacks S 1 and S 2 are merged together forming a single erase gate 24 which is shared by the two adjacent memory cells 10 .
- a layer of insulator 62 is deposited on the structure, and etched anisotropically to form spacers 62 next to the select gates 20 .
- insulator 62 is a composite layer comprising silicon dioxide and silicon nitride. Thereafter, an ion implant step is performed forming the first regions 14 . Each of these memory cells on another side share a common first region 14 . Insulators and metallization layers are subsequently deposited and patterned to form bit line 70 and bit line contacts 72 .
- the operating conditions may also be different.
- the following voltages may be applied.
- a negative voltage on the order of ⁇ 6 to ⁇ 9 volts may be applied to the select control gate 26 .
- the voltage applied to the select erase gate 24 may be lowered to approximately 7-9 volts.
- the “overhang” of the erase gate 24 shields the tunneling barrier from the negative voltage applied to the select control gate 26 .
- the following voltages may be applied.
- the selected cell is programmed through efficient hot-electron injection with the portion of the channel under the floating gate in inversion.
- the medium voltage of 3-6 volts is applied to the select SL to generate the hot electrons.
- the select control gate 26 and erase gate 24 are biased to a high voltage (6-9 volts) to utilize the high coupling ratio and to maximize the voltage coupling to the floating gate.
- the high voltage coupled to the floating gate induces FG channel inversion and concentrates lateral field in the split area to generate hot electrons more effectively.
- the voltages provide a high vertical field to attract hot electron into the floating gate and reduce injection energy barrier.
- the voltages on the select control gate 26 and the select erase gate 24 can be balanced because each is coupled to the floating gate.
- the voltages applied to each of the select control gate 26 and select erase gate 24 can be a combination of voltages ranging from 0 to 3.7V to achieve optimum window.
- voltage on the select control gate is unfavorable due to the RC coupling, voltages on the select erase gate 24 can result in a faster read operation.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Abstract
An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
Description
- This application is a continuation of U.S. application Ser. No. 11/834,574, filed Aug. 6, 2007, the entire contents of which is incorporated herein by reference.
- The present invention relates to a non-volatile flash memory cell which has a select gate, a floating gate, a control gate, and an erase gate having an overhang with the floating gate in a certain dimensional ratio. The present invention also relates to an array of such flash memory cells, and methods of manufacturing such cell and array.
- Split gate non-volatile flash memory cells having a select gate, a floating gate, a control gate and an erase gate are well known in the art. See for example U.S. Pat. No. 6,747,310. An erase gate having an overhang over the floating gate is also well know in the art. See for example, U.S. Pat. No. 5,242,848. Both of the foregoing disclosures are incorporated herein by reference in their entirety.
- Heretofore, the prior art has failed to teach or disclose that an overhang of the erase gate to the floating gate within certain limitations enhances the erase efficiency.
- Accordingly, it is one of the objectives of the present invention to improve the erase efficiency of such a cell by certain dimensional relationship between the erase gate and the floating gate.
- In the present invention, a split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate insulated and spaced apart from a first portion of the channel region. The cell further has a floating gate insulated and spaced apart from a second portion of the channel region. The floating gate has a first end closest to the select gate and a second end furthest away from the select gate. An erase gate is insulated and spaced apart from the substrate and is closest to the second end of the floating gate. A control gate is insulated and spaced apart from the floating gate, the select gate and the erase gate and is positioned above the floating gate and is between the erase gate and the select gate. The erase gate further has two electrically connected portions: a first portion laterally adjacent to and insulated from the second end of the floating gate and a second portion overlying and insulated from the floating gate and is adjacent to the control gate. The second portion of the erase gate is separated from the floating gate by a first length measured in a direction substantially perpendicular to the direction from the first region to the second region. The second portion of the erase gate has an end closest to the control gate, and the first portion of the erase gate has an end closest to the floating gate. The second portion of the erase gate overlies the floating gate by a second length measured from the end of the second portion of the erase gate closest to the control gate to the end of the first portion of the erase gate closest to the floating gate in a direction substantially perpendicular to the first length direction. Finally, the ratio of the second length to the first length is between approximately 1.0 and 2.5.
- The present invention also relates to an array of the foregoing memory cells.
-
FIG. 1A is a cross sectional view of an improved non-volatile memory cell of the present invention. -
FIG. 1B is an enlarged view of a portion of the cell shown inFIG. 1A , wherein the dimensional relationship between the overhang of the erase gate to the floating gate is shown in greater detail. -
FIG. 2 is a graph showing the improvement to erase efficiency by the improved cell of the present invention. -
FIGS. 3(A-L) are cross sectional views of one process to make one embodiment the memory cell of the present invention. -
FIGS. 4(A-L) are cross sectional views of another process to make another embodiment of the memory cell of the present invention. - Referring to
FIG. 1A there is shown a cross-sectional view of an improved non-volatile memory cell 10 of the present invention. The memory cell 10 is made in a substantially singlecrystalline substrate 12, such as single crystalline silicon, which is of P conductivity type. Within thesubstrate 12 is afirst region 14 of a second conductivity type. If the first conductivity type is P then the second conductivity type is N. Spaced apart from the first region is asecond region 16 of the second conductivity type. Between thefirst region 14 and thesecond region 16 is achannel region 18, which provides for the conduction of charges between thefirst region 14 and thesecond region 16. - Positioned above, and spaced apart and insulated from the
substrate 12 is a select gate 20, also known as the word tine 20. The select gate 20 is positioned over a first portion of thechannel region 18. The first portion of thechannel region 18, immediately abuts thefirst region 14. Thus, the select gate 20 has little or no overlap with thefirst region 14. A floating gate 22 is also positioned above and is spaced apart and is insulated from thesubstrate 12. The floating gate 22 is positioned over a second portion of thechannel region 18 and a portion of thesecond region 16. The second portion of thechannel region 18 is different from the first portion of thechannel region 18. Thus, the floating gate 22 is laterally spaced apart and is insulated from and is adjacent to the select gate 20. An erase gate 24 is positioned over and spaced apart from thesecond region 16, and is insulated from thesubstrate 12. The erase gate 24 is laterally insulated and spaced apart from the floating gate 22. The select gate 20 is to one side of the floating gate 22, with the erase gate 24 to another side of the floating gate 22. Finally, positioned above the floating gate 22 and insulated and spaced apart therefrom is a control gate 26. The control gate 26 is insulated and spaced apart from the erase gate 24 and the select gate 20 and is positioned between the erase gate 24 and the select gate 20. Thus far, the foregoing description of the memory cell 10 is disclosed in U.S. Pat. No. 6,747,310. - In the improvement of the present invention, the erase gate 24 has a portion that overhangs the floating gate 22. This is shown in greater detail in
FIG. 1B . The erase gate 24 comprises of two parts that are electrically connected. In the preferred embodiment, the two parts form a monolithic structure, although it is within the present invention that the two parts can be separate parts and electrically connected. A first part of the erase gate. 24 is immediately laterally adjacent to the floating gate 22 and is above thesecond region 16. The first part of the erase gate 24 has an end 32 that is closest to the floating gate 22. The second part of the erase gate 24 is laterally adjacent to the control gate 26 and overhangs a portion of the floating gate 22. The second part of the erase gate has an end 34 that is closest to the control gate 26. The horizontal distance (as measured in the direction between thefirst region 14 and the second region 16) between the end 34 and the end 32 is called “EG Overhang” as shown inFIG. 1B . The second part of the erase gate 24 which is laterally adjacent to the control gate 26 and overhangs the floating gate 22 is also vertically spaced apart from the floating gate 22. The vertical distance between the floating gate 22. and the second part of the erase gate 24, as measured in the “vertical” direction is called “Tax” as shown inFIG. 1B . The vertical distance of “Tox” is measured in a direction that is substantially perpendicular to the horizontal distance “EG Overhang”. - As described in U.S. Pat. No. 6,747,310, the memory cell 10 erases by electrons tunneling through the Fowler-Nordheim mechanism, from the floating gate 22 to the erase gate. Further, to improve the erase mechanism, the floating gate 22 may have a sharp corner closest to the erase gate 24 to enhance the local electrical field during erase and in turn enhance the flow of electrons from the corner of the floating gate 22 to the erase gate 24. It has been found that erase efficiency is enhanced when the ratio of “EG Overhang” to “Tox” is between approximately 1.0 and 2.5. This is shown in
FIG. 2 . Referring toFIG. 2 , there is shown a graph 30 of FTV, CR, and Verase as functions of the ratio of “EG overhang”/“Tox”. Verase is the voltage applied to the erase gate 24 during the erase operation, which can sufficiently erase the cell to “1” State. Verase=(FTV+QFG/Ctotal)/(1-CR). Ctotal is the total capacitance between the floating gate 22 and all surrounding nodes. CR is the coupling ratio between, the erase gate 24 and the floating gate 22. CR=CEG−FG/Ctotal, where CEG−FG is the capacitance between the erase gate 24 and the floating gate 22. QFG is the net charge on the floating gate which corresponds to “1” state. FTV is the voltage difference between the erase gate 24 and the floating gate 22 required to erase the cell to “1” state. When “EG overhang” is significantly smaller than “Tox”, the electron tunneling barrier in the tunnel oxide adjacent to the corner of floating gate 22 is electrically exposed to the lower potential of the nearby coupling gate 26, resulting in an increase of FTV, and in turn an increase of Verase. When “EG overhang” is significantly larger than “Tox”, CR is increased, which also in turn increases Verase. As shown inFIG. 2 , the graph 30 shows a minimum of Verase when “EG Overhang”/“Tox” is at approximately 1.6. With Verase requirement reduced, the requirement on the charge pump is similarly reduced. Thus, erase efficiency is enhanced. - There are two embodiments of the memory cell 10 of the present invention. The select gate 20 of the memory cell 10 is separated from the floating gate by an insulating region W1. In the first embodiment of the memory cell 10, the region W1 is silicon dioxide. This is called the cell 10 option A. In the second embodiment of the memory cell 10, the region W1 is a composite layer comprising silicon dioxide, silicon nitride, and silicon dioxide, and this embodiment is called the cell 10 option B.
- Referring to
FIGS. 3(A-L) there is shown cross-sectional views of the steps in the process to make a cell 10 option A of the present invention. Commencing withFIG. 3A , there is shown the formation of a layer ofsilicon dioxide 40 on thesubstrate 12 of P type single crystalline silicon. For the 90 n nm (or 120 nm) process, thelayer 40 of silicon dioxide is on the order of 80-100 angstroms. Thereafter afirst layer 42 of polysilicon (or amorphous silicon) is deposited or formed on thelayer 40 of silicon dioxide. Again for purpose of explanation for the 90 nm process, thefirst layer 42 of polysilicon is on the order of 300-800 angstroms. Thefirst layer 42 of polysilicon is subsequently patterned in a direction perpendicular to the select gate 20. - Referring to
FIG. 3B there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention. Another insulatinglayer 44, such as silicon dioxide (or even a composite layer, such as ONO) is deposited or formed on thefirst layer 42 of polysilicon. Depending on whether the material is silicon dioxide or ONO, thelayer 44 can be on the order of 100-200 angstroms. Asecond layer 46 of polysilicon is then deposited or formed on thelayer 44. Thesecond layer 46 of polysilicon is on the order of 500-4000 angstroms thick. Anotherlayer 48 of insulator is deposited or formed on thesecond layer 46 of polysilicon and used as a hard mask during subsequent dry etching. In the preferred embodiment, thelayer 48 is a composite layer, comprising silicon nitride 48 a, silicon dioxide 48 b, and silicon nitride 48 c. In the preferred embodiment for the 90 nm process, the dimensions are 200-600 angstroms for layer 48 a, 200-600 angstroms for layer 48 b, and 500-3000 angstroms for layer 48 c. - Referring to
FIG. 3C there is shown a cross sectional view of the next step in the process of making the cell 10 option A of the present invention. Photoresist material (not shown) is deposited on the structure shown inFIG. 3B , and a masking step is formed exposing selected portions of the photoresist material. The photoresist is developed and using the photoresist as a mask, the structure is etched. Thecomposite layer 48, thesecond layer 46 of polysilicon, the insulatinglayer 44 are then anisotropically etched, until thefirst layer 42 of polysilicon is exposed. The resultant structure is shown inFIG. 3C . Although only two “stacks”: S1 and S2 are shown, it should be clear that there are number of such “stacks” that are separated from one another. - Referring to
FIG. 3D there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention.Silicon dioxide 49 is deposited or formed on the structure. This is followed by the deposition ofsilicon nitride layer 50. Thesilicon dioxide 49 andsilicon nitride 50 are anisotropically etched leaving a spacer 51 (which is the combination of thesilicon dioxide 49 and silicon nitride 50) around each of the stacks S1 and S2. The resultant structure is shown inFIG. 3D . - Referring to
FIG. 3E there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention. A photoresist mask is formed over the regions between the stacks S1 and S2, and other alternating pairs stacks. For the purpose of this discussion, this region between the stacks S1 and S2 will be called the “inner region” and the regions not covered by the photoresist, shall be referred to as the “outer regions”. The exposedfirst polysilicon 42 in the outer regions is anisotropically etched. Theoxide layer 40 is similarly anisotropically etched. The resultant structure is shown inFIG. 3E . - Referring to
FIG. 3F there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention. The photoresist material is removed from the structure shown inFIG. 3E . A layer ofoxide 52 is then deposited or formed. Theoxide layer 52 is then subject to an anisotropicaletch leaving spacers 52, adjacent to the stacks S1 and S2. The resultant structure is shown inFIG. 3F . - Referring to
FIG. 3G there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention. Photoresist material is then deposited and is masked leaving openings in the inner regions between the stacks S1 and S2. Again, similar to the drawing shown inFIG. 3E , the photoresist is between other alternating pairs of stacks. Thepolysilicon 42 in the inner regions between the stacks S1 and S2 (and other alternating pairs of stacks) is anisotropically etched. Thesilicon dioxide layer 40 beneath thepolysilicon 42 may also be anisotropically etched. The resultant structure is subject to a high voltage ion implant forming thesecond regions 16. The resultant structure is shown inFIG. 3G . - Referring to
FIG. 3H there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention. Theoxide spacer 52 adjacent to the stacks S1 and S2 in the inner region is removed by e.g. a wet etch or a dry isotropic etch. The resultant structure is shown inFIG. 3H . - Referring to
FIG. 3I there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention. The photoresist material in the outer regions of the stacks S1 and S2 is removed.Silicon dioxide 54 is deposited or formed everywhere. The resultant structure is shown inFIG. 31 . - Referring to
FIG. 3J there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention. The structure is once again covered by photoresist material and a masking step is performed exposing the outer regions of the stacks S1 and S2 and leaving photoresist material covering the inner region between the stacks S1 and S2. An oxide anisotropical etch is performed, to reduce the thickness of thespacer 54 in the outer regions of the stack S1 and S2, and to completely remove silicon dioxide from the exposedsilicon substrate 12 in the outer regions. The resultant structure is shown inFIG. 3J . - Referring to
FIG. 3K there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention. Athin layer 56 of silicon dioxide, on the order of 20-100 angstroms, is formed on the structure. Thisoxide layer 56 is the gate oxide between the select gate and thesubstrate 12. the resultant structure is shown inFIG. 3K . - Referring to
FIG. 3L there is shown a cross sectional view of the next steps in the process of making the cell 10 option A of the present invention. Polysilicon 60 is deposited everywhere. The layer 60 of polysilicon is then subject to an anisotropical etch forming spacers in the outer regions of the stack S1 and S2 which form the select gates 20 of two memory cells 10 adjacent to one another sharing a commonsecond region 16. In addition, the spacers within the inner regions of the stacks S1 and S2 are merged together forming a single erase gate 24 which is shared by the two adjacent memory cells 10. A layer ofinsulator 62 is deposited on the structure, and etched anisotropically to formspacers 62 next to the select gates 20. In the preferred embodiment,insulator 62 is a composite layer comprising silicon dioxide and silicon nitride. Thereafter, an ion implant step is performed forming thefirst regions 14. Each of these memory cells on another side share a commonfirst region 14. Insulators and metallization layers are subsequently deposited and patterned to formbit line 70 and bitline contacts 72. - Referring to
FIGS. 4(A-L) there is shown cross-sectional views of the steps in the process to make a cell 10 option B of the present invention. The steps and the description set forth hereinafter are similar to the steps and description above for the method of forming the memory cells 10 option A shown and described inFIGS. 3(A-L) . Thus, the same numbers will be used for the same parts. Commencing withFIG. 4A , there is shown the formation of a layer ofsilicon dioxide 40 on thesubstrate 12 of P type single crystalline silicon. For the 90 nm process, thelayer 40 of silicon dioxide is on the order of 80-100 angstroms. Thereafter afirst layer 42 of polysilicon (or amorphous silicon) is deposited or formed on thelayer 40 of silicon dioxide. Again for purpose of explanation for the 90 nm process, thefirst layer 42 of polysilicon is on the order of 300-800 angstroms. Thefirst layer 42 of polysilicon is subsequently patterned in a direction perpendicular to the select gate 20. - Referring to
FIG. 4B there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention. Another insulatinglayer 44, such as silicon dioxide (or even a composite layer, such as ONO) is deposited or formed on thefirst layer 42 of polysilicon. Depending on whether the material is silicon dioxide or ONO, thelayer 44 can be on the order of 100-200 angstroms. Asecond layer 46 of polysilicon is then deposited or formed on thelayer 44. Thesecond layer 46 of polysilicon is on the order of 500-4000 angstroms thick. Anotherlayer 48 of insulator is deposited or formed on thesecond layer 46 of polysilicon and used as a hard mask during subsequent dry etching. In the preferred embodiment, thelayer 48 is a composite layer, comprising silicon nitride 48 a, silicon dioxide 48 b, and silicon nitride 48 c. In the preferred embodiment for the 90 nm process, the dimensions are 200-600 angstroms for layer 48 a, 200-600 angstroms for layer 48 b, and 500-3000 angstroms for layer 48 c. - Referring to
FIG. 4C there is shown a cross sectional view of the next step in the process of making the cell 10 option B of the present invention. Photoresist material (not shown) is deposited on the structure shown. inFIG. 4B , and a masking step is formed exposing selected portions of the photoresist material. The photoresist is developed and using the photoresist as a mask, the structure is etched. Thecomposite layer 48, thesecond layer 46 of polysilicon, the insulatinglayer 44 are then anisotropically etched, until thefirst layer 42 of polysilicon is exposed. The resultant structure is shown inFIG. 4C . Although only two “stacks”: S1 and S2 are shown, it should be clear that there are number of such “Stacks” that are separated from one another. - Referring to
FIG. 4D there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention. A photoresist mask is formed over the regions between the stacks S1 and S2, and other alternating pairs stacks. For the purpose of this discussion, this region between the stacks S1 and S2 will be called the “inner region” and the regions not covered by the photoresist, shall be referred to as the “outer regions”. The exposedfirst polysilicon 42 in the outer regions is anisotropically etched. Theoxide layer 40 is similarly anisotropically etched. The resultant structure is shown inFIG. 4D . - Referring, to
FIG. 4E there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention.Silicon dioxide 49 is deposited or formed on the structure. This is followed by the deposition ofsilicon nitride layer 50. Thesilicon dioxide 49 andsilicon nitride 50 are anisotropically etched leaving a spacer 51 (which is the combination of thesilicon dioxide 49 and silicon nitride 50) around each of the stacks S1 and S2 (and all the other spaced apart stacks which are not shown). The resultant structure is shown inFIG. 4E . - Referring to
FIG. 4F there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention. A layer ofoxide 52 is then deposited or formed. Theoxide layer 52 is then subject to an anisotropicaletch leaving spacers 52, adjacent to the stacks S1 and S2. The resultant structure is shown inFIG. 4F . - Referring to
FIG. 4G there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention. Photoresist material is then deposited and is masked leaving openings in the inner regions between the stacks S1 and S2. Again, the photoresist is between other alternating pairs of stacks. Thepolysilicon 42 in the inner regions between the stacks S1 and S2 (and other alternating pairs of stacks) is anisotropically etched. Thesilicon dioxide layer 40 beneath thepolysilicon 42 may also be anisotropically etched. The resultant structure is subject to a high voltage ion implant forming thesecond regions 16. The resultant structure is shown inFIG. 4G . - Referring to
FIG. 4H there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention. Theoxide spacer 52 adjacent to the stacks S1 and S2 in the inner region is removed by e.g. a wet etch or a dry isotropic etch. The resultant structure is shown inFIG. 4H . - Referring to
FIG. 4I there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention. The photoresist material in the outer regions of the stacks S1 and S2 is removed.Silicon dioxide 54 is deposited or formed everywhere. The resultant structure is shown inFIG. 4I . - Referring to
FIG. 4J there is shown. cross sectional view of the next steps in the process of making the cell 10 option B of the present invention. The structure is once again covered by photoresist material and a masking step is performed exposing the outer regions of the stacks S1 and S2 and leaving photoresist material covering the inner region between the stacks S1 and S2. An oxide anisotropical etch is performed, to reduce the thickness of theoxide spacer 54 in the outer regions of the stack S1 and S2, and to completely remove silicon dioxide from the exposedsilicon substrate 12 in the outer regions. The resultant structure is shown inFIG. 4J . - Referring to
FIG. 4K there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention. Athin layer 56 of silicon dioxide, on the order of 20-100 angstroms, is formed on the structure. Thisoxide layer 56 is the gate oxide between the select gate and thesubstrate 12. the resultant structure is shown inFIG. 4J . - Referring to
FIG. 4L there is shown a cross sectional view of the next steps in the process of making the cell 10 option B of the present invention. Polysilicon 60 is deposited everywhere. The layer 60 of polysilicon is then subject to an anisotropiesl etch forming spacers in the outer regions of the stack S1 and S2 which form the select gates 20 of two memory cells 10 adjacent to one another sharing a commonsecond region 16. In addition, the spacers within the inner regions of the stacks S1 and S2 are merged together forming a single erase gate 24 which is shared by the two adjacent memory cells 10. A layer ofinsulator 62 is deposited on the structure, and etched anisotropically to formspacers 62 next to the select gates 20. In the preferred embodiment,insulator 62 is a composite layer comprising silicon dioxide and silicon nitride. Thereafter, an ion implant step is performed forming thefirst regions 14. Each of these memory cells on another side share a commonfirst region 14. Insulators and metallization layers are subsequently deposited and patterned to formbit line 70 and bitline contacts 72. - The operations of program, read and erase and in particular the voltages to be applied may be the same as those as set forth in U.S. Pat. No. 6,747,310, whose disclosure is incorporated herein by reference in its entirety.
- However, the operating conditions may also be different. For example, for erase operation, the following voltages may be applied.
-
WL (20) BL (70) SL (16) CG (26) EG (24) Select Unselect Select Unselect Select Unselect Select Unselect Select Unselect 0 v 0 v 0 v 0 v 0 v 0 v 0 v or 0 v 9-11 v 0 v −6 to or 7- −9 v 9 v - During erase, a negative voltage on the order of −6 to −9 volts may be applied to the select control gate 26. In that event, the voltage applied to the select erase gate 24 may be lowered to approximately 7-9 volts. The “overhang” of the erase gate 24 shields the tunneling barrier from the negative voltage applied to the select control gate 26.
- For programming, the following voltages may be applied.
-
WL (20) BL (70) SL (16) CG (26) EG (24) Select Unselect Select Unselect Select Unselect Select Unselect Select Unselect 1-2 v 0 v 0.5- 1.5-3 v 3-6 v 0 v 6-9 v 0 v 6-9 v 0 v 5 uA - During programming, the selected cell is programmed through efficient hot-electron injection with the portion of the channel under the floating gate in inversion. The medium voltage of 3-6 volts is applied to the select SL to generate the hot electrons. The select control gate 26 and erase gate 24 are biased to a high voltage (6-9 volts) to utilize the high coupling ratio and to maximize the voltage coupling to the floating gate. The high voltage coupled to the floating gate induces FG channel inversion and concentrates lateral field in the split area to generate hot electrons more effectively. In addition, the voltages provide a high vertical field to attract hot electron into the floating gate and reduce injection energy barrier.
- For reading, the following voltages may be applied.
-
WL (20) BL (70) SL (16) CG (26) EG (24) Select Unselect Select Unselect Select Unselect Select Unselect Select Unselect 1.5- 0 v 0.5- 0 v 0 v 0 v 0 v- 0 v 0 v- 0 v 3.7 v 1.5 v 3.7 V 3.7 V - During read, depending upon the balance between program and read operations, the voltages on the select control gate 26 and the select erase gate 24 can be balanced because each is coupled to the floating gate. Thus, the voltages applied to each of the select control gate 26 and select erase gate 24 can be a combination of voltages ranging from 0 to 3.7V to achieve optimum window. In addition, because voltage on the select control gate is unfavorable due to the RC coupling, voltages on the select erase gate 24 can result in a faster read operation.
Claims (12)
1. A non-volatile memory cell comprising:
a substrate of a substantially single crystalline material of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, spaced apart from the first region, forming a channel region therebetween;
a select gate insulated and spaced apart from a first portion of the channel region adjacent to the first region;
a floating gate insulated and spaced apart from a second portion of the channel region; the floating gate having a first end closest to the select gate and a second end furthest away from the select gate; said floating gate having a top surface and a bottom surface opposite thereto, with said bottom surface facing the channel region, said floating gate having a tip on the top surface and at the second end;
a tunneling barrier covering said tip, said barrier for permitting charges to pass therethrough during an erase operation;
a control gate having a top surface and a bottom surface opposite thereto, with said bottom surface insulated from and facing the top surface of the floating gate; said control gate insulated and adjacent to the selected gate, said control gate having a first end closest to the select gate and a second end furthest away from the select gate;
wherein said second end of the control gate is closer to a vertical line aligned with the first end of the floating gate than the second end of the floating gate, whereby a portion of the top surface of the floating gate is not facing the bottom surface of the control gate;
an erase gate having a first portion insulated and spaced apart from the second region of the substrate and having a first end separated from the second end of the floating gate, and a second portion electrically connected to the first portion, said second portion above the floating gate and insulated therefrom and adjacent to the control gate, said second portion of the erase gate shielding said tunneling barrier from the control gate, said second portion of the erase gate separated from the floating gate by a first length measured in a direction substantially perpendicular to the direction from the first region to the second region; said second portion having a second end closest to the second end of the control gate, said second portion of the erase gate having a second length measured from the second end of the second portion of the erase gate to a vertical line aligned with the first end of the first portion of the erase gate in a direction substantially parallel to the direction from the first region to the seconds region;
wherein said ratio of the second length to the first length is between approximately 1.0 and 2.5.
2. The cell of claim 1 wherein said two portions of the erase gate are monolithically formed.
3. The cell of claim 1 wherein said two portions of the erase gate are two separate portions electrically connected together.
4. The cell of claim 2 wherein said floating gate has a sharp corner, said corner being at the second end of the floating gate closest to the first portion of the erase gate.
5. The cell of claim 4 wherein the corner facilitates electron flow from the floating gate to the erase gate during the erase operation.
6. The cell of claim 2 wherein said floating gate is insulated and spaced apart from a portion of the second region.
7. The cell of claim 6 wherein the first portion of the channel region over which the select gate is insulated and spaced apart from abuts the first region.
8. The cell of claim 2 wherein said select gate is separated from the first end of the floating gate by a composite insulating material.
9. The cell of claim 8 wherein the composite insulating material is silicon dioxide and silicon nitride.
10. The cell of claim 2 wherein said select gate is separated from the first end of the floating gate by a homogeneous insulating material.
11. The cell of claim 10 wherein said homogeneous insulating material is silicon dioxide.
12-19. (canceled)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/023,443 US20110127599A1 (en) | 2007-08-06 | 2011-02-08 | Split Gate Non-volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/834,574 US20090039410A1 (en) | 2007-08-06 | 2007-08-06 | Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing |
US12/618,632 US7868375B2 (en) | 2007-08-06 | 2009-11-13 | Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing |
US12/961,193 US7927994B1 (en) | 2007-08-06 | 2010-12-06 | Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing |
US13/023,443 US20110127599A1 (en) | 2007-08-06 | 2011-02-08 | Split Gate Non-volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/961,193 Division US7927994B1 (en) | 2007-08-06 | 2010-12-06 | Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing |
Publications (1)
Publication Number | Publication Date |
---|---|
US20110127599A1 true US20110127599A1 (en) | 2011-06-02 |
Family
ID=40345645
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/834,574 Abandoned US20090039410A1 (en) | 2007-08-06 | 2007-08-06 | Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing |
US12/618,632 Active US7868375B2 (en) | 2007-08-06 | 2009-11-13 | Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing |
US12/961,193 Active US7927994B1 (en) | 2007-08-06 | 2010-12-06 | Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing |
US13/023,443 Abandoned US20110127599A1 (en) | 2007-08-06 | 2011-02-08 | Split Gate Non-volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing |
Family Applications Before (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/834,574 Abandoned US20090039410A1 (en) | 2007-08-06 | 2007-08-06 | Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing |
US12/618,632 Active US7868375B2 (en) | 2007-08-06 | 2009-11-13 | Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing |
US12/961,193 Active US7927994B1 (en) | 2007-08-06 | 2010-12-06 | Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing |
Country Status (5)
Country | Link |
---|---|
US (4) | US20090039410A1 (en) |
JP (1) | JP5361292B2 (en) |
KR (1) | KR20090014967A (en) |
CN (3) | CN102403274A (en) |
TW (1) | TWI393263B (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140054667A1 (en) * | 2012-08-23 | 2014-02-27 | Silicon Storage Technology, Inc. | Split-Gate Memory Cell With Depletion-Mode Floating Gate Channel, And Method Of Making Same |
US20140091382A1 (en) * | 2012-09-28 | 2014-04-03 | Silicon Storage Technology, Inc. | Split-Gate Memory Cell With Substrate Stressor Region, And Method Of Making Same |
US8785307B2 (en) | 2012-08-23 | 2014-07-22 | Silicon Storage Technology, Inc. | Method of forming a memory cell by reducing diffusion of dopants under a gate |
CN107221350A (en) * | 2017-05-15 | 2017-09-29 | 上海华虹宏力半导体制造有限公司 | Accumulator system, memory array and its reading and operation scheme for programming |
TWI676272B (en) * | 2016-11-29 | 2019-11-01 | 台灣積體電路製造股份有限公司 | Semiconductor device and manufacturing method thereof |
US11721731B2 (en) | 2021-08-03 | 2023-08-08 | Globalfoundries Singapore Pte. Ltd. | Nonvolatile memory having multiple narrow tips at floating gate |
Families Citing this family (187)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8320191B2 (en) | 2007-08-30 | 2012-11-27 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
JP5503843B2 (en) * | 2007-12-27 | 2014-05-28 | ルネサスエレクトロニクス株式会社 | Nonvolatile semiconductor memory device and manufacturing method thereof |
US20090267130A1 (en) * | 2008-04-28 | 2009-10-29 | International Business Machines Corporation | Structure and process integration for flash storage element and dual conductor complementary mosfets |
CN101882576B (en) * | 2009-05-06 | 2012-03-14 | 中芯国际集成电路制造(北京)有限公司 | Method for improving efficiency of erasing floating gate |
US8445953B2 (en) | 2009-07-08 | 2013-05-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure for flash memory cells |
US8470670B2 (en) * | 2009-09-23 | 2013-06-25 | Infineon Technologies Ag | Method for making semiconductor device |
CN102097384B (en) * | 2009-12-15 | 2013-05-29 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing storage device |
CN102104044B (en) * | 2009-12-17 | 2013-02-27 | 中芯国际集成电路制造(上海)有限公司 | Separate gate flash memory and manufacturing method thereof |
CN102263064A (en) * | 2010-05-28 | 2011-11-30 | 中芯国际集成电路制造(上海)有限公司 | Method for forming discrete grid storage device |
CN102386141B (en) * | 2010-08-27 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Method for preventing collapse of stacked grid line in split grid flash memory |
CN102543885A (en) * | 2010-12-31 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Split-gate memory device and forming method thereof |
CN102610575A (en) * | 2011-01-21 | 2012-07-25 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing separated gate electrode type flash memory unit |
KR101787488B1 (en) | 2011-03-24 | 2017-10-19 | 삼성전자주식회사 | Non-volatile memory device and method of forming the same |
US8384147B2 (en) * | 2011-04-29 | 2013-02-26 | Silicon Storage Technology, Inc. | High endurance non-volatile memory cell and array |
US8711636B2 (en) | 2011-05-13 | 2014-04-29 | Silicon Storage Technology, Inc. | Method of operating a split gate flash memory cell with coupling gate |
CN102956562B (en) * | 2011-08-22 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Memory device forming method |
CN102956643A (en) * | 2011-08-24 | 2013-03-06 | 硅存储技术公司 | Non-volatile floating gate storage unit manufacturing method and storage unit manufactured by same |
CN102969346B (en) * | 2011-08-31 | 2016-08-10 | 硅存储技术公司 | There is band and improve floating boom and the Nonvolatile memery unit of coupling grid of coupling ratio |
CN102299157B (en) * | 2011-09-01 | 2016-08-03 | 上海华虹宏力半导体制造有限公司 | Gate-division type flash memory and manufacture method thereof |
CN102270608B (en) * | 2011-09-01 | 2016-12-28 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of split-gate type flash memory |
US8488388B2 (en) * | 2011-11-01 | 2013-07-16 | Silicon Storage Technology, Inc. | Method of programming a split gate non-volatile floating gate memory cell having a separate erase gate |
US8513728B2 (en) * | 2011-11-17 | 2013-08-20 | Silicon Storage Technology, Inc. | Array of split gate non-volatile floating gate memory cells having improved strapping of the coupling gates |
US8804429B2 (en) | 2011-12-08 | 2014-08-12 | Silicon Storage Technology, Inc. | Non-volatile memory device and a method of programming such device |
CN103178018A (en) * | 2011-12-22 | 2013-06-26 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing separation gate quick-flashing memory unit |
US9330922B2 (en) | 2012-03-07 | 2016-05-03 | Silicon Storage Technology, Inc. | Self-aligned stack gate structure for use in a non-volatile memory array and a method of forming such structure |
US8811093B2 (en) | 2012-03-13 | 2014-08-19 | Silicon Storage Technology, Inc. | Non-volatile memory device and a method of operating same |
US8878281B2 (en) | 2012-05-23 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for non-volatile memory cells |
US8890230B2 (en) | 2012-07-15 | 2014-11-18 | United Microelectronics Corp. | Semiconductor device |
JP5936959B2 (en) * | 2012-09-04 | 2016-06-22 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
CN103715144B (en) * | 2012-09-29 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Discrete grid storage device and forming method thereof |
US9123401B2 (en) | 2012-10-15 | 2015-09-01 | Silicon Storage Technology, Inc. | Non-volatile memory array and method of using same for fractional word programming |
US8669607B1 (en) * | 2012-11-01 | 2014-03-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for non-volatile memory cells with increased programming efficiency |
JP6114534B2 (en) | 2012-11-07 | 2017-04-12 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method of semiconductor device |
US9472284B2 (en) | 2012-11-19 | 2016-10-18 | Silicon Storage Technology, Inc. | Three-dimensional flash memory system |
CN102983139B (en) * | 2012-11-30 | 2017-09-29 | 上海华虹宏力半导体制造有限公司 | Semiconductor memory |
US8946807B2 (en) | 2013-01-24 | 2015-02-03 | Micron Technology, Inc. | 3D memory |
US9293359B2 (en) | 2013-03-14 | 2016-03-22 | Silicon Storage Technology, Inc. | Non-volatile memory cells with enhanced channel region effective width, and method of making same |
KR101716998B1 (en) | 2013-03-14 | 2017-03-15 | 실리콘 스토리지 테크놀로지 인크 | Non-volatile memory program algorithm device and method |
US9275748B2 (en) * | 2013-03-14 | 2016-03-01 | Silicon Storage Technology, Inc. | Low leakage, low threshold voltage, split-gate flash cell operation |
US9184175B2 (en) | 2013-03-15 | 2015-11-10 | Micron Technology, Inc. | Floating gate memory cells in vertical memory |
US8867281B2 (en) | 2013-03-15 | 2014-10-21 | Silicon Storage Technology, Inc. | Hybrid chargepump and regulation means and method for flash memory device |
US9064970B2 (en) | 2013-03-15 | 2015-06-23 | Micron Technology, Inc. | Memory including blocking dielectric in etch stop tier |
US9276011B2 (en) | 2013-03-15 | 2016-03-01 | Micron Technology, Inc. | Cell pillar structures and integrated flows |
CN104157614A (en) * | 2013-05-14 | 2014-11-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method for separated grid type flash memory |
US9484261B2 (en) | 2013-07-05 | 2016-11-01 | Silicon Storage Technology, Inc. | Formation of self-aligned source for split-gate non-volatile memory cell |
US9431256B2 (en) * | 2013-07-11 | 2016-08-30 | United Microelectronics Corp. | Semiconductor device and manufacturing method thereof |
US9123822B2 (en) | 2013-08-02 | 2015-09-01 | Silicon Storage Technology, Inc. | Split gate non-volatile flash memory cell having a silicon-metal floating gate and method of making same |
US9048316B2 (en) * | 2013-08-29 | 2015-06-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Flash memory structure and method of forming the same |
US9437604B2 (en) | 2013-11-01 | 2016-09-06 | Micron Technology, Inc. | Methods and apparatuses having strings of memory cells including a metal source |
US20150155039A1 (en) | 2013-12-02 | 2015-06-04 | Silicon Storage Technology, Inc. | Three-Dimensional Flash NOR Memory System With Configurable Pins |
JP2015130438A (en) | 2014-01-08 | 2015-07-16 | ルネサスエレクトロニクス株式会社 | Semiconductor device and semiconductor device manufacturing method |
US9287282B2 (en) | 2014-01-28 | 2016-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a logic compatible flash memory |
US20150249158A1 (en) * | 2014-03-03 | 2015-09-03 | United Microelectronics Corp. | Semiconductor structure and method for manufacturing the same |
US20150263040A1 (en) | 2014-03-17 | 2015-09-17 | Silicon Storage Technology, Inc. | Embedded Memory Device With Silicon-On-Insulator Substrate, And Method Of Making Same |
US9159842B1 (en) * | 2014-03-28 | 2015-10-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Embedded nonvolatile memory |
JP6238235B2 (en) | 2014-06-13 | 2017-11-29 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US9614048B2 (en) * | 2014-06-17 | 2017-04-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Split gate flash memory structure and method of making the split gate flash memory structure |
US9691883B2 (en) * | 2014-06-19 | 2017-06-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Asymmetric formation approach for a floating gate of a split gate flash memory structure |
US9252150B1 (en) | 2014-07-29 | 2016-02-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | High endurance non-volatile memory cell |
US9286982B2 (en) * | 2014-08-08 | 2016-03-15 | Silicon Storage Technology, Inc. | Flash memory system with EEPROM functionality |
US10312246B2 (en) | 2014-08-08 | 2019-06-04 | Silicon Storage Technology, Inc. | Split-gate flash memory cell with improved scaling using enhanced lateral control gate to floating gate coupling |
US9391085B2 (en) * | 2014-08-08 | 2016-07-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-aligned split gate flash memory having liner-separated spacers above the memory gate |
US9660106B2 (en) * | 2014-08-18 | 2017-05-23 | United Microelectronics Corp. | Flash memory and method of manufacturing the same |
US9431407B2 (en) | 2014-09-19 | 2016-08-30 | Silicon Storage Technology, Inc. | Method of making embedded memory device with silicon-on-insulator substrate |
US10312248B2 (en) * | 2014-11-12 | 2019-06-04 | Silicon Storage Technology, Inc. | Virtual ground non-volatile memory array |
KR102240022B1 (en) * | 2014-11-26 | 2021-04-15 | 삼성전자주식회사 | Semicondcutor device and manufacturing method for the same |
US9276005B1 (en) * | 2014-12-04 | 2016-03-01 | Silicon Storage Technology, Inc. | Non-volatile memory array with concurrently formed low and high voltage logic devices |
US9379121B1 (en) | 2015-01-05 | 2016-06-28 | Silicon Storage Technology, Inc. | Split gate non-volatile flash memory cell having metal gates and method of making same |
US9276006B1 (en) | 2015-01-05 | 2016-03-01 | Silicon Storage Technology, Inc. | Split gate non-volatile flash memory cell having metal-enhanced gates and method of making same |
TWI594420B (en) * | 2015-01-13 | 2017-08-01 | Xinnova Tech Ltd | Non-volatile memory components and methods of making the same |
US9361995B1 (en) * | 2015-01-21 | 2016-06-07 | Silicon Storage Technology, Inc. | Flash memory system using complementary voltage supplies |
CN107210203B (en) | 2015-01-22 | 2020-10-16 | 硅存储技术公司 | High density split gate memory cell |
KR101998009B1 (en) * | 2015-01-22 | 2019-07-08 | 실리콘 스토리지 테크놀로지 인크 | Method for forming a discrete gate memory cell array with low voltage and high voltage logic devices |
CN107210202B (en) * | 2015-01-23 | 2018-11-09 | 硅存储技术公司 | The method for forming autoregistration splitting bar memory cell array with metal gate and logical device |
US9721958B2 (en) | 2015-01-23 | 2017-08-01 | Silicon Storage Technology, Inc. | Method of forming self-aligned split-gate memory cell array with metal gates and logic devices |
TWI606551B (en) * | 2015-02-16 | 2017-11-21 | Xinnova Tech Ltd | Non-volatile memory device method |
US9620216B2 (en) | 2015-02-17 | 2017-04-11 | Silicon Storage Technology, Inc. | Flash memory device configurable to provide read only memory functionality |
CN105990367B (en) | 2015-02-27 | 2019-03-12 | 硅存储技术公司 | Nonvolatile memory unit array with ROM cell |
US9793280B2 (en) | 2015-03-04 | 2017-10-17 | Silicon Storage Technology, Inc. | Integration of split gate flash memory array and logic devices |
US10134475B2 (en) | 2015-03-31 | 2018-11-20 | Silicon Storage Technology, Inc. | Method and apparatus for inhibiting the programming of unselected bitlines in a flash memory system |
CN106158027B (en) | 2015-04-09 | 2020-02-07 | 硅存储技术公司 | System and method for programming split-gate non-volatile memory cells |
US9917165B2 (en) * | 2015-05-15 | 2018-03-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory cell structure for improving erase speed |
US9608000B2 (en) | 2015-05-27 | 2017-03-28 | Micron Technology, Inc. | Devices and methods including an etch stop protection material |
US9431406B1 (en) * | 2015-05-28 | 2016-08-30 | Macronix International Co., Ltd. | Semiconductor device and method of forming the same |
US9672930B2 (en) | 2015-05-29 | 2017-06-06 | Silicon Storage Technology, Inc. | Low power operation for flash memory system |
US9793279B2 (en) | 2015-07-10 | 2017-10-17 | Silicon Storage Technology, Inc. | Split gate non-volatile memory cell having a floating gate, word line, erase gate, and method of manufacturing |
US9793281B2 (en) | 2015-07-21 | 2017-10-17 | Silicon Storage Technology, Inc. | Non-volatile split gate memory cells with integrated high K metal gate logic device and metal-free erase gate, and method of making same |
US9711513B2 (en) | 2015-08-14 | 2017-07-18 | Globalfoundries Inc. | Semiconductor structure including a nonvolatile memory cell and method for the formation thereof |
JP2017045755A (en) | 2015-08-24 | 2017-03-02 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method of the same |
JP6568751B2 (en) | 2015-08-28 | 2019-08-28 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
CN106531212B (en) | 2015-09-11 | 2020-02-07 | 硅存储技术公司 | Flash memory system using memory cells as source line pull-down circuits |
US9634019B1 (en) * | 2015-10-01 | 2017-04-25 | Silicon Storage Technology, Inc. | Non-volatile split gate memory cells with integrated high K metal gate, and method of making same |
US9634020B1 (en) * | 2015-10-07 | 2017-04-25 | Silicon Storage Technology, Inc. | Method of making embedded memory device with silicon-on-insulator substrate |
US9673208B2 (en) | 2015-10-12 | 2017-06-06 | Silicon Storage Technology, Inc. | Method of forming memory array and logic devices |
US10141321B2 (en) * | 2015-10-21 | 2018-11-27 | Silicon Storage Technology, Inc. | Method of forming flash memory with separate wordline and erase gates |
EP3371829B1 (en) | 2015-11-03 | 2020-11-25 | Silicon Storage Technology, Inc. | Integration of split gate non-volatile flash memory with finfet logic |
CN108292516A (en) * | 2015-11-03 | 2018-07-17 | 硅存储技术公司 | Metal floating boom in the nonvolatile memory integrated |
US9960176B2 (en) | 2015-11-05 | 2018-05-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Nitride-free spacer or oxide spacer for embedded flash memory |
US9548312B1 (en) | 2015-11-10 | 2017-01-17 | Globalfoundries Inc. | Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure including a nonvolatile memory cell |
US9583640B1 (en) * | 2015-12-29 | 2017-02-28 | Globalfoundries Inc. | Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure |
US9673210B1 (en) | 2016-02-25 | 2017-06-06 | Globalfoundries Inc. | Semiconductor structure including a nonvolatile memory cell having a charge trapping layer and method for the formation thereof |
CN107293546B (en) | 2016-04-08 | 2020-09-04 | 硅存储技术公司 | Reduced size split gate non-volatile flash memory cell and method of making same |
CN107305892B (en) * | 2016-04-20 | 2020-10-02 | 硅存储技术公司 | Method of forming tri-gate non-volatile flash memory cell pairs using two polysilicon deposition steps |
CN107316868B (en) * | 2016-04-22 | 2020-04-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
CN107342288B (en) * | 2016-04-29 | 2020-08-04 | 硅存储技术公司 | Split gate type dual bit non-volatile memory cell |
US9922986B2 (en) | 2016-05-16 | 2018-03-20 | Globalfoundries Inc. | Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cell and method for the formation thereof |
KR20190002708A (en) * | 2016-05-17 | 2019-01-08 | 실리콘 스토리지 테크놀로지 인크 | An array of three-gate flash memory cells with separate memory cell read, program, and erase |
US10269440B2 (en) | 2016-05-17 | 2019-04-23 | Silicon Storage Technology, Inc. | Flash memory array with individual memory cell read, program and erase |
WO2017200883A1 (en) | 2016-05-17 | 2017-11-23 | Silicon Storage Technology, Inc. | Deep learning neural network classifier using non-volatile memory array |
WO2017200709A1 (en) * | 2016-05-18 | 2017-11-23 | Silicon Storage Technology, Inc. | Method of making split gate non-volatile flash memory cell |
US9953719B2 (en) | 2016-05-18 | 2018-04-24 | Silicon Storage Technology, Inc. | Flash memory cell and associated decoders |
CN107425003B (en) | 2016-05-18 | 2020-07-14 | 硅存储技术公司 | Method of manufacturing split gate non-volatile flash memory cell |
US9911501B2 (en) | 2016-05-24 | 2018-03-06 | Silicon Storage Technology, Inc. | Sensing amplifier comprising a built-in sensing offset for flash memory devices |
US9972493B2 (en) * | 2016-08-08 | 2018-05-15 | Silicon Storage Technology, Inc. | Method of forming low height split gate memory cells |
US9997524B2 (en) * | 2016-08-24 | 2018-06-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor memory device and manufacturing method thereof |
TWI708373B (en) * | 2016-10-11 | 2020-10-21 | 聯華電子股份有限公司 | Flash memory structure |
CN106601749A (en) * | 2016-12-15 | 2017-04-26 | 武汉新芯集成电路制造有限公司 | Flash memory unit structure and discrete gate flash memory |
US10431265B2 (en) | 2017-03-23 | 2019-10-01 | Silicon Storage Technology, Inc. | Address fault detection in a flash memory system |
US10381088B2 (en) | 2017-03-30 | 2019-08-13 | Silicon Storage Technology, Inc. | System and method for generating random numbers based on non-volatile memory cell array entropy |
CN108695331B (en) * | 2017-04-05 | 2020-11-27 | 中芯国际集成电路制造(北京)有限公司 | Memory, programming method, erasing method, reading method and electronic device thereof |
US10192874B2 (en) * | 2017-06-19 | 2019-01-29 | United Microelectronics Corp. | Nonvolatile memory cell and fabrication method thereof |
US10199112B1 (en) | 2017-08-25 | 2019-02-05 | Silicon Storage Technology, Inc. | Sense amplifier circuit for reading data in a flash memory cell |
US10586598B2 (en) | 2017-09-14 | 2020-03-10 | Silicon Storage Technology, Inc. | System and method for implementing inference engine by optimizing programming operation |
US10534554B2 (en) | 2017-10-13 | 2020-01-14 | Silicon Storage Technology, Inc. | Anti-hacking mechanisms for flash memory device |
US10515694B2 (en) | 2017-11-03 | 2019-12-24 | Silicon Storage Technology, Inc. | System and method for storing multibit data in non-volatile memory |
US10699779B2 (en) | 2017-11-29 | 2020-06-30 | Silicon Storage Technology, Inc. | Neural network classifier using array of two-gate non-volatile memory cells |
US10803943B2 (en) | 2017-11-29 | 2020-10-13 | Silicon Storage Technology, Inc. | Neural network classifier using array of four-gate non-volatile memory cells |
US10748630B2 (en) | 2017-11-29 | 2020-08-18 | Silicon Storage Technology, Inc. | High precision and highly efficient tuning mechanisms and algorithms for analog neuromorphic memory in artificial neural networks |
US11087207B2 (en) | 2018-03-14 | 2021-08-10 | Silicon Storage Technology, Inc. | Decoders for analog neural memory in deep learning artificial neural network |
US10714634B2 (en) | 2017-12-05 | 2020-07-14 | Silicon Storage Technology, Inc. | Non-volatile split gate memory cells with integrated high K metal control gates and method of making same |
US10600484B2 (en) | 2017-12-20 | 2020-03-24 | Silicon Storage Technology, Inc. | System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory |
US10878897B2 (en) | 2018-01-04 | 2020-12-29 | Silicon Storage Technology, Inc. | System and method for storing and retrieving multibit data in non-volatile memory using current multipliers |
CN110021602B (en) | 2018-01-05 | 2023-04-07 | 硅存储技术公司 | Non-volatile memory cell with floating gate in dedicated trench |
CN110010606B (en) | 2018-01-05 | 2023-04-07 | 硅存储技术公司 | Dual bit non-volatile memory cell with floating gate in substrate trench |
US10312247B1 (en) | 2018-03-22 | 2019-06-04 | Silicon Storage Technology, Inc. | Two transistor FinFET-based split gate non-volatile floating gate flash memory and method of fabrication |
US10580491B2 (en) | 2018-03-23 | 2020-03-03 | Silicon Storage Technology, Inc. | System and method for managing peak power demand and noise in non-volatile memory array |
US10468428B1 (en) | 2018-04-19 | 2019-11-05 | Silicon Storage Technology, Inc. | Split gate non-volatile memory cells and logic devices with FinFET structure, and method of making same |
US10418451B1 (en) * | 2018-05-09 | 2019-09-17 | Silicon Storage Technology, Inc. | Split-gate flash memory cell with varying insulation gate oxides, and method of forming same |
US10790292B2 (en) | 2018-05-14 | 2020-09-29 | Silicon Storage Technology, Inc. | Method of making embedded memory device with silicon-on-insulator substrate |
CN108831829B (en) * | 2018-06-19 | 2020-10-27 | 上海华力微电子有限公司 | Side wall grid isolation etching film layer process under split gate structure |
US10727240B2 (en) | 2018-07-05 | 2020-07-28 | Silicon Store Technology, Inc. | Split gate non-volatile memory cells with three-dimensional FinFET structure |
US10714489B2 (en) * | 2018-08-23 | 2020-07-14 | Silicon Storage Technology, Inc. | Method of programming a split-gate flash memory cell with erase gate |
US10838652B2 (en) | 2018-08-24 | 2020-11-17 | Silicon Storage Technology, Inc. | Programming of memory cell having gate capacitively coupled to floating gate |
US10985272B2 (en) * | 2018-11-05 | 2021-04-20 | Samsung Electronics Co., Ltd. | Integrated circuit devices including vertical field-effect transistors |
TWI694592B (en) | 2018-11-09 | 2020-05-21 | 物聯記憶體科技股份有限公司 | Non-volatile memory and manufacturing method thereof |
CN111192877B (en) * | 2018-11-14 | 2021-02-19 | 合肥晶合集成电路股份有限公司 | Nonvolatile memory and manufacturing method thereof |
US10797142B2 (en) | 2018-12-03 | 2020-10-06 | Silicon Storage Technology, Inc. | FinFET-based split gate non-volatile flash memory with extended source line FinFET, and method of fabrication |
US10998325B2 (en) | 2018-12-03 | 2021-05-04 | Silicon Storage Technology, Inc. | Memory cell with floating gate, coupling gate and erase gate, and method of making same |
US10937794B2 (en) | 2018-12-03 | 2021-03-02 | Silicon Storage Technology, Inc. | Split gate non-volatile memory cells with FinFET structure and HKMG memory and logic gates, and method of making same |
US10902921B2 (en) * | 2018-12-21 | 2021-01-26 | Texas Instruments Incorporated | Flash memory bitcell erase with source bias voltage |
US11409352B2 (en) | 2019-01-18 | 2022-08-09 | Silicon Storage Technology, Inc. | Power management for an analog neural memory in a deep learning artificial neural network |
US11023559B2 (en) | 2019-01-25 | 2021-06-01 | Microsemi Soc Corp. | Apparatus and method for combining analog neural net with FPGA routing in a monolithic integrated circuit |
US10720217B1 (en) | 2019-01-29 | 2020-07-21 | Silicon Storage Technology, Inc. | Memory device and method for varying program state separation based upon frequency of use |
US11107827B2 (en) | 2019-02-28 | 2021-08-31 | International Business Machines Corporation | Integration of split gate metal-oxide-nitride-oxide-semiconductor memory with vertical FET |
US11423979B2 (en) | 2019-04-29 | 2022-08-23 | Silicon Storage Technology, Inc. | Decoding system and physical layout for analog neural memory in deep learning artificial neural network |
CN112185815A (en) | 2019-07-04 | 2021-01-05 | 硅存储技术公司 | Method of forming split gate flash memory cells with spacer defined floating gates and discretely formed polysilicon gates |
US10991433B2 (en) | 2019-09-03 | 2021-04-27 | Silicon Storage Technology, Inc. | Method of improving read current stability in analog non-volatile memory by limiting time gap between erase and program |
US11315636B2 (en) * | 2019-10-14 | 2022-04-26 | Silicon Storage Technology, Inc. | Four gate, split-gate flash memory array with byte erase operation |
CN110797344B (en) * | 2019-11-08 | 2022-10-21 | 武汉新芯集成电路制造有限公司 | Method for manufacturing semiconductor device |
US20210193671A1 (en) | 2019-12-20 | 2021-06-24 | Silicon Storage Technology, Inc. | Method Of Forming A Device With Split Gate Non-volatile Memory Cells, HV Devices Having Planar Channel Regions And FINFET Logic Devices |
CN113299333A (en) | 2020-02-21 | 2021-08-24 | 硅存储技术股份有限公司 | Wear leveling in an EEPROM emulator formed from flash memory cells |
US11114451B1 (en) | 2020-02-27 | 2021-09-07 | Silicon Storage Technology, Inc. | Method of forming a device with FinFET split gate non-volatile memory cells and FinFET logic devices |
US11362100B2 (en) | 2020-03-24 | 2022-06-14 | Silicon Storage Technology, Inc. | FinFET split gate non-volatile memory cells with enhanced floating gate to floating gate capacitive coupling |
KR20220163463A (en) | 2020-06-23 | 2022-12-09 | 실리콘 스토리지 테크놀로지 인크 | Method for manufacturing memory cells, high voltage devices and logic devices on substrates |
CN113838853A (en) | 2020-06-23 | 2021-12-24 | 硅存储技术股份有限公司 | Method of fabricating memory cells, high voltage devices and logic devices on a substrate |
US11309042B2 (en) | 2020-06-29 | 2022-04-19 | Silicon Storage Technology, Inc. | Method of improving read current stability in analog non-volatile memory by program adjustment for memory cells exhibiting random telegraph noise |
CN114078864A (en) | 2020-08-17 | 2022-02-22 | 硅存储技术股份有限公司 | Method of fabricating memory cells, high voltage devices and logic devices on a substrate by silicide on conductive blocks |
KR102559812B1 (en) | 2020-08-17 | 2023-07-25 | 실리콘 스토리지 테크놀로지 인크 | Manufacturing method of memory cell, high voltage device and logic device on substrate having silicide in conductive block |
CN114256251A (en) | 2020-09-21 | 2022-03-29 | 硅存储技术股份有限公司 | Method of forming an apparatus having a memory cell, a high voltage device and a logic device |
WO2022060402A1 (en) | 2020-09-21 | 2022-03-24 | Silicon Storage Technology, Inc. | Method of forming a device with planar split gate non-volatile memory cells, high voltage devices and finfet logic devices |
US11387241B2 (en) | 2020-09-22 | 2022-07-12 | United Microelectronics Corporation | Method for fabricating flash memory |
CN114446972A (en) | 2020-10-30 | 2022-05-06 | 硅存储技术股份有限公司 | Split gate non-volatile memory cell, HV and logic device with finfet structure and method of fabricating the same |
WO2022146465A1 (en) | 2020-12-29 | 2022-07-07 | Silicon Storage Technology, Inc. | Improved architectures for storing and retrieving system data in a non-volatile memory system |
US11538532B2 (en) | 2020-12-29 | 2022-12-27 | Silicon Storage Technology, Inc. | Architectures for storing and retrieving system data in a non-volatile memory system |
US11545583B2 (en) | 2021-02-05 | 2023-01-03 | Semiconductor Components Industries, Llc | Process of forming an electronic device including a non-volatile memory cell |
CN115000072A (en) | 2021-03-01 | 2022-09-02 | 硅存储技术股份有限公司 | Method of forming a semiconductor device having a memory cell, a high voltage device and a logic device on a substrate |
EP4302332A1 (en) | 2021-03-01 | 2024-01-10 | Silicon Storage Technology Inc. | Method of forming a semiconductor device with memory cells, high voltage devices and logic devices on a substrate |
EP4348651A1 (en) | 2021-06-02 | 2024-04-10 | Silicon Storage Technology Inc. | Method of improving read current stability in analog non-volatile memory by post-program tuning for memory cells exhibiting random telegraph noise |
WO2022260692A1 (en) | 2021-06-08 | 2022-12-15 | Silicon Storage Technology, Inc. | Method of reducing random telegraph noise in non-volatile memory by grouping and screening memory cells |
US11769558B2 (en) | 2021-06-08 | 2023-09-26 | Silicon Storage Technology, Inc. | Method of reducing random telegraph noise in non-volatile memory by grouping and screening memory cells |
US11462622B1 (en) | 2021-06-23 | 2022-10-04 | Globalfoundries Singapore Pte. Ltd. | Memory cells and methods of forming a memory cell |
TW202308125A (en) * | 2021-08-02 | 2023-02-16 | 聯華電子股份有限公司 | Semiconductor memory device and fabrication method thereof |
WO2023091172A1 (en) | 2021-11-22 | 2023-05-25 | Silicon Storage Technology, Inc. | Address fault detection in a memory system |
WO2023154078A1 (en) | 2022-02-14 | 2023-08-17 | Silicon Storage Technology, Inc. | Method of forming a semiconductor device with memory cells, high voltage devices and logic devices on a substrate using a dummy area |
WO2023172279A1 (en) | 2022-03-08 | 2023-09-14 | Silicon Storage Technology, Inc. | Method of forming a device with planar split gate non-volatile memory cells, planar hv devices, and finfet logic devices on a substrate |
US11968829B2 (en) | 2022-03-10 | 2024-04-23 | Silicon Storage Technology, Inc. | Method of forming memory cells, high voltage devices and logic devices on a semiconductor substrate |
WO2023172280A1 (en) | 2022-03-10 | 2023-09-14 | Silicon Storage Technology, Inc. | Method of forming memory cells, high voltage devices and logic devices on a semiconductor substrate |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5268319A (en) * | 1988-06-08 | 1993-12-07 | Eliyahou Harari | Highly compact EPROM and flash EEPROM devices |
US20040065917A1 (en) * | 2002-10-07 | 2004-04-08 | Der-Tsyr Fan | Flash memory cells with separated self-aligned select and erase gates, and process of fabrication |
US20050023591A1 (en) * | 2003-07-30 | 2005-02-03 | Yi Ding | Nonvolatile memory cell with multiple floating gates formed after the select gate and having upward protrusions |
US20060203552A1 (en) * | 2004-03-17 | 2006-09-14 | Actrans System Incorporation, Usa | Process of Fabricating Flash Memory with Enhanced Program and Erase Coupling |
US20070093024A1 (en) * | 2005-10-26 | 2007-04-26 | Promos Technologies Inc. | Split gate flash memory cell and fabrication method thereof |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0640588B2 (en) * | 1987-03-13 | 1994-05-25 | 株式会社東芝 | Semiconductor memory device |
JPH01143361A (en) * | 1987-11-30 | 1989-06-05 | Sony Corp | Nonvolatile memory |
US5095344A (en) * | 1988-06-08 | 1992-03-10 | Eliyahou Harari | Highly compact eprom and flash eeprom devices |
US5242848A (en) * | 1990-01-22 | 1993-09-07 | Silicon Storage Technology, Inc. | Self-aligned method of making a split gate single transistor non-volatile electrically alterable semiconductor memory device |
JP3854629B2 (en) * | 1991-04-09 | 2006-12-06 | シリコン・ストーリッジ・テクノロジー・インク | Memory array device, memory cell device and programming method thereof |
US5579259A (en) * | 1995-05-31 | 1996-11-26 | Sandisk Corporation | Low voltage erase of a flash EEPROM system having a common erase electrode for two individually erasable sectors |
JP3241316B2 (en) * | 1998-01-07 | 2001-12-25 | 日本電気株式会社 | Manufacturing method of flash memory |
JP4222675B2 (en) * | 1999-03-29 | 2009-02-12 | 三洋電機株式会社 | Nonvolatile semiconductor memory device |
US20040256657A1 (en) * | 2003-06-20 | 2004-12-23 | Chih-Wei Hung | [flash memory cell structure and method of manufacturing and operating the memory cell] |
US6992929B2 (en) * | 2004-03-17 | 2006-01-31 | Actrans System Incorporation, Usa | Self-aligned split-gate NAND flash memory and fabrication process |
FR2871940B1 (en) * | 2004-06-18 | 2007-06-15 | St Microelectronics Rousset | TRANSISTOR MOS WITH FLOATING GRID, WITH DOUBLE CONTROL GRID |
JP2006108668A (en) * | 2004-09-30 | 2006-04-20 | Samsung Electronics Co Ltd | Nonvolatile memory device and manufacturing method therefor |
US7700473B2 (en) * | 2007-04-09 | 2010-04-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gated semiconductor device and method of fabricating same |
-
2007
- 2007-08-06 US US11/834,574 patent/US20090039410A1/en not_active Abandoned
-
2008
- 2008-07-18 TW TW097127416A patent/TWI393263B/en active
- 2008-08-01 KR KR1020080075628A patent/KR20090014967A/en not_active Application Discontinuation
- 2008-08-05 CN CN2011102379841A patent/CN102403274A/en active Pending
- 2008-08-05 CN CN2008101352676A patent/CN101364614B/en active Active
- 2008-08-05 CN CN2011104494755A patent/CN102522409A/en active Pending
- 2008-08-06 JP JP2008225276A patent/JP5361292B2/en active Active
-
2009
- 2009-11-13 US US12/618,632 patent/US7868375B2/en active Active
-
2010
- 2010-12-06 US US12/961,193 patent/US7927994B1/en active Active
-
2011
- 2011-02-08 US US13/023,443 patent/US20110127599A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5268319A (en) * | 1988-06-08 | 1993-12-07 | Eliyahou Harari | Highly compact EPROM and flash EEPROM devices |
US20040065917A1 (en) * | 2002-10-07 | 2004-04-08 | Der-Tsyr Fan | Flash memory cells with separated self-aligned select and erase gates, and process of fabrication |
US20050023591A1 (en) * | 2003-07-30 | 2005-02-03 | Yi Ding | Nonvolatile memory cell with multiple floating gates formed after the select gate and having upward protrusions |
US20060203552A1 (en) * | 2004-03-17 | 2006-09-14 | Actrans System Incorporation, Usa | Process of Fabricating Flash Memory with Enhanced Program and Erase Coupling |
US20070093024A1 (en) * | 2005-10-26 | 2007-04-26 | Promos Technologies Inc. | Split gate flash memory cell and fabrication method thereof |
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2888760A4 (en) * | 2012-08-23 | 2016-04-13 | Silicon Storage Tech Inc | Split-gate memory cell with depletion-mode floating gate channel, and method of making same |
US9466732B2 (en) * | 2012-08-23 | 2016-10-11 | Silicon Storage Technology, Inc. | Split-gate memory cell with depletion-mode floating gate channel, and method of making same |
US20140054667A1 (en) * | 2012-08-23 | 2014-02-27 | Silicon Storage Technology, Inc. | Split-Gate Memory Cell With Depletion-Mode Floating Gate Channel, And Method Of Making Same |
KR101823212B1 (en) * | 2012-08-23 | 2018-01-29 | 실리콘 스토리지 테크놀로지 인크 | Split-gate memory cell with depletion-mode floating gate channel, and method of making same |
US8785307B2 (en) | 2012-08-23 | 2014-07-22 | Silicon Storage Technology, Inc. | Method of forming a memory cell by reducing diffusion of dopants under a gate |
WO2014031285A1 (en) * | 2012-08-23 | 2014-02-27 | Silicon Storage Technology, Inc. | Split-gate memory cell with depletion-mode floating gate channel, and method of making same |
US9018690B2 (en) * | 2012-09-28 | 2015-04-28 | Silicon Storage Technology, Inc. | Split-gate memory cell with substrate stressor region, and method of making same |
CN104685570A (en) * | 2012-09-28 | 2015-06-03 | 硅存储技术公司 | Split-gate memory cell with substrate stressor region, and method of making same |
US20140091382A1 (en) * | 2012-09-28 | 2014-04-03 | Silicon Storage Technology, Inc. | Split-Gate Memory Cell With Substrate Stressor Region, And Method Of Making Same |
EP2901455A4 (en) * | 2012-09-28 | 2016-05-25 | Silicon Storage Tech Inc | Split-gate memory cell with substrate stressor region, and method of making same |
US9306039B2 (en) | 2012-09-28 | 2016-04-05 | Silicon Storage Technology, Inc. | Method of making split-gate memory cell with substrate stressor region |
WO2014051855A1 (en) * | 2012-09-28 | 2014-04-03 | Silicon Storage Technology, Inc. | Split-gate memory cell with substrate stressor region, and method of making same |
TWI676272B (en) * | 2016-11-29 | 2019-11-01 | 台灣積體電路製造股份有限公司 | Semiconductor device and manufacturing method thereof |
US10510544B2 (en) | 2016-11-29 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Non-volatile memory semiconductor device and manufacturing method thereof |
US11133188B2 (en) | 2016-11-29 | 2021-09-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Non-volatile memory semiconductor device with electrostatic discharge protection, planarization layers, and manufacturing method thereof |
CN107221350A (en) * | 2017-05-15 | 2017-09-29 | 上海华虹宏力半导体制造有限公司 | Accumulator system, memory array and its reading and operation scheme for programming |
US11721731B2 (en) | 2021-08-03 | 2023-08-08 | Globalfoundries Singapore Pte. Ltd. | Nonvolatile memory having multiple narrow tips at floating gate |
Also Published As
Publication number | Publication date |
---|---|
JP5361292B2 (en) | 2013-12-04 |
CN102522409A (en) | 2012-06-27 |
CN101364614A (en) | 2009-02-11 |
CN101364614B (en) | 2012-02-08 |
JP2009044164A (en) | 2009-02-26 |
TWI393263B (en) | 2013-04-11 |
US7868375B2 (en) | 2011-01-11 |
US7927994B1 (en) | 2011-04-19 |
CN102403274A (en) | 2012-04-04 |
KR20090014967A (en) | 2009-02-11 |
US20110076816A1 (en) | 2011-03-31 |
US20100054043A1 (en) | 2010-03-04 |
US20090039410A1 (en) | 2009-02-12 |
TW200917495A (en) | 2009-04-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7868375B2 (en) | Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing | |
US6894339B2 (en) | Flash memory with trench select gate and fabrication process | |
US6885586B2 (en) | Self-aligned split-gate NAND flash memory and fabrication process | |
US7407857B2 (en) | Method of making a scalable flash EEPROM memory cell with notched floating gate and graded source region | |
US6764905B2 (en) | Method of manufacturing a scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate | |
US6747310B2 (en) | Flash memory cells with separated self-aligned select and erase gates, and process of fabrication | |
US7208794B2 (en) | High-density NROM-FINFET | |
US9123822B2 (en) | Split gate non-volatile flash memory cell having a silicon-metal floating gate and method of making same | |
JP6094934B2 (en) | Divided gate memory cell with depletion mode floating gate channel and method for manufacturing the same | |
US6875660B2 (en) | Method of manufacturing high coupling ratio flash memory having sidewall spacer floating gate electrode | |
US5643812A (en) | Method of making EEPROM flash memory cell with erase gate | |
US7439572B2 (en) | Stacked gate memory cell with erase to gate, array, and method of manufacturing | |
US20040071025A1 (en) | Flash memory device and fabricating method therefor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |