TWI708373B - Flash memory structure - Google Patents

Abstract

The present invention provides a flash memory structure, comprising: a substrate; a select gate, formed on the substrate; a control gate, formed on the substrate, adjacent and separated from the select gate, having a top surface and a bottom surface; a oxide bump, formed on the substrate in-between the select gate and the control gate, wherein the top surface of the control gate vertically projects to the bottom surface to define a main portion and a protruding portion of the control gate, the protruding portion is on a side of the main portion close to the oxide bump, a first distance is defined between the main portion and the oxide bump, a second distance is defined between the oxide bump and the select gate, and a ratio of the first distance to the second distance is in a range of 0.3-1.

Description

Flash memory structure

The present invention relates to a flash memory structure, in particular to a flash memory structure that increases the effective channel length.

In recent years, the development of data rewritable non-volatile memory has been extensive. In the technical field of this kind of non-volatile memory, with market demand, there has been continuous development towards miniaturization of memory cells and increasing memory capacity, with ONO (oxide/nitride/oxide The SONOS (silicon/oxide/nitride/oxide/silicon) type flash memory of the film has also been developed.

Flash memory is a non-volatile memory device that can store data with low power consumption. It can be deleted or written many times during operation. In addition, compared to other memory devices, flash memory has lower read latency, better dynamic shock resistance, significant speed advantages when writing large amounts of data, and a better cost structure. It has become the most widely adopted technology for non-volatile solid-state storage, such as notebook computers, digital walkmans, digital cameras, mobile phones, game consoles and other related products.

The SONOS flash memory described above stores charges in a silicon nitride film (called a trap layer) with a control gate structure, and the silicon nitride film is sandwiched between the silicon oxide film. between. In the current conventional process technology, a patterned pad oxide layer is first formed on the substrate, then an ONO film and a polysilicon layer are sequentially formed, and finally the gate is defined by an etching step. However, in this manufacturing method, because the pad oxide layer overlaps the ONO film, part of the pad oxide layer remains during the gate definition step. Generally speaking, to solve the problem of the residual oxide layer of the pad, it is necessary to modify the existing process steps. For the process factory, relatively high costs must be invested in R&D and testing, and this often leads to an increase in process costs. However, under the same current manufacturing process steps, the prior art cannot further improve the performance of the flash memory.

Based on the above-mentioned problems, the present invention provides a flash memory structure that can be applied to the existing process steps and does not increase the additional process cost to improve and enhance the performance of the flash memory.

The present invention provides a flash memory structure, comprising: a substrate; a selective gate structure formed on the substrate; a control gate structure, which is formed on the substrate adjacently and separately from the selective gate structure, and has a The upper surface and the lower surface; oxide bumps, formed on the substrate, between the control gate structure and the select gate structure, wherein the control gate structure, the select gate structure and the oxide bump are separated from each other, and the control gate The upper surface of the pole structure is vertically projected to the lower surface to define a main body and a protrusion. The protrusion is located on a side of the main body close to the oxide bump, and there is a first distance between the oxide bump and the main body. There is a second distance between the oxide bump and the selection gate structure, and the ratio of the first distance to the second distance is between 0.3-1.

In a preferred embodiment of the present invention, the first distance is less than 40 nm.

In a preferred embodiment of the present invention, the first distance is greater than 20 nm.

In a preferred embodiment of the present invention, the protruding portion extends in the direction of the oxide bump, and the length of the protruding portion is between 3-7 nm.

In a preferred embodiment of the present invention, the length of the protrusion is 5 nm.

In a preferred embodiment of the present invention, the area of the upper surface is smaller than the area of the lower surface.

In a preferred embodiment of the present invention, there is a third distance between the control gate structure and the selection gate structure, which is between 120-150 nm.

In a preferred embodiment of the present invention, the third distance is between 120-130 nm.

In a preferred embodiment of the present invention, the width of one of the oxide bumps is between 30-50 nm.

In a preferred embodiment of the present invention, the width is 40 nm.

In a preferred embodiment of the present invention, the thickness of the oxide bump is between 100-150 angstroms.

In a preferred embodiment of the present invention, the thickness of the oxide bump is 110 angstroms.

In a preferred embodiment of the present invention, the control gate structure includes a first oxide layer, a nitride layer, a second oxide layer, and a polysilicon gate layer in sequence from the substrate in a direction away from the substrate.

In a preferred embodiment of the present invention, the selective gate structure includes a gate oxide layer and a polysilicon gate layer in sequence from the substrate in a direction away from the substrate.

Therefore, the flash memory structure provided by the present invention can not only be directly applied to the conventional manufacturing process, but also enable the control gate electrode structure to have a longer effective channel length without increasing the additional process cost and product size. , Thereby achieving the effect of improving the stability and reliability of the flash memory.

1: substrate

2. 2’: Patterned pad oxide layer

T1: opening

3. 3’, 3”: ONO stacking

4.41, 42: oxide layer

5. 5’: Polysilicon layer

6: Control gate structure

7: Select the gate structure

21: oxide bump

31, 31’, 611: bottom oxide layer

32, 32’, 612: Nitride layer

33, 33’, 613: Surface oxide layer

51: Control gate electrode

52: Select gate electrode

61: ONO structure layer

71: gate oxide

621: body part

622: protruding part

D1, D2, D3, D4, D21: distance

H21: height

S51b, S51t, S61b: surface

PR1, PR2: patterned photoresist layer

PR21, PR22: photoresist

R1, R2: projection area

In order to make the above and other objects, features and advantages of the present invention more comprehensible, several preferred embodiments are listed below in conjunction with the accompanying drawings, which are described in detail as follows: Figures 1-9 are based on the present invention Draw a cross-sectional structure diagram of the flash memory structure in different steps of the process.

The present invention provides a flash memory structure. In order to make the above and other objects, features and advantages of the present invention more comprehensible, the following embodiments are combined with the accompanying drawings to reveal the process steps related to the embodiments of the present invention. In order to make the structure and function of the present invention easier to understand.

As shown in FIG. 1, a patterned pad oxide layer 2 is formed on a substrate 1 (for example, a silicon substrate), wherein the pad oxide layer 2 opening T1 is used to define the area of the subsequent control gate structure. Next, as shown in FIG. 2, an ONO stack 3 is formed on the substrate 1 to conformally cover the substrate 1 and the patterned pad oxide layer 2, wherein the ONO stack 3 includes a bottom oxide layer 31 and a nitride layer formed in sequence 32 (for example, silicon nitride) and a surface oxide layer 33. The above-mentioned pad oxide layer 2, bottom oxide layer 31, nitride layer 32, and surface oxide layer 33 are formed using conventional techniques, such as deposition (CVD), thermal oxidation, etc., and the thickness of the formation can also be customized. Make adjustments, so I won’t repeat them here.

Next, as shown in FIGS. 3-4, a patterned photoresist layer PR1 is formed on the ONO stack 3 to cover the opening T1 and a portion of the patterned pad oxide layer 2 adjacent to the opening T1. Then, a photolithography process is performed on the ONO stack 3 using the patterned photoresist layer PR1 as a mask to remove the part of the ONO stack 3 exposed to the patterned photoresist layer PR1, and then the patterned photoresist layer PR1 is removed. After removing the exposed part of the ONO stack 3 and the patterned photoresist layer PR1, it is possible to remove part of the patterned pad oxide layer 2 exposed to the patterned photoresist layer PR1 at the same time, as shown in FIG. 4 , Forming a patterned ONO stack 3'and a patterned pad oxide layer 2'with a thin exposed part, wherein the patterned ONO structure layer stack 3'sequentially includes patterned under-oxidation from the surface of the substrate 1 to a direction away from the substrate 1 Layer 31', patterned nitride layer 32', and patterned surface oxide layer 33'.

Next, as shown in FIGS. 5-6, the patterned pad oxide layer 2'exposed to the ONO stack 3'is removed (ie, the thinned portion of the patterned pad oxide layer 2'is removed) to form oxide bumps 21 , And adjacent to the opening T1. The method can choose an etchant with a large etching ratio of oxide to nitride, and use dry or Wet etching is performed, and the above etching method will also remove the patterned surface oxide layer 33' in the patterned ONO stack 3'at the same time, thus forming the structure shown in FIG. 5, and part of the patterned ONO stack 3'( That is, the patterned nitride layer 32 and the patterned surface oxide layer 33 ′) cover the opening T1 and the oxide bump 21 on the substrate 1. Then the oxide layer 4 is formed, including the first partial oxide layer 41 covering the patterned nitride layer 32', and the second partial oxide layer 42 covering the exposed portion of the substrate 1, wherein the first partial oxide layer 41, the patterned nitrogen The oxide layer 32' and the patterned surface oxide layer 33' together form an ONO stack 3". The width D21 of the oxide bump 21 is between 30-50nm and the height H21 is between 100-150 angstroms, and is based on In one embodiment of the present invention, the length D21 of the oxide bump 21 is about 40 nm and the height H21 is about 110 angstroms.

Next, as shown in FIGS. 7-8, a patterned polysilicon layer 5'is formed, including a control gate electrode 51 formed on the ONO structure layer 3" in the opening T1, and a selective gate electrode formed on the second partial oxide layer 42 52. The control gate electrode 51 has an upper surface S51t and a lower surface S51b, wherein the area of the upper surface S51t is smaller than the area of the lower surface S51b. The patterned polysilicon layer 5'can be formed by depositing a polysilicon layer 5 to cover the entire substrate 1 is stacked with ONO 3", a planarization process (such as chemical mechanical polishing CMP) is selectively performed, and then a photolithography process (such as anisotropic dry etching or wet etching) is performed to pattern the polysilicon layer 5. As shown in FIG. 7, the patterned photoresist layer PR2 includes photoresists PR21 and PR22 formed on the polysilicon layer 5. The photoresist PR21 is located above the ONO stack 3" in the opening T1, and the photoresist PR22 is located above the first partial oxide layer 42. And the shortest distance D3 between the photoresist PR21 and PR22 is between 120-150nm, preferably between 120-130nm, and is used to define the control gate electrode 51 and the selection gate electrode 52. The photoresist PR21 is projected vertically to the base. The surface of the material 1 defines the projection area R1, the shortest distance D1 from the oxide bump 21 is less than 40nm and greater than 20nm, and the photoresist PR22 is vertically projected onto the surface of the substrate 1 to define the projection area R2, the projection area R2 and the oxide bump There is the shortest distance D2 between 21, where the ratio of distance D1 to distance D2 is between 0.3 and 1. Ideally, the formed control gate electrode 51 should be consistent with the coverage of the photoresist PR21 The rectangular parallelepiped (ie, the polysilicon layer 5 covered by the vertical projection of the photoresist PR21), but because the oxide bump 21 is adjacent to the part of the polysilicon layer 5 under the photoresist PR21, the etching is close to the oxide bump under the photoresist PR21 The etching effect of the polysilicon layer 5 on the side 21 is poor, so the structure shown in FIG. 8 is produced. The control gate electrode 51 is close to the part of the oxide bump 21 near the surface of the substrate 1 and protrudes and extends toward the oxide. Bump 21.

Then, as shown in FIG. 9, using the control gate electrode 51 and the selection gate electrode 52 as a mask, the exposed part of the ONO stack 3" and the first part of the oxide layer 41 are removed to form the control gate structure 6 and the selection gate structure 7 On the substrate 1, the selective gate structure 7 and the control gate structure 6 are adjacent to and separated from each other. The control gate structure 6 includes a bottom oxide layer 611 and a nitride layer on the surface of the substrate 1 in a direction away from the substrate 1. The layer 612, the surface oxide layer 613 and the control gate electrode 51, wherein the bottom oxide layer 611, the nitride layer 612, and the surface oxide layer 613 together constitute the ONO structure layer 61; and the selective gate structure 7 is on the surface of the substrate 1 away from the substrate The direction of 1 includes gate oxide layer 71 and select gate electrode 52. Then, an interlayer dielectric layer is formed to cover the entire substrate 1, control gate structure 6 and select gate structure 7, and then the control gate structure 6 and The two sides of the gate structure 7 are selected to form contact plugs and the like to complete the flash memory structure.

And according to different embodiments, the doping process of the shallow doped region and the source/drain electrode can be performed before or after the patterned ONO stack 3". For example, in an embodiment of the present invention, after the patterned polysilicon layer 5'is formed Before performing the patterned ONO stack 3", perform an LDD (lightly doped drain) process to form a lightly doped region (or source/drain extension region), and then perform source/drain after the ONO structure layer 61' is formed Doping process; In another embodiment of the present invention, the shallow doping region and the source/drain doping process are all performed after the ONO structure layer 61' is formed. Since this part is the same as the conventional one, it is not additionally shown in the drawings and will not be repeated.

Due to the relative positions of the components during the above-mentioned process of the present invention, and the existing limitations of the etching process, the control gate structure 6 cannot form a completely vertical side close to the side of the oxide bump 2 The wall can achieve the effect of increasing the effective channel length without changing the process cost. As shown in FIG. 9, the upper surface of the control gate structure 6 is the upper surface S51t, and the lower surface S61b is the contact surface between the bottom oxide layer 611 and the substrate 1. The area of the upper surface S51t is smaller than the area of the lower surface S61b, and The vertical projection of the upper surface S51t to the lower surface S61b defines the main body 621, and the part outside the main body 621 is defined as the protrusion 622. The protrusion 622 is adjacent to the main body 621, and the protrusion 622 is located in the main body 621. Close to one side of the oxide bump 21, the protrusion 622 extends in the direction of the oxide bump 21, and has a protrusion length D4 between 3-7 nm; in an embodiment of the present invention, The protrusion length D4 is 5 nm. In addition, since the upper surface S51t of the control gate structure 6 is directly below the photoresist PR21, the body portion 621 defined by the vertical projection of the upper surface S51t is the projection area R1, and the area between the oxide bump 21 and the body portion 621 The shortest distance is D1. Similarly, the shortest distance between the selected gate structure 7 and the oxide bump 21 is D2, and the shortest horizontal distance between the control gate structure 6 and the selected gate structure 7 is D3. The length range and ratio range of D1, D2, and D3 are the same as those described above, and will not be repeated here.

According to an embodiment of the present invention, the thickness of the control gate electrode 51 is 800 angstroms, and the thickness of the bottom oxide layer 611, the nitride layer 612, and the surface oxide layer 613 in the ONO structure layer 61 are 39 angstroms, 73 angstroms, and 18 angstroms, respectively And the oxide bump 21 has a thickness of 110 angstroms and a width of 40 nm.

In order to avoid errors caused by the yellow light process, the patterned photoresist layer (PR1) will inevitably cover part of the patterned pad oxide layer (2) during the process to ensure that the control gate electrode formed later can completely cover the ONO stack (3 ), so the oxide bumps (21) generated during the manufacturing process cannot be avoided. The above parameters and distance ranges provided by the present invention can ensure that there is a complete ONO structure layer under the protrusions of the control gate structure, and due to the existence of the protrusions, the control gate structure can have a longer effective channel length. At the same time, it is separated from the oxide bump. Therefore, according to the above method of the present invention, the existence of oxide bumps, the definition of the horizontal distance between the photoresist of the gate electrode and the oxide bumps, the etching defects caused by the environment, and the interaction of the three can be directly used. Applied to the learning system Under the premise of the process, the parameter adjustment is used to enable the control gate electrode structure to have a longer effective channel length, thereby achieving the effect of improving the stability and reliability of the flash memory.

Therefore, the manufacturing process of the flash memory structure provided by the present invention can be directly applied to the conventional technology, and the stability and reliability of the flash memory can be improved without increasing the manufacturing cost and product size. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

1: substrate

6: Control gate structure

7: Select the gate structure

21: oxide bump

611, 613: bottom oxide layer

612: Nitriding layer

51: Control gate electrode

52: Select gate electrode

61: ONO structure layer

71: gate oxide

621: body part

622: protruding part

D4: distance

S51t, S61b: Surface

Claims (14)

A flash memory structure includes: a substrate; a selective gate structure formed on the substrate; a control gate structure formed on the substrate adjacent to and separated from the selective gate structure, It has an upper surface and a lower surface; and an oxide bump formed on the substrate, between the control gate structure and the selection gate structure, wherein the control gate structure, the selection gate structure and the The oxide bumps are separated from each other, wherein the upper surface is vertically projected to the lower surface to define a body portion and a protruding portion. The protruding portion is located on a side of the body portion close to the oxide bump, and the oxide bump There is a first distance between the object bump and the body portion, and there is a second distance between the oxide bump and the selective gate structure, and the ratio of the first distance to the second distance is 0.3-1 between. The flash memory structure according to claim 1, wherein the first distance is less than 40 nm. The flash memory structure according to claim 2, wherein the first distance is greater than 20 nm. The flash memory structure according to claim 1, wherein the protrusion extends in the direction of the oxide bump, and has a protrusion length between 3-7 nm. The flash memory structure of claim 4, wherein the length of the protrusion is 5 nm. The flash memory structure according to claim 1, wherein the area of the upper surface is smaller than the area of the lower surface. The flash memory structure according to claim 1, wherein there is a third distance between the control gate structure and the selection gate structure, which is between 120-150 nm. The flash memory structure according to claim 7, wherein the third distance is between 120-130 nm. The flash memory structure of claim 1, wherein a width of the oxide bump is between 30-50 nm. The flash memory structure according to claim 9, wherein the width is 40 nm. The flash memory structure according to claim 1, wherein one of the oxide bumps has a thickness between 100-150 angstroms. The flash memory structure according to claim 11, wherein the thickness is 110 angstroms. The flash memory structure according to claim 1, wherein the control gate structure sequentially includes a first oxide layer, a nitride layer, and a second oxide layer on the substrate in a direction away from the substrate And a polysilicon gate layer. The flash memory structure according to claim 1, wherein the selective gate structure includes a gate oxide layer and a polysilicon gate layer in sequence in a direction away from the substrate from the substrate.

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