TWI517302B - Method of fabricating semiconductor device - Google Patents

Description

Semiconductor device manufacturing method

The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device having three gates.

Flash memory is a non-volatile memory that retains the information stored in memory in the absence of an external power supply. In recent years, flash memory has been widely used in mobile phones, digital cameras, and video players because of its advantages of rewritable writing and electrical erasing. An electronic product such as a personal digital assistant (PDA) or a system on a chip (SOC) under development.

Please refer to FIG. 1 , which illustrates a cross-sectional view of a conventional flash memory unit. As shown in FIG. 1, the flash memory cell 10 includes a semiconductor substrate 12, a gate stack 14 disposed on the semiconductor substrate 12, and a select gate 20 disposed on the side of the gate stack 14. The gate stack 14 includes a floating gate 16 and a control gate 18. The floating gate 16, the control gate 18 and the selection gate 20 are generally composed of polysilicon, and dielectric layers 22/24/26 such as oxide layers may be disposed between the gates to be electrically insulated from each other. The flash memory cell 10 further includes a source doping region 28 and a drain doping region 30 disposed in the semiconductor substrate 12 on both sides of the gate stack 14, and a channel region 32 defined in the source doping region 28 and The semiconductor substrate 12 is between the drain regions 30. In addition, the dielectric layer 22 between the floating gate 16 and the semiconductor substrate 12 is a tunneling oxide layer through which the hot electrons tunneling into and out of the floating layer. The gate 16 is configured to access the data access of the flash memory unit 10.

In the process of the conventional flash memory cell 10, a gate layer (not shown) having two sidewall shapes is formed on both sides of the gate stack 14, and the gate on the side of the gate stack 14 is covered by the photomask. a pole layer, such as a select gate 20 on the drain doped region 30, in conjunction with a reactive-ion-etching (RIE) process to remove the gate layer on the other side of the gate stack 14. For example, a gate layer (not shown) on the source doping region 28 completes the structure of the flash memory cell 10. However, as the size of the flash memory cell 10 shrinks, the sidewalls of the common gate stack 14 after the reactive ion etching process, such as the sidewall S of the gate stack 14 on the source doped region 28, remain The residual polycrystalline germanium is also known as the stringer R. This residue R affects the electrical performance of the flash memory cell, causing leakage current, thereby reducing the data retention capability of the flash memory. Therefore, how to avoid the formation of the residue to improve the electrical performance of the flash memory cell is a problem that the related art desires to improve.

One of the objects of the present invention is to provide a method of fabricating a semiconductor device having three gates to avoid formation of a residue.

A preferred embodiment of the present invention provides a method of fabricating a semiconductor device comprising the following steps. First, a two-gate stack is formed on a semiconductor substrate, and then a material layer is formed on the semiconductor substrate, and the material layer covers the two gate stack layers. Then, a portion of the material layer is removed to form a sacrificial layer between the two gate stack layers and a sidewall is formed on opposite sides of the two gate stack layers. Subsequently, a patterned mask layer is formed to cover the two gate stack layers and the sidewalls and expose the sacrificial layer, and the sacrificial layer is removed.

The present invention can form a semiconductor device by forming a sidewall spacer on only one side of the gate stack layer and forming a sacrificial layer between the gate stack layers, so that no redundant between the two gate stack layers is formed. The sidewalls, therefore, there is no need to additionally perform a lithography process for removing the sidewalls between the two gate stack layers, and it is also possible to avoid the formation of a residue on the sidewalls of the gate stack layer due to the mask alignment error. The situation helps to improve the electrical performance of the semiconductor device.

The present invention will be further understood by those of ordinary skill in the art of the present invention. The preferred embodiments of the present invention are set forth in the accompanying drawings.

The present invention provides a method of fabricating a semiconductor device, please refer to Figures 2 through 7. 2 to 7 are schematic views showing a method of fabricating a semiconductor device in accordance with a preferred embodiment of the present invention. As shown in FIG. 2, a two gate stack layer 102/104 is formed on a semiconductor substrate 100. The semiconductor substrate 100 may comprise, for example, a germanium, gallium arsenide, germanium-on-insulator (SOI) layer, an epitaxial layer, germanium. A substrate composed of a layer of germanium or other semiconductor substrate material. Each of the gate stack layers 102/104 includes at least one gate layer and at least one dielectric layer. In this embodiment, each of the gate stack layers 102/104 includes a first dielectric layer 106, a first gate layer 108, a second dielectric layer 110, and a second gate layer 112. On the semiconductor substrate 100, and in principle, the two gate stack layers 102/104 have the same height and width, but are not limited thereto.

The method of forming the two gate stack layers 102/104 may include the following steps: First, a stacked layer (not shown) is formed on the semiconductor substrate 100, and the stacked layer includes a dielectric layer, a gate layer, a dielectric layer, and a gate. The layers are sequentially disposed on the semiconductor substrate 100. The dielectric layer may be composed of a single layer or a plurality of layers of insulating material, including tantalum oxide, oxynitride or a high-k dielectric layer having a dielectric constant greater than four. The gate layer may be composed of a conductive material, including polysilicon, metal halide or a metal material having a specific work function. In this embodiment, the dielectric layer is composed of a tantalum oxide formed by a thermal oxidation process or a chemical vapor deposition (CVD) or atomic layer deposition (ALD) deposition process. The gate layer is composed of polycrystalline germanium formed by a low pressure chemical vapor deposition (LPCVD) process, but is not limited thereto. Next, a patterned photoresist layer (not shown) is formed over the stacked layers, and an etching process step is performed to remove portions of the stacked layers to form two gate stack layers 102/104 having the same width. The etching process includes performing an anisotropic dry etching process by patterning the photoresist layer as a mask, removing a portion of the dielectric layer and a portion of the gate layer under the patterned photoresist layer to form a first dielectric layer. 106. The first gate layer 108, the second dielectric layer 110, and the second gate layer 112 are sequentially disposed on the semiconductor base. On the bottom 100. In this embodiment, the first dielectric layer 106 can serve as a tunneling oxide layer, the first gate layer 108 can serve as a floating gate, and the second dielectric layer 110 can serve as a gate dielectric layer. And the second gate layer 112 can serve as a control gate. In addition, in some applications, the first gate layer 108 used as a floating gate may also include materials such as nitrogen ruthenium compounds to trap charges. Subsequently, the patterned photoresist layer is removed.

As shown in FIG. 3, compliantly forms a dielectric layer 114 on the semiconductor substrate 100. The dielectric layer 114 may be composed of a single or composite insulating material, including tantalum oxide, oxynitride or a dielectric constant greater than 4 high dielectric constant dielectric layer. A dielectric layer 114 is over the two gate stack layers 102/104 to cover and contact the top surfaces of the two gate stack layers 102/104 and the sides of the two gate stack layers 102/104. The method of forming the dielectric layer 114 includes performing a thermal oxidation process, oxidizing the exposed two gate stack layers 102/104 and the surface of the semiconductor substrate, or performing a chemical vapor deposition (CVD) process to form a ruthenium oxide or the like. A dielectric layer 114 of insulating material. Then, a material layer (not shown) is formed on the dielectric layer 114, and a material layer is formed on the semiconductor substrate 100 and covers the two gate stack layers 102/104 and the dielectric layer 114. The material layer may be composed of a conductive material, including polycrystalline germanium, metal germanide or a metal material having a specific work function, for forming a third gate layer as a select gate in a subsequent process; It is made of an insulating material and can be applied to other types of semiconductor device processes. In this embodiment, the material layer is a polycrystalline germanium layer formed by a chemical vapor deposition (CVD) process.

Next, a portion of the material layer is removed until a portion of the dielectric layer 114 is exposed, and the exposed portion of the dielectric layer 114 is overlying each of the gate stack layers 102/104. The method of removing a portion of the material layer includes performing an anisotropic etching process such as a reactive-ion-etching (RIE) process, and the remaining material layer forms a layer between the two gate stack layers 102/104. The sacrificial layer 116 is self-aligned to form sidewall spacers 118A/118B on opposite outer sides of the two gate stack layers 102/104, respectively. The side wall sub-118A on the outer side of the gate stack layer 102 and the side wall sub-118B on the outer side of the gate stack layer 104 have the same height H and bottom width W, and further, the curved faces of the side wall sub-118A and the side wall sub-118B have opposite projections from each other. direction.

The fabrication method disclosed in this embodiment can be applied to various corresponding semiconductor devices. Taking a flash memory cell as an example, the material of the material layer is polysilicon. Therefore, each sidewall sub-118A/118B can serve as a third gate. The layers, that is, the select gates, are respectively disposed on one side of each of the gate stack layers 102/104, and the dielectric layer 114 and the sidewall spacers 118B and the gate between the sidewall sub-118A and the gate stack layer 102. The dielectric layer 114 between the pole stack layers 104 can serve as a gate dielectric layer such that the sidewall spacers 118A/118B (third gate layer), the first gate layer 108, and the second gate layer 112 are mutually Inter-electrical insulation. In addition, by appropriately controlling the pitch D of one of the two gate stack layers 102/104 and the parameter of the anisotropic etching process for adjusting the material layer of the removed portion, the material of the opposite inner side of the two gate stack layers 102/104 can be made. The layers cannot be separated into individual sacrificial layers 116 after etching. In the present embodiment, the sacrificial layer 116 is formed to completely overlap the semiconductor substrate 100 between the two gate stack layers 102/104. In addition, a spacing D between the two gate stack layers 102/104 will affect the top surface of the sacrificial layer 116 to a flat surface or have a V shape. Notch.

As shown in FIG. 4, a patterning mask layer 120 is then formed to completely cover the gate stack layer 102/104 and the sidewall spacers 118A/118B and expose the sacrificial layer 116, and the upper portion of the patterned mask layer 120 is non- flat. The material of the patterned mask layer 120 has an etching selectivity ratio with the material of the sacrificial layer 116 and the material of the dielectric layer 114, that is, the patterned mask layer 120 and the sacrificial layer 116 and the dielectric layer 114 are opposed to an etchant. Have different etch rates. For example, a patterned photoresist layer can be directly formed as the patterned mask layer 120 to cover the gate stack layer 102/104 and the sidewall spacers 118A/118B and expose the sacrificial layer 116. In a preferred embodiment of the present invention, tantalum nitride is selected as the material of the patterned mask layer 120 to provide a better etching selectivity and high integration with other component processes, wherein patterning is formed. The method of the mask layer 120 can be exemplified by the following steps: compliant formation of a tantalum nitride mask layer (not shown) on the semiconductor substrate 100, the mask layer covering the semiconductor substrate 100, the gate stack layer 102/104, and a sidewall spacer 118A/118B; then, a patterned photoresist layer (not shown) is formed on the mask layer, and an etching process is performed to remove a portion of the mask layer to form an opening O in the mask layer, and Opening O is used to expose sacrificial layer 116; finally, the patterned photoresist layer is removed. It should be noted that in order to provide a better protection effect of the formed gate stack layer 102/104 and sidewall spacers 118A/118B, one of the openings O preferably has a width substantially less than between the two gate stack layers 102/104. The pitch D, that is, the patterned mask layer 120 preferably partially covers the sacrificial layer 116, and the opening O of the patterned mask layer 120 exposes a portion of the sacrificial layer 116.

As shown in FIG. 5, an etching process is then performed to remove the two gate stack layers 102/104. The sacrificial layer 116 between. In this embodiment, a wet etching process can be performed to remove the sacrificial layer 116. The etching solution of the wet etching process preferably has a selectivity ratio of cerium oxide to nitride, that is, when the sacrificial layer 116 is removed. The patterned mask layer 120 serves as a mask, and the dielectric layer 114 between the gate stack layer 102/104 and the sacrificial layer 116 and the dielectric layer 114 between the semiconductor substrate 100 and the sacrificial layer 116 are partially dielectric layers As an etch stop layer, the etchant is prevented from causing damage to the gate stack layer 102/104, the sidewall spacers 118A/118B, and the semiconductor substrate 100 during the etching process.

Then, as shown in FIG. 6, an etching process is performed to remove the patterned mask layer 120 to form a first gate structure 122 and a second gate structure 124, respectively, and the first gate structure 122 and the second The gate structures 124 are mirror-symmetrical to each other. In this embodiment, a wet etching process can be performed and a heated phosphoric acid solution is used as an etchant to remove the patterned mask layer 120 composed of tantalum nitride. In addition, the first gate structure 122 and the second gate structure 124 each include three gates, that is, a first gate layer 108, a second gate layer 112, and sidewall spacers 118A/118B (third gate layer). Since the sacrificial layer 116 between the two gate stack layers 102/104 has been removed, the sidewall spacers 118A/118B are formed only on the opposite outer side of the gate stack layer 102/104, that is, on the left side of the first gate structure 122. And the right side of the second gate structure 124. Therefore, it is not necessary to perform an etching process to remove excess conductive material between the first gate structure 122 and the second gate structure 124, for example, an electrically conductive sidewall. It is avoided that a stringer is formed on the sidewalls S1/S2 of the first gate structure 122 and the second gate structure 124 due to the mask alignment error, which is advantageous for improving the electrical performance of the semiconductor device.

As shown in FIG. 7 , the first gate structure 122 and the second gate structure 124 are used as a mask, and an ion implantation process is performed on both sides of the first gate structure 122 and the second gate structure 124. A source/drain doping region 126/128/130 is formed in the semiconductor substrate. In this embodiment, the source/drain doping region 128 can serve as the first gate structure 122 and the second gate structure 124. The source region helps to reduce the area occupied by the subsequently formed semiconductor device to enhance the integration of the semiconductor device.

In summary, the present invention forms a sidewall spacer on only one side of the gate stack layer and a stack layer on the second gate layer after the first gate layer and the second gate layer of the two gate stack layers are formed. A semiconductor device in which a sacrificial layer is formed therebetween, so that no excess sidewalls are formed between the two gate stack layers, and therefore, no additional lithography for removing sidewalls between the two gate stack layers is required. The etching process can also avoid the formation of a residue on the sidewall of the gate stack layer due to the mask alignment error, which helps to improve the electrical performance of the semiconductor device.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧Flash memory unit

12,100‧‧‧Semiconductor substrate

14‧‧‧gate stacking

16‧‧‧Floating gate

18‧‧‧Control gate

20‧‧‧Selecting the gate

22,24,26,114‧‧‧ dielectric layer

28‧‧‧ source doped area

30‧‧‧汲Doped area

32‧‧‧Channel area

102,104‧‧‧ gate stack

106‧‧‧First dielectric layer

108‧‧‧First gate layer

110‧‧‧Second dielectric layer

112‧‧‧second gate layer

116‧‧‧ Sacrifice layer

118A, 118B‧‧‧ Sidewall

120‧‧‧ patterned mask layer

122‧‧‧First gate structure

124‧‧‧Second gate structure

126, 128, 130‧‧‧ source/drain doping

D‧‧‧ spacing

H‧‧‧ Height

O‧‧‧ openings

R‧‧‧ Remnant

S, S1, S2‧‧‧ side wall

W‧‧‧ bottom width

FIG. 1 is a cross-sectional view showing a conventional flash memory unit.

2 to 7 are schematic views showing a method of fabricating a semiconductor device in accordance with a preferred embodiment of the present invention.

100. . . Semiconductor substrate

102,104. . . Gate stack

106. . . First dielectric layer

108. . . First gate layer

110. . . Second dielectric layer

112. . . Second gate layer

114. . . Dielectric layer

116. . . Sacrificial layer

118A, 118B. . . Side wall

120. . . Patterned mask layer

D. . . spacing

O. . . Opening

Claims (15)

A method of fabricating a semiconductor device, comprising: forming a two-gate stack on a semiconductor substrate, wherein each of the gate stack layers comprises at least two gate layers; forming a single-layer dielectric layer completely covering and contacting the gate a stacking layer; forming a material layer on the semiconductor substrate and covering the gate stack layer and the dielectric layer; removing a portion of the material layer to form a sacrificial layer between the gate stack layers Forming a sidewall on opposite sides of the gate stack layer; compliant forming a patterned mask layer completely covering the gate stack layer and the sidewalls and exposing the sacrificial layer, wherein the patterned mask layer The upper portion is non-planar; and the sacrificial layer is removed. The method of fabricating a semiconductor device according to claim 1, further comprising: removing the patterned mask layer to form a first gate structure and a second gate structure, respectively, and the first gate structure and the The second gate structures are mirror-symmetrical to each other. The method of fabricating a semiconductor device according to claim 2, further comprising: performing an ion implantation process to form a source in the semiconductor substrate on both sides of the first gate structure and the second gate structure, respectively Bungee doped area. A method of fabricating a semiconductor device according to claim 1, wherein each of the gate stack layers More than at least one dielectric layer is included. A method of fabricating a semiconductor device according to claim 1, wherein the material of the gate layer comprises a conductive material. A method of fabricating a semiconductor device according to claim 5, wherein the material of the gate layer comprises polysilicon. A method of fabricating a semiconductor device according to claim 1, wherein the material of the material layer comprises a conductive material. A method of fabricating a semiconductor device according to claim 1, wherein removing a portion of the material layer comprises performing an anisotropic etching process. A method of fabricating a semiconductor device according to claim 1, wherein after the portion of the material layer is removed, the sacrificial layer is formed to completely overlap the semiconductor substrate between the gate stack layers. The method of fabricating a semiconductor device according to claim 1, wherein after removing a portion of the material layer, the exposed dielectric layer is located above each of the gate stack layers. A method of fabricating a semiconductor device according to claim 1, wherein the patterned mask layer partially covers the sacrificial layer. The method of fabricating a semiconductor device according to claim 1, wherein the step of forming the patterned mask layer comprises: forming a mask layer on the semiconductor substrate; forming a patterned photoresist layer on the mask layer Removing a portion of the mask layer to form an opening in the mask layer, and the opening is for exposing the sacrificial layer; and removing the patterned photoresist layer. A method of fabricating a semiconductor device according to claim 12, wherein one of the openings has a width substantially less than a pitch between the gate stack layers. A method of fabricating a semiconductor device according to claim 1, wherein the material of the patterned mask layer comprises tantalum nitride. A method of fabricating a semiconductor device according to claim 1, wherein removing the sacrificial layer comprises performing a wet etching process.