TWI539581B - Semiconductor device and method of fabricating the same - Google Patents

Description

Semiconductor device and method of fabricating the same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having a three-gate and a method of fabricating the same.

Flash memory is a non-volatile memory that retains the information stored in memory in the absence of an external power supply. In recent years, flash memory has been widely used in mobile phones, digital cameras, and video players because of its advantages of rewritable writing and electrical erasing. An electronic product such as a personal digital assistant (PDA) or a system on a chip (SOC) under development.

Please refer to FIG. 1 , which illustrates a cross-sectional view of a conventional flash memory unit. As shown in FIG. 1, the flash memory cell 10 includes a semiconductor substrate 12, a gate stack 14 disposed on the semiconductor substrate 12, and a select gate 20 disposed on the side of the gate stack 14. The gate stack 14 includes a floating gate 16 and a control gate 18. The floating gate 16, the control gate 18 and the selection gate 20 are generally composed of polysilicon, and dielectric layers 22/24/26 such as oxide layers may be disposed between the gates to be electrically insulated from each other. The flash memory cell 10 further includes a source doping region 28 and a drain doping region 30 disposed on the gate stack A semiconductor substrate 12 on both sides of the 14 and a channel region 32 are defined in the semiconductor substrate 12 between the source doping region 28 and the gate doping region 30. In addition, the dielectric layer 22 between the floating gate 16 and the semiconductor substrate 12 is a tunneling oxide layer through which the hot electrons tunneling into and out of the floating layer. The gate 16 is configured to access the data access of the flash memory unit 10.

In the process of the conventional flash memory cell 10, a gate layer (not shown) having two sidewall shapes is formed on both sides of the gate stack 14, and the gate on the side of the gate stack 14 is covered by the photomask. a pole layer, such as a select gate 20 on the drain doped region 30, in conjunction with a reactive-ion-etching (RIE) process to remove the gate layer on the other side of the gate stack 14. For example, the gate layer on the source doping region 28 completes the structure of the flash memory cell 10. However, as the size of the flash memory cell 10 shrinks, the sidewalls of the common gate stack 14 after the reactive ion etching process, such as the sidewall S of the gate stack 14 on the source doped region 28, remain The residual polycrystalline germanium is also known as the stringer R. This residue R affects the electrical performance of the flash memory cell, causing leakage current, thereby reducing the data retention capability of the flash memory. Therefore, how to avoid the formation of the residue to improve the electrical performance of the flash memory cell is a problem that the related art desires to improve.

It is an object of the present invention to provide a semiconductor device having three gates and a method of fabricating the same to avoid formation of a residue.

A preferred embodiment of the present invention provides a method of fabricating a semiconductor device comprising the following steps. First, a semiconductor substrate is provided, and then a gate stack is formed on the semiconductor substrate, and the gate stack layer further has a cap layer. Then, two first sidewalls are formed around the opposite sidewalls of the gate stack layer. The cap layer is removed and two second sidewalls are formed on a portion of the gate stack layer. Subsequently, a portion of the first sidewall spacer and a gate stack layer not covered by the second sidewall spacer are removed to form a two-gate stack structure.

Another preferred embodiment of the present invention provides a semiconductor device including a semiconductor substrate and at least one gate structure disposed on the semiconductor substrate. The gate structure includes a first gate electrode stacked on the semiconductor substrate from bottom to top, a second gate and an upper surface not parallel to the top cover layer of the semiconductor substrate, and the third gate is located at the first gate a gate and one side of the second gate.

The invention firstly increases the original height of the first side wall by the cover layer, and then uses the size and position of the second side wall formed after the first side wall sub-definition, and then further uses the second side wall as a mask. The three gates in each gate structure are formed by a self-aligned process, which can reduce the cost of the mask of the process and effectively avoid the formation of the residue on the sidewalls of the gate structures.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

The present invention provides a method of fabricating a semiconductor device, please refer to Figures 2 through 7. 2 to 7 are schematic views showing a method of fabricating a semiconductor device in accordance with a preferred embodiment of the present invention. As shown in FIG. 2, a semiconductor substrate 100 is provided, and a gate stack layer 102 is formed on the semiconductor substrate 100. The semiconductor substrate 100 can comprise, for example, a substrate composed of germanium, gallium arsenide, a silicon-on-insulator (SOI) layer, an epitaxial layer, a germanium layer, or other semiconductor substrate material. The gate stack layer 102 includes at least one gate layer and at least one dielectric layer. In this embodiment, the gate stack layer 102 includes a first dielectric layer 104, a first gate layer 106, and a second dielectric layer. The electric layer 108 and a second gate layer 110 are sequentially disposed on the semiconductor substrate 100, and the gate stack layer 102 further has a cap layer 112.

The method of forming the gate stack layer 102 and the cap layer 112 includes the following steps: First, a stacked layer (not shown) is formed on the semiconductor substrate 100, and the stacked layer includes a dielectric layer, a gate layer, a dielectric layer, and a gate. The layer and the capping material layer are sequentially disposed on the semiconductor substrate 100. The dielectric layer may be composed of an insulating material including tantalum oxide, oxynitride or a high-k dielectric layer having a dielectric constant greater than 4. The gate layer may be composed of a conductive material, including polysilicon, metal halide or a metal material having a specific work function. The material of the capping material layer may include an insulating material such as tantalum nitride, hafnium oxide or hafnium oxynitride. In this embodiment, the dielectric layer is a tantalum oxide formed by a thermal oxidation process or a deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The gate layer is formed by a low pressure chemical vapor deposition (LPCVD) process. The polycrystalline germanium is formed, and the capping material layer is composed of tantalum nitride formed by a chemical vapor deposition (CVD) process, but is not limited thereto. Next, a patterned photoresist layer (not shown) is formed over the cap layer material layer, and an etching process step is performed to remove portions of the stacked layers to form the gate stack layer 102 and the cap layer 112. The etching process step includes patterning the photoresist layer as a mask while removing a portion of the dielectric layer, a portion of the gate layer, and a portion of the capping material layer, and then removing the patterned photoresist layer; or first patterning the photoresist layer The pattern is transferred to the capping material layer, the patterned photoresist layer is removed, and the patterned capping material layer is used as a mask to remove a portion of the dielectric layer and a portion of the gate layer. Since the cap layer 112 is used as an etch hard mask in the lithography and etching process, one of the cap layers 112 has a width substantially equal to the width of one of the gate stack layers 102, that is, the first dielectric layer. 104. The first gate layer 106, the second dielectric layer 108, the second gate layer 110, and the cap layer 112 have the same width.

As shown in FIG. 3, compliantly forms a dielectric layer 114 on the semiconductor substrate 100. The dielectric layer 114 can cover the top surface of the cap layer 112, the side of the cap layer 112, and the side of the gate stack layer 102. The electrical layer 114 can be constructed of a single layer or a composite layer of insulating material. Then, a conductive layer (not shown) is formed on the dielectric layer 114, and an anisotropic etching process is performed, for example, a reactive-ion-etching (RIE) process to remove a portion of the conductive layer. To completely expose the dielectric layer 114 on the gate stack layer 102, and the remaining conductive layers form two first sidewalls 116A/116B around the opposite sidewalls of the gate stack layer 102, that is, two first sidewalls The 116A/116B can surround the gate stack layer 102 and the cap layer 112. Basically, the height h1 of one of the first side walls 116A/116B is related to the height h2 of one of the cover layers 112, that is, in the same etching system. Under the condition of the parameters, for example, the same etching solution selection ratio and the same etching time, the increase of the height h2 of the cap layer 112 will help to retain more conductive layers after the anisotropic etching process to increase formation. The original height h1 of the first side wall 116A/116B and a bottom width w1. In the present embodiment, the conductive layer for forming the first sidewall spacers 116A/116B includes a conductive material such as polysilicon, but is not limited thereto. In other embodiments, the material forming the first sidewall sub-116A/116B may also be an insulating material for use in other types of semiconductor device processes.

Next, as shown in FIG. 4, the cap layer 112 on the gate stack layer 102 is removed. When the cap layer 112 is composed of tantalum nitride, a wet etching process may be performed, and the etching liquid is preferably selected from the material of the first sidewall 116A/116B and the material of the second gate layer 110, for example: polycrystalline cookware. For example, a heated phosphoric acid solution or the like to completely remove the cap layer 112 and a portion of the dielectric layer 114, exposing the top surface of the gate stack layer 102, that is, the second gate layer 110, and retaining the surrounding gate The first sidewalls 116A/116B of the sidewalls of the pole stack layer 102, at this time, the height h3 of the remaining first sidewalls 116A/116B is still substantially greater than the height h4 of one of the gate stack layers 102. The method of removing the cap layer 112 is not limited thereto, and other processes for completely removing the cap layer 112 and making the height h3 of each of the first sidewalls 116A/116B still substantially larger than the height h4 of the gate stack layer 102 are also applicable to this invention.

As shown in FIG. 5, two second sidewalls 118A/118B are formed on a portion of the gate stack layer 102, wherein the second sidewall spacers 118A/118B are formed without completely overlapping the gate stack layer 102. The method of forming the second sidewall sub-118A/118B after removing the cap layer 112 includes: Compliance forms a material layer (not shown) on the semiconductor substrate 100 and covers the gate stack layer 102 and the first sidewall spacers 116A/116B, and the material of the material layer is connected to the first gate layer 106 and the second gate. The pole layer 110 and the first sidewalls 116A/116B preferably have an etch selectivity ratio, that is, the material layer is etched with respect to the first gate layer 106, the second gate layer 110, and the first sidewall spacers 116A/116B. The agents have different etch rates, for example, they may be selected from insulating materials including tantalum nitride or hafnium oxide. Thereafter, an etch process, such as an anisotropic etch process, is performed to remove portions of the material layer to expose the top surface of the first sidewall sub-116A/116B and a portion of the gate stack layer 102. In the present embodiment, the second sidewall sub-118A/118B has the same height h5 and the same bottom width w2 with respect to the top surface of the gate stack layer 102. Each of the second side walls 118A/118B directly contacts the corresponding first side wall sub-116A/116B, and the height h5 of each of the second side wall sub-118A/118B is substantially equal to the respective first side wall sub-116A/116B relative to the brake A height h6 of the top surface of the pole stack layer 102, that is, one of the apexes of each of the second sidewall sub-118A/118B and one of the apexes of each of the first sidewall sub-116A/116B has the same height with respect to the semiconductor substrate 100. In more detail, under the same etching process parameters, the size of the second sidewalls 118A/118B and the overlapping area with the top surface of the gate stack 102 are related to the height of the first sidewalls 116A/116B. That is, as the height h6 of the first sidewall sub-116A/116B increases, the height h5 and the bottom width w2 of the formed second sidewall sub-118A/118B will also increase after the etching process.

As shown in FIG. 6, an etching process, such as a dry etching process, is performed to remove portions of the first sidewalls 116A/116B to form a third gate 124 and simultaneously remove the second sidewalls 118A/118B. The gate stacks the layers 102 to form a two-gate stack Structures 102A/102B, and gate stack structures 102A/102B have a first gate 120 and a second gate 122, respectively. The height h7 of the third gate 124 is preferably substantially equal to the height h8 of the gate stack structure 102A/102B. In addition, preferably, in the etching process, part of the second sidewall spacers 118A/118B are also reduced by etching, and the remaining second sidewall spacers 118A'/118B' are located on the gate stack structure 102A/102B. And has a non-planar surface. The remaining second sidewalls 118A'/118B' can be selectively retained on the second gate 122, depending on the process or product requirements, without the need for additional processing.

Please refer to Figure 5 and Figure 6 together. It should be noted that since the second sidewall spacers 118A/118B are used as the etch mask in the above etching process, the gate stack layer 102 not covered by the second sidewall spacers 118A/118B is removed, that is, The width of the top surface of the exposed gate stack layer 102 is substantially equal to the distance between the first gate structure 126 and the second gate structure 128, that is, the present invention is replaced with the second sidewall sub-118A/118B. A mask as a mask to define the predetermined position of the gate structure not only helps to reduce the cost of the mask of the process, but also produces a smaller line width. In addition, using the second sidewall sub-118A/118B as a mask, the gate structure having the same width can be defined by self-alignment at the same time, that is, the bottom width w2 of the second sidewall sub-118A/118B is substantially equal to the gate. One of the bottom stack structures 102A has a bottom width w3 and one of the gate stack structures 102B has a bottom width w4. In more detail, after the etching process for removing a portion of the first sidewall spacers 116A/116B and a portion of the gate stack layer 102 is completed, three gates (the first gate 120, the second gate 122, and the third portion) are respectively formed. a first gate structure 126 and a second gate structure 128 of the gate 124), wherein the second sidewall The sub-118A'/118B' and the third gate 124 can be used to define the length of the channel region of the first gate structure 126 / the second gate structure 128. In addition, the third gates 124 are respectively formed on one side of the gate stack structure 102A/102B, and no unnecessary conductive layer remains between the first gate structure 126 and the second gate structure 128. Therefore, The etching process is further performed to remove the excess conductive layer, and the stringer composed of the conductive material is effectively prevented from being formed on the sidewall S1/S2 between the first gate structure 126 and the second gate structure 128. Further, the electrical performance of the semiconductor device is improved and the yield is improved.

As shown in FIG. 7, the first gate structure 126 and the second gate structure 128 are used as masks, and an ion implantation process is performed on both sides of the first gate structure 126 and the second gate structure 128. The source/drain doping region 130/132/134 is formed in the semiconductor substrate 100. In the embodiment, the source/drain doping region 132 can serve as the first gate structure 126 and the second gate structure 128. The common source region helps to reduce the area occupied by the semiconductor device to enhance the integration of the semiconductor device.

The present invention also provides a semiconductor device. In order to simplify the description, the same components are denoted by the same reference numerals in the following embodiments, and the overlapping portions will not be described again. Please refer to Figure 8. Figure 8 is a schematic view of a semiconductor device in accordance with a preferred embodiment of the present invention. As shown in FIG. 8, semiconductor device 148 includes semiconductor substrate 100 and at least one gate structure 136/138 disposed thereon. In the present embodiment, the first gate structure 136 and the second gate structure 138 respectively include a first gate 120, a second gate 122 and an upper surface that are not parallel to the semiconductor. a top cover layer 140 of the substrate, and a third gate 124 are located at the first gate 120 and the second gate 122 One side. The first gate 120, the second gate 122, and the third gate 124 may each be composed of a conductive material including a polysilicon, a metal halide, or a metal material having a specific work function. The material of the cap layer 140 may include an oxidation resistant material such as tantalum nitride or tantalum oxide. The first gate structure 136 and the adjacent second gate structure 138 are mirror-symmetrical to each other, that is, the first gate structure 136 and the second gate structure 138 have the same width w5/w6. In addition, the third gate 124 is a sidewall shape, and the third gate 124A of the first gate structure 136 is located on the left side of the first gate 120A and the second gate 122A, and the third gate structure 138 is third. The gate 124B is located on the right side of the first gate 120B and the second gate 122B. Taking the semiconductor device 148 as a flash memory unit as an example, the first gate 120 is a floating gate, the second gate 122 is a control gate, and the third gate 124 is a selection gate. A select gate, in addition, in some applications, the first gate 120 used as a floating gate may also include a material such as a nitrogen ruthenium compound to trap charges. . The height h7 of one of the third gates 124 is preferably substantially equal to the height h9 of the top surface of the second gate 122. The cap layer 140 substantially directly contacts the top surface of the second gate 122 and has a non-planar upper surface. In this embodiment, the cap layer 140 has a sidewall sub-structure and is on the same gate. In the structure 136/138, the arc surface of the cap layer 140 and the arc surface of the third gate 124 have protruding directions opposite to each other.

The first gate structure 136 and the second gate structure 138 respectively include a first dielectric layer 142 disposed between the semiconductor substrate 100 and the first gate 120, and a second dielectric layer 144 disposed on the first gate. Between 120 and the second gate 122, and an L-shaped third dielectric layer 146 are disposed between the third gate 124 and the first gate 120 and the second gate 122, and are located on the semiconductor substrate 100 and Three gates between 124. First dielectric layer 142, first Both the dielectric layer 144 and the third dielectric layer 146 may be composed of an insulating material including tantalum oxide, oxynitride or a high-k dielectric layer having a dielectric constant greater than 4. The first dielectric layer 142 can serve as a tunneling oxide layer, and the hot electrons tunnel into and out of the first gate 120 via the first dielectric layer 142 to achieve the data access function of the semiconductor device 148. The second dielectric layer 144 and the third dielectric layer 146 can serve as an inter-gate oxide layer to provide an insulating effect between the first gate 120, the second gate 122, and the third gate 124. In addition, the source/drain doping regions 130/132/134 are disposed in the semiconductor substrate 100 on both sides of the first gate structure 136 and the second gate structure 138.

In summary, the present invention firstly increases the original height of the first side wall by the cover layer, and then defines the size and the formed position of the second side wall by the first side wall, and then further the second side wall. As a mask, the three gates in the first gate structure/second gate structure are formed by the self-aligned process, which can reduce the cost of the mask of the process and effectively avoid the first gate structure/second gate structure. The formation of a residue on the sidewall.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧Flash memory unit

12,100‧‧‧Semiconductor substrate

14‧‧‧gate stacking

16‧‧‧Floating gate

18‧‧‧Control gate

20‧‧‧Selecting the gate

22,24,26,114‧‧‧ dielectric layer

28‧‧‧ source doped area

30‧‧‧汲Doped area

32‧‧‧Channel area

102‧‧‧ gate stack

102A, 102B‧‧‧ gate stack structure

104,142‧‧‧First dielectric layer

106‧‧‧First gate layer

108,144‧‧‧Second dielectric layer

110‧‧‧second gate layer

112‧‧‧ cover

116A, 116B‧‧‧ first side wall

118A, 118B, 118A’, 118B’‧‧‧ second side

120, 120A, 120B‧‧‧ first gate

122,122A, 122B‧‧‧second gate

124, 124A, 124B‧‧‧ third gate

126, 136‧‧‧ first gate structure

128,138‧‧‧second gate structure

130,132,134‧‧‧Source/drain-doped area

140‧‧‧Top cover

146‧‧‧ Third dielectric layer

148‧‧‧Semiconductor device

R‧‧‧ Remnant

H1, h2, h3, h4, h5, h6, h7, h8, h9‧‧‧ height

S, S1, S2‧‧‧ side wall

W1, w2, w3, w4, w5, w6‧‧‧ width

FIG. 1 is a cross-sectional view showing a conventional flash memory unit.

2 to 7 are schematic views showing a method of fabricating a semiconductor device in accordance with a preferred embodiment of the present invention.

Figure 8 is a schematic view of a semiconductor device in accordance with a preferred embodiment of the present invention.

100‧‧‧Semiconductor substrate

120, 120A, 120B‧‧‧ first gate

122,122A, 122B‧‧‧second gate

124, 124A, 124B‧‧‧ third gate

130,132,134‧‧‧Source/drain-doped area

136‧‧‧First gate structure

138‧‧‧Second gate structure

140‧‧‧Top cover

142‧‧‧First dielectric layer

144‧‧‧Second dielectric layer

146‧‧‧ Third dielectric layer

148‧‧‧Semiconductor device

H7, h9‧‧‧ height

W5, w6‧‧‧ width

Claims (19)

A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate; forming a gate stack on the semiconductor substrate, and having a cap layer on the gate stack; forming two first sidewalls on the gate stack Surrounding the opposite sidewalls of the layer; removing the cap layer; forming two second sidewalls on a portion of the gate stack layer; and simultaneously removing portions of the first sidewalls and the gate not covered by the second sidewalls The poles are stacked to form a two-gate stack structure. A method of fabricating a semiconductor device according to claim 1, wherein one of the cap layers has a width substantially equal to a width of one of the gate stack layers. The method of fabricating a semiconductor device according to claim 1, wherein the forming the first sidewalls comprises: forming a dielectric layer on the cap layer; forming a conductive layer on the dielectric layer; and removing the portion The conductive layer is to completely expose the dielectric layer on the gate stack layer. A method of fabricating a semiconductor device according to claim 3, wherein removing a portion of the conductive layer comprises performing an anisotropic etching process. A method of fabricating a semiconductor device according to claim 1, wherein the first sidewalls surround the gate stack layer and the cap layer. A method of fabricating a semiconductor device according to claim 1, wherein removing the cap layer comprises performing a wet etching process. The method of fabricating a semiconductor device according to claim 1, wherein a height of each of the first sidewalls is substantially larger than one of the gate stack layers after the cap layer is removed and the gate stack structures are formed. height. The method of fabricating a semiconductor device according to claim 1, wherein after the cap layer is removed, the step of forming the second sidewalls comprises: forming a layer of a substance on the semiconductor substrate; and removing a portion of the layer of material to expose the layer Waiting for the first sidewall and a portion of the top surface of the gate stack. A method of fabricating a semiconductor device according to claim 8, wherein removing a portion of the material layer comprises performing an anisotropic etching process. The method of fabricating a semiconductor device according to claim 1, wherein each of the second sidewalls directly contacts the corresponding first sidewall before removing a portion of the first sidewalls. The method of fabricating a semiconductor device according to claim 10, wherein a height of each of the second sidewalls relative to a top surface of the gate stack layer is substantially equal to each of the first sidewalls relative to the gate One of the top faces of the stacked layers. The method of fabricating a semiconductor device according to claim 1, wherein the gate stack layer comprises at least one gate layer and at least one dielectric layer. A method of fabricating a semiconductor device according to claim 12, wherein the gate layer comprises a conductive material. A method of fabricating a semiconductor device according to claim 1, wherein the first sidewalls comprise a conductive material. A method of fabricating a semiconductor device according to claim 1, wherein the cap layer and the second sidewalls each comprise an insulating material. A semiconductor device comprising: a semiconductor substrate; and at least one gate structure disposed on the semiconductor substrate, wherein the gate structure comprises a first gate, a second gate and a first stack sequentially stacked from bottom to top The upper surface is not parallel to the top cover layer of the semiconductor substrate, and the third gate is located at one side of the first gate and the second gate, and one of the top ends of the third gate is opposite to the top cover layer The top is low. The semiconductor device of claim 16, wherein the gate structure further comprises: a first dielectric layer disposed between the semiconductor substrate and the first gate; a second dielectric layer disposed on the first gate Between the pole and the second gate; and an L-shaped third dielectric layer disposed between the third gate and the first gate and the second gate, and located on the semiconductor substrate and the first Between the three gates. The semiconductor device of claim 16, wherein the first gate comprises a floating gate, the second gate comprises a control gate, and the third gate comprises a selection gate (select gate). The semiconductor device of claim 16, wherein the gate structure and the adjacent another gate structure are mirror-symmetrical to each other.