TWI495090B - Memory structure and fabricating method thereof - Google Patents

Description

Memory structure and manufacturing method thereof

The present invention relates to a memory structure and a method of fabricating the same, and more particularly to a memory structure having a self-aligned separation gate structure and a method of fabricating the same.

Among various non-volatile memory products, there is a flash memory that can perform operations such as storing, reading, erasing, etc., and the stored data does not disappear after power-off. It has become a memory component widely used in personal computers and electronic devices.

A typical flash memory is a floating gate and a control gate made of doped polysilicon. In addition, in the prior art, a charge trapping layer is used instead of a polysilicon floating gate, and the material of the charge trapping layer is, for example, tantalum nitride. The tantalum nitride charge trapping layer usually has a layer of yttrium oxide on top of each other to form an oxide-nitride-oxide (ONO) composite layer.

In addition, in order to reduce the memory cell area and enhance the writing effect, a select gate may be additionally provided on the control gate sidewall to form a split-gate structure.

It is an object of the present invention to provide a memory structure that has the advantage of being inexpensive to manufacture.

Another object of the present invention is to provide a method of fabricating a memory structure that can effectively simplify the process.

An embodiment of the present invention provides a memory structure including at least one memory cell including a substrate, a charge storage structure, a control gate, a selection gate, a dummy gate, a dielectric layer, and two doped regions. The charge storage structure is disposed on the substrate. The control gate is disposed on the charge storage structure. The selection gate is disposed on the substrate on the side of the control gate. The dummy gate is disposed on the substrate on the other side of the control gate. The dielectric layer is disposed between the selection gate and the control gate, between the selection gate and the substrate, between the dummy gate and the control gate, and between the dummy gate and the substrate. The doped regions are respectively disposed in the substrate on both sides of the structure formed by the control gate, the selection gate, and the dummy gate.

According to an embodiment of the invention, in the memory structure, the gate and the dummy gate have a recess, for example, on a side away from the control gate.

According to an embodiment of the invention, in the memory structure, the shape of the gate and the dummy gate is, for example, an L-shaped or L-shaped mirror image, respectively.

According to an embodiment of the invention, in the memory structure described above, the doped region close to the dummy gate further includes a substrate extending below the dummy gate.

According to an embodiment of the invention, in the memory structure, a spacer is further disposed on the sidewall of the selection gate and the sidewall of the dummy gate.

According to an embodiment of the invention, in the memory structure, a metal germanide layer is further disposed on the selective gate, the dummy gate and the doped region.

According to an embodiment of the invention, in the memory structure, the metal telluride layer further comprises a gate disposed on the control gate.

According to an embodiment of the invention, in the memory structure, the charge storage structure includes a bottom dielectric layer, a charge storage layer and a top dielectric layer in sequence from the substrate.

According to an embodiment of the invention, in the above memory structure, when the memory structure includes a plurality of memory cells, the adjacent two memory cells are, for example, in a mirror image configuration.

According to an embodiment of the present invention, in the memory structure, the dielectric layer includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer. The first dielectric layer is disposed between the selection gate and the control gate. The second dielectric layer is disposed between the selection gate and the substrate. The third dielectric layer is disposed between the dummy gate and the control gate. The fourth dielectric layer is disposed between the dummy gate and the substrate.

An embodiment of the invention provides a method of fabricating a memory structure comprising the following steps. First, a stacked structure is formed on a substrate, and the stacked structure includes a charge storage structure, a control gate, and a sacrificial layer from the substrate. Next, a dielectric layer is formed on the substrate exposed by the stacked structure and on the sidewalls of the control gate. Then, a conductor layer covering the stacked structure is conformally formed on the substrate. Next, a first spacer is formed on the conductor layers on both sides of the stacked structure, and the first spacer portion partially covers the conductor layer. Thereafter, a portion of the conductor layer is removed by using the first spacer as a mask to form a selective gate and a dummy gate on both sides of the stacked structure. Then, doped regions are respectively formed in the substrates on both sides of the structure formed by the control gate, the selection gate and the dummy gate.

According to an embodiment of the present invention, in the method of fabricating the memory structure described above, the method of forming the first spacer includes the following steps. First, a first spacer material layer covering the conductor layer is formed conformally. Next, an etch back process is performed on the first spacer material layer.

According to an embodiment of the present invention, in the method of fabricating the memory structure described above, the method of forming the doped region close to the dummy gate includes the following steps. First, a patterned photoresist layer exposing one side of the stacked structure is formed on the substrate. Next, the substrate is subjected to an ion implantation process using the patterned photoresist layer as a mask.

According to an embodiment of the present invention, in the method of fabricating a memory structure, a method of forming a doped region close to a select gate includes controlling a gate, selecting a gate, and a dummy gate as a mask. The substrate is subjected to an ion implantation process.

According to an embodiment of the invention, in the method of fabricating the memory structure, after the selection gate and the dummy gate are formed, the sacrificial layer is further removed.

According to an embodiment of the invention, in the method for fabricating a memory structure, the method further includes forming a metal telluride layer on the control gate, the selection gate, the dummy gate, and the doped region.

According to an embodiment of the invention, in the method of fabricating the memory structure, after the forming the gate and the dummy gate are formed, the first spacer is further removed.

According to an embodiment of the invention, in the method of fabricating the memory structure, after forming the gate and the dummy gate, a portion of the dielectric layer is removed to expose a portion of the substrate.

According to an embodiment of the present invention, in the method of fabricating the memory structure, after forming the gate and the dummy gate, forming a second surface on the sidewall of the gate and the sidewall of the dummy gate Two gap walls.

According to an embodiment of the invention, in the method for fabricating a memory structure, the method further includes forming a metal germanide layer on the select gate, the dummy gate, and the doped regions.

According to an embodiment of the invention, in the method of fabricating the memory structure, after forming the select gate and the dummy gate, the virtual gate is further removed.

According to an embodiment of the invention, in the method of fabricating the memory structure, the method of removing the dummy gate includes the following steps. First, a patterned photoresist layer is formed on the substrate exposing a side of the stacked structure close to the virtual gate. Next, the patterned photoresist layer is used as a mask to remove the dummy gate.

According to an embodiment of the present invention, in the method of fabricating the memory structure, the method of forming the doped region away from the selection gate includes patterning the photoresist layer as a mask after removing the dummy gate , the substrate is subjected to an ion implantation process.

According to an embodiment of the present invention, in the method for fabricating a memory structure, a method of forming a doped region close to a gate includes performing a ion implantation on the substrate by using a gate and a gate as a mask. Into the process.

According to an embodiment of the present invention, in the method of fabricating the memory structure, after removing the dummy gate, a third spacer is formed on both sides of the structure formed by the control gate and the selection gate. .

According to an embodiment of the invention, in the method for fabricating a memory structure, after removing the dummy gate, a metal germanide layer is formed on the selective gate and the doped region.

Based on the above, since the memory structure of the present invention is manufactured by using the first spacer as a mask, a part of the conductor layer is removed to form a selective gate and a dummy gate, so that the gate can be prevented from being defined by the photoresist. Overlap shift problems that can occur with poles and virtual gates.

In addition, the memory structure proposed by the present invention has the advantages of low manufacturing cost because the process is simple and the amount of use of the photomask can be reduced.

The above described features and advantages of the present invention will be more apparent from the following description.

1A to 1E are cross-sectional views showing a manufacturing process of a memory structure according to a first embodiment of the present invention.

First, referring to FIG. 1A, a stacked structure 102 is formed on a substrate 100, and the stacked structure 102 includes a charge storage structure 104, a control gate 106, and a sacrificial layer 108 from the substrate 100. The substrate 100 is, for example, a crucible substrate. The charge storage structure 104 may include a bottom dielectric layer 110, a charge storage layer 112, and a top dielectric layer 114 in sequence from the substrate 100. The material of the bottom dielectric layer 110 is, for example, ruthenium oxide. The material of the charge storage layer 112 is, for example, tantalum nitride. The material of the top dielectric layer 114 is, for example, yttrium oxide. In addition to controlling the conduction of the channel during reading and providing a transverse electric field during writing/erasing, the control gate 106 can protect the charge storage structure 104 underneath, thereby providing better uniformity of the charge storage structure 104 ( Uniformity). The material of the control gate 106 is, for example, doped polysilicon. The material of the sacrificial layer 108 is, for example, tantalum nitride. The method for forming the charge storage structure 104, the control gate 106 and the sacrificial layer 108 is formed, for example, by a deposition process and a patterning process. In this embodiment, although the description is made to form two stacked structures 102, it is not intended to limit the present invention, and it is within the scope of the present invention to form at least one stacked structure 102.

Next, a patterned photoresist layer 116 exposing one side of the stacked structure 102 is formed on the substrate 100. The material of the patterned photoresist layer 116 is, for example, a positive photoresist or a negative photoresist, and the formation method of the patterned photoresist layer 116 is formed, for example, by a lithography process.

Then, with the patterned photoresist layer 116 as a mask, a doped region 118 is formed in the substrate 100 on the side of the stacked structure 102 on which one of the dummy gates is formed. The method of forming the doping region 118 is formed by, for example, patterning the photoresist layer 116 as a mask to perform an ion implantation process on the substrate 100.

Next, referring to FIG. 1B, the patterned photoresist layer 116 is removed. The method of removing the patterned photoresist layer 116 is, for example, a dry de-resisting method or a wet de-glazing method.

Thereafter, a dielectric layer 120 is formed on the substrate 100 exposed by the stacked structure 102 and on the sidewalls of the control gate 106. The material of the dielectric layer 120 is, for example, ruthenium oxide, and the formation method of the dielectric layer 120 is, for example, a thermal oxidation method. In addition, the forming step of the dielectric layer 120 further forms the dielectric layer 120 on the sidewalls of the charge storage structure 104.

Next, a conductor layer 122 covering the stacked structure 102 is conformally formed on the substrate 100. The material of the conductor layer 122 is, for example, doped polysilicon, and the method of forming the conductor layer 122 is, for example, a chemical vapor deposition method.

Furthermore, the spacer material layer 124 covering the conductor layer 122 is conformally formed. The material of the spacer material layer 124 is, for example, tantalum nitride, and the method of forming the spacer material layer 124 is, for example, a chemical vapor deposition method.

Subsequently, referring to FIG. 1C , the spacer material layer 124 is etched back to form spacers 124 a on the conductor layers 122 on both sides of the stacked structure 102 , and the spacers 124 a partially cover the conductor layers 122 . In addition, the length of the subsequently formed select gate and the length of the dummy gate can be adjusted by the width of the spacer 124a.

Then, the partial conductor layer 122 is removed by using the spacers 124a as a mask to form the selection gate 122a and the dummy gate 122b on both sides of the stacked structure 102, and the sacrificial layer 108 can be exposed at the same time. Since the critical dimension of the selection gate 122a and the dummy gate 122b is determined by the film thickness of the conductor layer 122 and the width of the spacer 124a, it is not defined using a photomask, so that the process can be simplified. The selection gate 122a and the dummy gate 122b are isolated from the control gate 106 by the dielectric layer 120. The method of removing part of the conductor layer 122 is, for example, a dry etching method.

Moreover, since the dummy gate 122b is formed over the doped region 118, the doped region 118 proximate to the dummy gate 122b can extend into the substrate 100 under the dummy gate 122b. In addition, the selection gate 122a and the dummy gate 122b have, for example, notches 126 on the side remote from the control gate 108, respectively. The shapes of the selection gate 122a and the dummy gate 122b are respectively, for example, an L-shaped or L-shaped mirror image.

Then, referring to FIG. 1D, the sacrificial layer 108 can be selectively removed to expose the control gate 106. The removal method of the sacrificial layer 108 is, for example, a wet etching method or a dry etching method. In this embodiment, since the sacrificial layer 108 is similar in material to the spacers 124a, the spacers 124a can be selectively removed in the process of removing the sacrificial layer 108, which simplifies the process, but is not limited. this invention. In other embodiments, the sacrificial layer 108 and the spacers 124a may also be removed separately.

Next, referring to FIG. 1E, a spacer 128 may be selectively formed on the sidewall of the selection gate 122a and the sidewall of the dummy gate 122b. The material of the spacer 128 is, for example, ruthenium oxide. The spacer 128 is formed by, for example, conformally forming a spacer material layer covering the selection gate 122a and the dummy gate 122b by chemical vapor deposition, and then forming the spacer material layer by etch-etching. It should be noted that in the process of forming the spacers 128, a portion of the dielectric layer 120 on both sides of the structure formed by the control gate 106, the selection gate 122a and the dummy gate 122b can be simultaneously removed, and exposed. Part of the substrate 100.

Thereafter, the control gate 106, the selection gate 122a, the dummy gate 122b, and the spacer 128 can be used as a mask to perform an ion implantation process on the substrate 100 to control the gate 106, select the gate 122a, and the dummy gate. Doped regions 118, 130 are formed in the substrates 100 on both sides of the structure formed by the electrodes 122b, respectively. The doped region 118 is close to the dummy gate 122b, and the doped region 130 is close to the selection gate 122a. In this embodiment, although the doping regions 118, 130 are formed by the above method, and the doping region 118 is formed by performing two ion implantation processes, it is not intended to limit the present invention. Those skilled in the art may also use other methods to fabricate the doped regions 118, 130. That is, as long as the doping regions 118, 130 are respectively formed in the substrate 100 on both sides of the structure formed by the control gate 106, the selection gate 122a and the dummy gate 122b, it is within the scope of the present invention.

Next, a metal telluride layer 132 can be selectively formed on the control gate 106, the select gate 122a, the dummy gate 122b, and the doped regions 118, 130. The material of the metal telluride layer 132 is, for example, TiSi ₂ , CoSi ₂ or NiSi ₂ , and the method of forming the metal telluride layer 132 is formed, for example, by performing a self-aligned metal telluride process.

According to the above embodiment, since the memory structure is manufactured by using the spacers 124a as a mask, the partial conductor layer 122 is removed to form the selective gate 122a and the dummy gate 122b, so that the general separation gate memory can be avoided. The choice of gate alignment problems often encountered by cells.

2 is a cross-sectional view showing the structure of a memory according to a second embodiment of the present invention. 2 is a schematic illustration of the following description taken after FIG. 1C.

Next, a method of manufacturing the memory structure of the second embodiment of the present invention will be described with reference to FIG.

Referring to FIG. 2 and FIG. 1A to FIG. 1E simultaneously, the difference between the second embodiment and the first embodiment is that the second embodiment does not remove the sacrificial layer 108 covering the control gate 106, so the metal telluride layer 132 only It is formed on the selection gate 122a, on the dummy gate 122b, and on the doping regions 118, 130, but not on the control gate 108. Furthermore, the second embodiment selectively removes the spacers 124a after forming the selective gate 122a and the dummy gate 122b. The method of removing the spacers 124a is, for example, a dry etching method. In this embodiment, although the removal of the spacer 124a is taken as an example, it is not intended to limit the present invention. In other embodiments, the spacers 124a may also be retained. In addition, the same reference numerals in FIG. 2 and FIGS. 1A to 1E denote similar members, and have similar materials, configurations, formation methods, and effects, and thus will not be described again.

Similarly, the memory structure of the second embodiment is manufactured by using the spacers 124a as a mask to remove a portion of the conductor layer 122 to form the selective gate 122a and the dummy gate 122b, thereby avoiding the general separation gate memory. The choice of gate alignment problems encountered by the cell.

3A to 3D are cross-sectional views showing a manufacturing process of a memory structure according to a third embodiment of the present invention.

First, referring to FIG. 3A, a stacked structure 202 is formed on the substrate 200, and the stacked structure 202 includes a charge storage structure 204, a control gate 206, and a sacrificial layer 208 from the substrate 200. The substrate 200 is, for example, a crucible substrate. The charge storage structure 204 may include a bottom dielectric layer 210, a charge storage layer 212, and a top dielectric layer 214 in sequence from the substrate 200. The material of the bottom dielectric layer 210 is, for example, ruthenium oxide. The material of the charge storage layer 212 is, for example, tantalum nitride. The material of the top dielectric layer 214 is, for example, ruthenium oxide. In addition to controlling the conduction of the channel during reading and providing a transverse electric field during writing/erasing, the control gate 206 protects the charge storage structure 204 underneath, thereby providing better uniformity of the charge storage structure 204 ( Uniformity). The material of the control gate 206 is, for example, doped polysilicon. The material of the sacrificial layer 208 is, for example, tantalum nitride. The method for forming the charge storage structure 204, the control gate 206 and the sacrificial layer 208 is formed, for example, by a deposition process and a patterning process. In this embodiment, although the description is made to form two stacked structures 202, it is not intended to limit the present invention, and it is within the scope of the present invention to form at least one stacked structure 202.

Next, a dielectric layer 216 is formed on the substrate 200 exposed by the stacked structure 202 and on the sidewalls of the control gate 206. The material of the dielectric layer 216 is, for example, ruthenium oxide, and the formation method of the dielectric layer 216 is, for example, a thermal oxidation method. In addition, the step of forming the dielectric layer 216 further forms the dielectric layer 216 on the sidewalls of the charge storage structure 204.

Next, a conductor layer 218 covering the stacked structure 202 is conformally formed on the substrate 200. The material of the conductor layer 218 is, for example, doped polysilicon, and the method of forming the conductor layer 218 is, for example, a chemical vapor deposition method.

Furthermore, the spacer material layer 220 covering the conductor layer 218 is conformally formed. The material of the spacer material layer 220 is, for example, tantalum nitride, and the method of forming the spacer material layer 220 is, for example, a chemical vapor deposition method.

Subsequently, referring to FIG. 3B, the spacer material layer 220 is etched back to form a spacer 220a on the conductor layer 218 on both sides of the stacked structure 202, and the spacer 220a partially covers the conductor layer 218. In addition, the length of the subsequently formed selection gate and the length of the dummy gate can be adjusted by the width of the spacer 220a.

Then, a portion of the conductor layer 218 is removed by using the spacer 220a as a mask to form a selection gate 218a and a dummy gate 218b on both sides of the stacked structure 202, and the sacrificial layer 208 may be exposed at the same time. Since the critical dimension of the selection gate 218a and the dummy gate 218b is determined by the film thickness of the conductor layer 218 and the width of the spacer 220a, it is not defined by the reticle, so that the selection gate can be avoided due to the alignment offset. Length deviation. The gate 218a and the dummy gate 218b are separated from the control gate 206 by the dielectric layer 216. The method of removing part of the conductor layer 218 is, for example, a dry etching method.

Further, the selection gate 218a and the dummy gate 218b have, for example, notches 222 on the side remote from the control gate 208, respectively. The shape of the selection gate 218a and the dummy gate 218b are respectively, for example, an L-shaped or L-shaped mirror image.

Then, referring to FIG. 3C, the spacer 220a can be selectively removed. The method of removing the spacer 220a is, for example, a dry etching method. In this embodiment, although the removal of the spacer 220a is taken as an example, it is not intended to limit the present invention. In other embodiments, the spacers 220a may also be retained.

Next, a patterned photoresist layer 224 exposing the stacked structure 202 to one side of the dummy gate 218b is formed on the substrate 200. The material of the patterned photoresist layer 224 is, for example, a positive photoresist or a negative photoresist, and the formation method of the patterned photoresist layer 224 is formed, for example, by a lithography process.

Thereafter, the dummy gate 218b is removed by patterning the photoresist layer 224 as a mask. The method of removing the dummy gate 218b is, for example, a dry etching method. It should be noted that in the process of removing the dummy gate 218b, the dielectric layer 216 located near the dummy gate 218b can be simultaneously removed to expose a portion of the substrate 200.

Next, with the patterned photoresist layer 224 as a mask, the substrate 200 is subjected to an ion implantation process to separate the doped regions 226 from the substrate 200 of the selection gate 218a.

Subsequently, referring to FIG. 3D, the patterned photoresist layer 224 is removed. The method of removing the patterned photoresist layer 224 is, for example, a dry de-resisting method.

Furthermore, a spacer 228 can be selectively formed on the sidewall of the selection gate 218a and the sidewall of the control gate 206. The material of the spacer 228 is, for example, ruthenium oxide. The spacer 228 is formed by, for example, conformally forming a spacer material layer covering the selection gate 218a and the control gate 206 by chemical vapor deposition, and then forming the spacer material layer by etch-etching. It should be noted that in the process of forming the spacers 228, the dielectric layer 216 located near the selection gate 218a can be simultaneously removed to expose a portion of the substrate 200.

Thereafter, the control gate 206, the selection gate 218a and the spacer 228 can be used as a mask to perform an ion implantation process on the substrate 200 to form a substrate on both sides of the structure formed by the control gate 206 and the selection gate 218a. Doped regions 226, 230 are formed in 200, respectively. The doped region 226 is away from the select gate 218a, and the doped region 230 is adjacent to the select gate 218a. In this embodiment, although the doping regions 226, 230 are formed by the above method, and the doping region 226 is formed by performing two ion implantation processes, it is not intended to limit the present invention. Those skilled in the art may also use other methods to fabricate the doped regions 226, 230. That is, as long as the doping regions 226, 230 are respectively formed in the substrate 200 on both sides of the structure formed by the control gate 206 and the selection gate 218a, it is within the scope of the present invention.

Next, a metal telluride layer 232 can be selectively formed on the select gate 218a and the doped regions 226, 230. The material of the metal telluride layer 232 is, for example, TiSi ₂ , CoSi ₂ or NiSi ₂ , and the method of forming the metal telluride layer 232 is formed, for example, by performing a self-aligned metal telluride process.

According to the above embodiment, since the memory structure is manufactured by using the spacer 220a as a mask and removing part of the conductor layer 218 to form the selection gate 218a, the amount of the mask can be reduced, and the process can be simplified. .

Hereinafter, the memory structure of the above embodiment will be described below with reference to FIGS. 1E and 2.

Referring to FIG. 1E, the memory structure includes at least one memory cell 134. Each memory cell 134 includes a substrate 100, a charge storage structure 104, a control gate 106, a selection gate 122a, a dummy gate 122b, a dielectric layer 120, and a doping layer. Areas 118, 130. The adjacent two memory cells 134 are, for example, in a mirrored configuration. The charge storage structure 104 is disposed on the substrate 100. The charge storage structure 104 may include a bottom dielectric layer 110, a charge storage layer 112, and a top dielectric layer 114 in sequence from the substrate 100. Control gate 106 is disposed on charge storage structure 104. The selection gate 122a is disposed on the substrate 200 on the side of the control gate 106. The dummy gate 122b is disposed on the substrate 200 on the other side of the control gate 106. The selection gate 122a and the dummy gate 122b have, for example, notches 126 on the side remote from the control gate 108, respectively. The shapes of the selection gate 122a and the dummy gate 122b are respectively, for example, an L-shaped or L-shaped mirror image. The dielectric layer 120 includes dielectric layers 120a, 120b, 120c, and 120d. The dielectric layer 120a is disposed between the selection gate 122a and the control gate 106. The dielectric layer 120b is disposed between the selection gate 122a and the substrate 100. The dielectric layer 120c is disposed between the dummy gate 122b and the control gate 106, and the dielectric layer 120d is disposed between the dummy gate 122b and the substrate 100. In this embodiment, the dielectric layers 120a, 120b, 120c, and 120d are respectively a part of the dielectric layer 120, and are, for example, the same film layer formed by the same process, but are not intended to limit the present invention. In other embodiments, the dielectric layers 120a, 120b, 120c, 120d may also be different film layers formed by different processes. The doped regions 118, 130 are respectively disposed in the substrate 100 on both sides of the structure formed by the control gate 106, the selection gate 122a, and the dummy gate 122b. In addition, the memory cell 134 may further include a spacer 128 disposed on the sidewall of the selection gate 122a and the sidewall of the dummy gate 122b. The memory cell 138 may further include a metal telluride layer 132 disposed on the control gate 106, the select gate 122a, the dummy gate 122b, and the doped regions 118, 130. In addition, since the materials, arrangement, formation method and effect of each member in the memory structure of FIG. 1E have been described in detail in the above embodiments, they will not be described again.

Next, referring to FIG. 2 and FIG. 1E simultaneously, the difference between the second embodiment and the first embodiment is that since the memory cell 136 of the second embodiment further includes the sacrificial layer 108 covering the control gate 106, the metal telluride layer 132 is disposed on the selection gate 122a, the dummy gate 122b, and the doped regions 118, 130, and is not disposed on the control gate 108. Similarly, since the materials, arrangement, formation methods, and effects of the components in the memory structure of FIG. 2 have been described in detail in the above embodiments, they are not described herein.

Based on the above embodiments, the automatic alignment selection gate method of the above memory structure has the advantages of small area and stable performance.

In summary, the above embodiment has at least the following advantages:

1. The method of fabricating the memory structure proposed by the above embodiments can have high process stability.

2. The memory structure proposed in the above embodiments has the advantage of high integration.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope is subject to the definition of the scope of the patent application attached.

100, 200. . . Base

102, 202. . . Stack structure

104, 204. . . Charge storage structure

106, 206. . . Control gate

108, 208. . . Sacrificial layer

110, 210. . . Bottom dielectric layer

112, 212. . . Charge storage layer

114,214. . . Top dielectric layer

116, 224. . . Patterned photoresist layer

118, 130, 226, 230. . . Doped region

120, 120a, 120b, 120c, 120d, 216. . . Dielectric layer

122,218. . . Conductor layer

122a, 218a. . . Select gate

122b, 218b. . . Virtual gate

124, 220. . . Gap material layer

124a, 128, 220a, 228. . . Clearance wall

126, 222. . . Notch

132, 232. . . Metal telluride layer

134, 136. . . Memory cell

1A to 1E are cross-sectional views showing a manufacturing process of a memory structure according to a first embodiment of the present invention.

2 is a cross-sectional view showing the structure of a memory according to a second embodiment of the present invention.

3A to 3D are cross-sectional views showing a manufacturing process of a memory structure according to a third embodiment of the present invention.

100. . . Base

104. . . Charge storage structure

106. . . Control gate

110. . . Bottom dielectric layer

112. . . Charge storage layer

114. . . Top dielectric layer

118, 130. . . Doped region

120, 120a, 120b, 120c, 120d. . . Dielectric layer

122a. . . Select gate

122b. . . Virtual gate

126. . . Notch

128. . . Clearance wall

132. . . Metal telluride layer

134. . . Memory cell

Claims (25)

A memory structure includes at least one memory cell, the memory cell comprising: a substrate; a charge storage structure disposed on the substrate; a control gate disposed on the charge storage structure; and a selection gate disposed on The control gate is disposed on the substrate on one side of the gate; a dummy gate is disposed on the substrate on the other side of the control gate; a dielectric layer is disposed between the selection gate and the control gate, Selecting a gate and the substrate, between the dummy gate and the control gate, and between the dummy gate and the substrate; and two doped regions respectively disposed by the control gate and the selection gate In the substrate on both sides of the structure formed by the pole and the dummy gate, wherein the selection gate and the dummy gate respectively have a notch on a side away from the control gate. The memory structure of claim 1, wherein the shape of the selection gate and the dummy gate are respectively L-shaped or L-shaped. The memory structure of claim 1, wherein the doped region adjacent to the dummy gate further comprises a substrate extending below the dummy gate. The memory structure of claim 1, further comprising a spacer disposed on the sidewall of the select gate and the sidewall of the dummy gate. The memory structure of claim 1, further comprising a metal telluride layer disposed on the select gate and on the dummy gate On the doped region. The memory structure of claim 5, wherein the metal telluride layer further comprises a gate electrode disposed on the control gate. The memory structure of claim 1, wherein the charge storage structure comprises a bottom dielectric layer, a charge storage layer and a top dielectric layer in sequence from the substrate. The memory structure of claim 1, wherein when the memory structure comprises a plurality of memory cells, the adjacent two memory cells are mirrored. The memory structure of claim 1, wherein the dielectric layer comprises: a first dielectric layer disposed between the selection gate and the control gate; and a second dielectric layer disposed Between the selected gate and the substrate; a third dielectric layer disposed between the dummy gate and the control gate; and a fourth dielectric layer disposed on the dummy gate and the substrate between. A method of fabricating a memory structure, comprising: forming a stacked structure on a substrate, and the stacked structure comprises a charge storage structure, a control gate and a sacrificial layer from the substrate; the exposed structure is exposed Forming a dielectric layer on the substrate and the sidewall of the control gate; forming a conductor layer covering the stack structure on the substrate; forming a first space on the conductor layer on both sides of the stack structure a gap wall, and the first spacer wall partially covers the conductor layer; the first spacer wall is used as a mask to remove a portion of the conductor layer, so as to form a selection gate and a virtual gate on both sides of the stack structure And forming a doping region in the substrate on both sides of the structure formed by the control gate, the selection gate and the dummy gate. The method of fabricating a memory structure according to claim 10, wherein the method of forming the first spacer comprises: conformally forming a first spacer material layer covering the conductor layer; and the first The spacer material layer is subjected to an etching process. The method of fabricating a memory structure according to claim 10, wherein the forming of the doped region adjacent to the dummy gate comprises: forming a pattern on the substrate exposing a side of the stacked structure a photoresist layer; and using the patterned photoresist layer as a mask to perform an ion implantation process on the substrate. The method of fabricating a memory structure according to claim 10, wherein the method of forming the doped region adjacent to the select gate comprises using the control gate, the select gate, and the dummy gate as a mask And performing an ion implantation process on the substrate. The method of fabricating a memory structure according to claim 10, wherein after the forming the gate and the dummy gate are formed, the sacrificial layer is further removed. The system for memory structure as described in claim 14 The method further includes forming a metal telluride layer on the control gate, the select gate, the dummy gate and the doped regions. The method of fabricating a memory structure according to claim 10, wherein after the forming the gate and the dummy gate are formed, the first spacer is further removed. The method of fabricating a memory structure according to claim 10, wherein after forming the select gate and the dummy gate, further comprising removing a portion of the dielectric layer to expose a portion of the substrate. The method of fabricating a memory structure according to claim 10, wherein after forming the selective gate and the dummy gate, further comprising forming on a sidewall of the selective gate and a sidewall of the dummy gate a second spacer. The method for fabricating a memory structure according to claim 10, further comprising forming a metal telluride layer on the dummy gate, the dummy gate and the doped regions. The method of fabricating a memory structure according to claim 10, wherein after the forming the gate and the dummy gate are formed, the removing the dummy gate further comprises removing the dummy gate. The method of fabricating a memory structure according to claim 20, wherein the method of removing the dummy gate comprises: forming a pattern on the substrate exposing a side of the stacked structure close to the virtual gate a photoresist layer; and the patterned photoresist layer is used as a mask to remove the dummy gate. The system for memory structure as described in claim 21 The method of forming a doped region away from the select gate includes performing an ion implantation process on the substrate after the dummy gate is removed and the patterned photoresist layer is used as a mask. The method of fabricating a memory structure according to claim 20, wherein the method of forming the doped region adjacent to the select gate comprises using the control gate and the select gate as a mask to perform the substrate An ion implantation process. The method for fabricating a memory structure according to claim 20, wherein after the dummy gate is removed, a third gap is formed on both sides of the structure formed by the control gate and the selection gate. wall. The method of fabricating a memory structure according to claim 20, wherein after removing the dummy gate, further comprising forming a metal telluride layer on the selected gate and the doped regions.