TWI775303B - Memory device and manufacturing method thereof - Google Patents

Abstract

A memory device and a manufacturing method thereof are provided. The memory device includes a floating gate, an inter-gate dielectric layer, a gate coupling layer and a control gate. The floating gate is disposed on a substrate, and has a comb portion having finger portions laterally separated from one another. The inter-gate dielectric layer covers a top surface of the comb portion of the floating gate. The gate coupling layer covers the inter-gate dielectric layer. The control gate includes a conductive plug standing on the gate coupling layer, and is electrically connected to the gate coupling layer. The control gate is capacitively coupled to the comb portion of the floating gate along a vertical direction and a horizontal direction.

Description

Memory device and method of manufacturing the same

The present disclosure relates to a memory device and a method of manufacturing the same, and more particularly, to a non-volatile memory.

In modern electronic products, memory plays an indispensable role. In addition to storing user data, the memory is also used to store the code of the processor and the temporary data required in the operation of the processor. Generally speaking, memory can be divided into volatile memory and non-volatile memory. The data stored in volatile memory will disappear after a power failure, while the data stored in non-volatile memory will remain after a power failure.

Flash memory is a widely used non-volatile memory. Flash memory consists of a floating gate transistor, which includes a control gate and a floating gate separated by an insulating layer. The control gate is used to control the switching of the floating thyristor. On the other hand, charge can be stored in the floating gate set, which affects the threshold voltage of the floating gate transistor. Floating gate transistors can be used to store data by changing the starting voltage. Improving the capacitive coupling between the control gate and the floating gate can reduce the write voltage of the floating gate transistor and reduce the interference between adjacent floating gate transistors. However, it is currently difficult to improve the above-mentioned capacitive coupling without increasing the area of the floating thyristor due to the limitation of the manufacturing process.

The present disclosure provides a memory device and a manufacturing method thereof, which can improve the capacitive coupling between the floating gate and the control gate.

One aspect of the present disclosure provides a memory device, including: a floating gate disposed on a substrate and having a comb-shaped portion, wherein the comb-shaped portion has a plurality of stripe patterns laterally spaced apart from each other; between the gates a dielectric layer covering the upper surface of the comb-shaped portion of the floating gate; a gate coupling layer covering the inter-gate dielectric layer; and a control gate including standing on the gate coupling layer The conductive plug is electrically connected to the gate coupling layer, wherein the control gate is capacitively coupled to the comb-shaped portion of the floating gate in the vertical direction and the horizontal direction.

In some embodiments, the inter-gate dielectric layer and the gate coupling layer substantially completely cover the upper surface of the comb portion of the floating gate.

In some embodiments, the memory device further includes a metal silicide layer. A metal silicide layer is formed on the gate coupling layer. The conductive plug of the control gate is electrically connected to the gate coupling layer through the metal silicide layer.

In some embodiments, the floating gate further has another portion extending over the active region of the substrate and in contact with the active region through the tunnel dielectric layer.

In some embodiments, the memory device further includes an isolation structure. The isolation structure is disposed in the substrate and surrounds the active region.

In some embodiments, the comb portion of the floating gate, the inter-gate dielectric layer, and the gate coupling layer overlap the isolation structure.

In some embodiments, the inter-gate dielectric layer further covers the sidewalls of the comb-shaped portion of the floating gate, and the gate coupling layer is further filled in between the strip patterns of the comb-shaped portion of the floating gate. in space.

In some embodiments, the inter-gate dielectric layer has a plurality of portions laterally spaced apart from each other, respectively covering a plurality of stripe patterns of combs of the floating gate. The gate coupling layer also has portions laterally spaced apart from each other, covering the portions of the inter-gate dielectric layer, respectively.

In some embodiments, the control gate further includes at least one conductive wall extending between adjacent strip patterns of the comb-shaped portion of the floating gate.

Another aspect of the present disclosure provides a method of fabricating a memory device, comprising: forming a floating gate over a substrate, wherein the floating gate has comb-shaped portions, and the comb-shaped portions have laterally spaced apart a plurality of stripe patterns; forming an inter-gate dielectric layer on the comb portion of the floating gate; forming a gate coupling layer on the inter-gate dielectric layer; and forming a control gate on the substrate, wherein the control gate comprises The conductive plug stands on the gate coupling layer and is electrically connected to the gate coupling layer, and wherein the control gate is capacitively coupled to the comb-shaped portion of the floating gate in the vertical direction and the horizontal direction.

Based on the above, by disposing the gate coupling layer between the floating gate and the conductive plug of the control gate, the capacitive coupling area between the control gate and the floating gate can be increased. In some embodiments, the gate coupling layer covers the top surface and sidewalls of the floating gate, so that the control gate electrically connected to the gate coupling layer can be capacitively connected to the gate coupling layer in the vertical and horizontal directions through the gate coupling layer. coupled to the floating gate. In other embodiments, the gate coupling layer can be used to increase the capacitive coupling area between the control gate and the floating gate in the vertical direction, and the control gate can further include a conductive wall extending on the side of the floating gate. In this way, the control gate can still be capacitively coupled to the floating gate in the vertical and horizontal directions.

FIG. 1A is a schematic cross-sectional view of a semiconductor structure 100 with embedded memory device 10 in accordance with some embodiments of the present disclosure. FIG. 1B is a schematic plan view of the memory device 10 shown in FIG. 1A .

Referring to FIG. 1A , in some embodiments, the memory device 10 is an embedded memory device. In such embodiments, the memory device 10 may be formed in the memory region 100A of the semiconductor structure 100 , and the logic circuit may be formed in the logic region 100B of the semiconductor structure 100 . The boundary of the memory region 100A and the logic region 100B may be defined by a portion of the isolation structure 104 formed in the substrate 102 . The substrate 102 may be a semiconductor wafer, or may be a semiconductor-on-insulator (SOI) wafer. For example, the semiconductor material in a semiconductor wafer or SOI wafer may include silicon. In addition, in some embodiments, the isolation structure 104 may be a trench isolation structure, and may extend from the top surface of the substrate 102 to the interior of the substrate 102 .

In some embodiments, each memory cell of the memory device 10 includes an access transistor AT and a floating gate transistor FT. The floating thyristor FT is used for storing data, and the access transistor AT is connected to the floating thyristor FT and can be used to control the access of the floating thyristor FT. In some embodiments, the access transistor AT is formed on the surface region of the active area AA. The active area AA may be a well area formed in the substrate 102 and surrounded by a portion of the isolation structure 104 . The access transistor AT includes a gate electrode 106 formed on the active area AA, and a doped area 108 and a doped area 110 formed in the active area AA. The doped region 108 and the doped region 110 are located on opposite sides of the gate electrode 106 and have another conductivity type different from that of the active region AA, and can be used as the drain electrode and the source electrode of the access transistor AT. When the access transistor AT is turned on, a conductive channel may be formed in the portion of the active area AA located between the doped area 108 and the doped area 110 . On the other hand, when the access transistor AT is turned off, the above-mentioned conductive path does not exist. In some embodiments, the access transistor AT and the floating gate transistor FT are connected to each other by a common drain/source (eg, the doped region 108 ). In such embodiments, the potential of one of the terminals of the floating thyristor FT is controlled by the access transistor AT. In this way, the access transistor AT can control the switching of the floating gate transistor FT, thereby controlling the access of the floating gate transistor FT.

As shown in FIG. 1A , a gate dielectric layer 112 is further disposed between the gate electrode 106 and the surface of the active area AA. In some embodiments, the material of the gate dielectric layer 112 includes silicon oxide. In addition, at least one spacer 114 may be disposed around the gate electrode 106 and the gate dielectric layer 112 . For example, the spacer 114 may include a spacer 114a and a spacer 114b. The spacer 114b is disposed outside the spacer 114a, and the spacer 114a may have an extension portion extending below the spacer 114b. In some embodiments, the spacer 114a and the spacer 114b may be formed of silicon oxide or silicon nitride, respectively. The doped regions 108 and 110 in the active area AA may be located outside the spacers 114 (eg, outside the spacers 114 b ), and may or may not extend slightly below the spacers 114 . In some embodiments, the access transistor AT further includes a pair of lightly doped regions 116 in the active region AA. The pair of lightly doped regions 116 are disposed on the sides of the doped region 108 and the doped region 110 facing each other, and can be regarded as an extension of the doped region 108 and the doped region 110 . As such, the lightly doped regions 116 may extend below the spacers 114 , and may or may not extend slightly below the gate dielectric layer 112 . The conductivity type of the lightly doped region 116 may be the same as the conductivity type of the doped region 108 and the doped region 110 , and the doping concentration of the lightly doped region 116 may be lower than that of the doped region 108 and the doped region 110 . concentration.

On the other hand, in some embodiments, the floating gate transistor FT includes a floating gate 120, a doped region 122, and a doped region 108 common to the access transistor AT. A portion of the floating gate 120 is formed on the active region AA, and the doped region 122 and the doped region 108 are located in the active region AA and on opposite sides of the portion of the floating gate 120 . The conductivity type of the doped region 122 and the doped region 108 can be different from that of the active region AA, and can be used as the drain and source of the floating gate transistor FT. When the floating thyristor FT is turned on, a conductive channel can be formed in the portion of the active region AA located between the doped region 122 and the doped region 108 . On the other hand, when the floating thyristor FT is turned off, the above-mentioned conduction path does not exist. In addition, during the write operation, the carriers can be tunneled into the floating gate 120 by the above-mentioned conductive channel. On the other hand, during the erase operation, the carriers stored in the floating gate 120 can be returned to the active area AA by the tunneling effect. In some embodiments, the floating gate 120 is composed of the same material as the gate 106 of the access transistor AT.

A tunnel dielectric layer 124 is further disposed between the active area AA and the portion of the floating gate 120 located on the active area AA. In some embodiments, the tunnel dielectric layer 124 is composed of the same material as the gate dielectric layer 112 of the access transistor AT. In addition, similar to the spacer 114 of the access transistor AT, at least one spacer 126 may be disposed around the floating gate 120 and the tunnel dielectric layer 124 . For example, the spacer 126 may include a spacer 126a and a spacer 126b. The spacer 126b is disposed outside the spacer 126a, and the spacer 126a may have an extension portion extending below the spacer 126b. In some embodiments, the spacer 126a and the spacer 126b may be formed of silicon oxide or silicon nitride, respectively. The doped regions 108 and 122 in the active area AA may be located outside the spacers 126 (eg, outside the spacers 126 b ), and may or may not extend slightly below the spacers 126 . In some embodiments, the access transistor AT further includes a pair of lightly doped regions 128 in the active region AA. The pair of lightly doped regions 128 are disposed on the sides of the doped region 108 and the doped region 122 facing each other, and can be regarded as an extension of the doped region 108 and the doped region 122 . As such, lightly doped regions 128 may extend below spacers 126 , and may or may not extend slightly below tunnel dielectric layer 124 . The conductivity type of the lightly doped region 128 may be the same as the conductivity type of the doped region 108 and the doped region 122 , and the doping concentration of the lightly doped region 128 may be lower than that of the doped region 108 and the doped region 122 concentration.

Referring to FIGS. 1A and 1B , the floating gate 120 further extends beyond the range of the active area AA. As shown in FIG. 1A , the extended portion 120e of the floating gate 120 may be located on the isolation structure 104 surrounding the active area AA. As shown in FIG. 1B , the extending portion 120e of the floating gate 120 may include a comb portion CM and a connecting portion BR. The comb-shaped portion CM of the floating gate 120 has a plurality of strip-shaped patterns that are laterally spaced apart from each other, and these strip-shaped patterns respectively have one end (eg, the bottom end shown in FIG. 1B ) of the adjacent strip-shaped patterns. Pattern side connection. For example, the plurality of stripe patterns of the comb portion CM extend in the direction Y, and the lateral patterns for connecting the plurality of stripe patterns may extend in the direction X. On the other hand, the portion of the floating gate 120 located in the active area AA is connected to the comb-shaped portion CM through the connection portion BR. In some embodiments, the connecting portion BR extends along the direction Y. It should be noted that, in FIG. 1A , the portion of the floating gate 120 located on the isolation structure 104 may be a cross-sectional view of a plurality of strip patterns (as shown in FIG. 1B ) of the comb-shaped portion CM of the floating gate 120 Schematic.

Referring to FIG. 1A , in some embodiments, the tunnel dielectric layer 124 is not disposed between the extended portion 120 e of the floating gate 120 and the isolation structure 104 . In addition, in some embodiments, the extended portion 120e of the floating gate 120 is also surrounded by the spacer 126 . Furthermore, the floating gate transistor FT further includes an inter-gate dielectric layer 130 , a gate coupling layer 132 and a control gate 134 located on the extending portion 120 e of the floating gate 120 . The control gate 134 is electrically connected to the gate coupling layer 132 , and the control gate 134 and the gate coupling layer 132 are capacitively coupled to the extension portion 120 e of the floating gate 120 through the inter-gate dielectric layer 130 . The control gate 134 is used to control the switching of the floating gate transistor FT, and the floating gate 120 capacitively coupled to the control gate 134 affects the starting voltage of the floating gate transistor FT. By arranging the gate coupling layer 132 between the control gate 134 and the floating gate 120, the coupling area between the control gate 134 and the floating gate 120 can be increased, and the control gate 134 and the floating gate 120 can be improved. Capacitive coupling between gates 120 . In this way, the operating voltage and power consumption of the floating thyristor FT can be effectively reduced. As shown in FIGS. 1A and 1B , the inter-gate dielectric layer 130 , the gate coupling layer 132 and the control gate 134 are disposed on the comb-shaped portion CM of the floating gate 120 and may not cover the floating gate 120 The connection part BR and the part located on the active area AA. In some embodiments, the inter-gate dielectric layer 130 and the gate coupling layer 132 substantially completely cover the upper surface of the comb portion CM of the floating gate 120 . As shown in FIG. 1A , in some embodiments, the inter-gate dielectric layer 130 conformally covers the comb portion CM of the floating gate 120 and the spacers 126 therearound. The gate coupling layer 132 covers the inter-gate dielectric layer 130 and fills the recesses between the plurality of strip patterns of the comb-shaped portion CM of the floating gate 120 . The control gate 134 may include a plurality of conductive plugs 134 a, and the plurality of conductive plugs 134 a stand on the gate coupling layer 132 . In some embodiments, the plurality of conductive plugs 134a may be located between adjacent strip patterns of the comb portion CM of the floating gate 120 . As shown in FIG. 1B , in some embodiments, a plurality of conductive plugs 134 a separated from each other may be disposed between adjacent strip patterns of the comb portion CM of the floating gate 120 . The inter-gate dielectric layer 130 may be formed of a dielectric material, and the gate coupling layer 132 and the control gate 134 may be formed of a conductor material. For example, the above-mentioned dielectric material may include tetraethoxysilane (TEOS) silicon oxide, high dielectric constant (higk-k) dielectric material (eg, a dielectric material with a dielectric constant greater than 3.9) or its combination. On the other hand, the conductor material constituting the gate coupling layer 132 may include, for example, polysilicon, and the conductor material constituting the control gate 134 may include, for example, tungsten.

Referring to FIG. 1A , the semiconductor structure 100 may further include a transistor T in the logic region 100B. The transistor T can be an active element in the logic circuit. In other words, the logic circuit may also include other active elements and/or passive elements. In some embodiments, transistor T may be similar or identical to access transistor AT in structure and configuration, but transistor T and access transistor AT may be of the same or different conductivity types. Similar to the access transistor AT, the transistor T is disposed on the surface area of the active area AA' surrounded by the isolation structure 104 . The transistor T may include a gate electrode 136 formed on the active region AA', and a doped region 138 and a doped region 140 formed in the active region AA'. The doped region 138 and the doped region 140 are located on opposite sides of the gate electrode 136 and have another conductivity type different from that of the active region AA', and can be used as the drain electrode and the source electrode of the transistor T. In some embodiments, a gate dielectric layer 142 is further disposed under the gate electrode 136 , and one or more spacers 144 (for example, including a spacer 144 a and a spacer 144 ) may be disposed around the gate electrode 136 and the gate dielectric layer 142 144b). In addition, the transistor T may further include a pair of lightly doped regions 146 . The gate 136, doped regions 138, doped regions 140, gate dielectric layer 142, spacers 144, and lightly doped regions 146 of the transistor T may be similar to the gate 106 and doped regions 108 of the access transistor AT , the doped region 110 , the gate dielectric layer 112 , the spacer 114 and the lightly doped region 116 , which will not be described in detail here.

In some embodiments, the semiconductor structure 100 further includes a metal silicide layer 150 . The metal silicide layer 150 spans the memory region 100A and the logic region 100B. In the memory region 100A, portions of the metal silicide layer 150 cover the top surfaces of the doped region 108, the doped region 110, and the doped region 122, and cover the gate 106 and the active region AA of the floating gate 120. upper part. In addition, in the memory region 100A, other parts of the metal silicide layer 150 cover the upper surface of the gate coupling layer 132, so that the control gate 134 (eg, the conductive plug 134a of the control gate 134) passes through the metal silicide This portion of layer 150 is in contact with gate coupling layer 132 . On the other hand, in the logic region 100B, some portions of the metal silicide layer 150 cover the upper surfaces of the gate electrode 136 , the doped region 138 and the doped region 140 . In some embodiments, the material of the metal silicide layer 150 may include titanium silicide, tungsten silicide, tantalum silicide, molybdenum silicide, cobalt silicide, nickel silicide, or the like.

In some embodiments, the semiconductor structure 100 further includes a plurality of conductive plugs 152 . Some conductive plugs 152 stand on the doped region 110 and the doped region 122 in the memory region 100A to establish electrical connection with the access transistor AT and the floating gate transistor FT. In the embodiment in which the access transistor AT and the floating thyristor FT are interconnected by the doped region 108, the doped region 108 may be electrically floating, and there may be no conductive plugs disposed thereon. On the other hand, other conductive plugs 152 stand on the doped region 138 and the doped region 140 in the logic region 100B to establish electrical connection with the drain and source of the transistor T. In addition, as shown in FIG. 1B , another conductive plug 152 may also be disposed on the gate 106 of the access transistor AT. Similarly, although not shown in FIG. 1A or FIG. 1B , additional conductive plugs 152 (not shown) may optionally be disposed over the gate 136 of the transistor T in the logic region 100B. In some embodiments, compared to conductive plug 134a disposed above floating gate 120 (ie, a portion of control gate 134), conductive plug 152 disposed above gate 106, and Additional conductive plugs 152 on 136, conductive plugs 152 standing on doped region 110, doped region 122, doped region 138, and doped region 140 may have a higher height. In addition, in some embodiments, the conductive plug 134a and the conductive plug 152 may be made of the same conductive material (eg, tungsten).

In some embodiments, the interlayer dielectric layer 154 comprehensively covers the substrate 102, and covers the components of the access transistor AT, the floating gate transistor FT and the transistor T disposed on the substrate 102, and laterally surrounds The conductive plug 134a and the conductive plug 152. In this way, the conductive plug 134a and the conductive plug 152 can be regarded as passing through the interlayer dielectric layer 154 to establish electrical connection with the access transistor AT, the floating gate transistor FT and the transistor T. Additionally, in some embodiments, the etch stop layer 156 is further lined below the interlayer dielectric layer 154 . In such embodiments, the etch stop layer 156 may conformally cover the substrate 102 and components of the access transistor AT, the floating thyristor FT, and the transistor T disposed on the substrate 102 . In addition, the conductive plug 134a may pass through the etch stop layer 156 and be electrically connected to the gate coupling layer 132 (eg, electrically connected to the gate coupling layer 132 via the metal silicide layer 150). Similarly, the conductive plug 152 can pass through the etch stop layer 156 and be electrically connected to the doped regions of the access transistor AT, the floating gate transistor FT and the transistor T and the gate 106 and the gate 136 (eg, via The metal silicide layer 150 is electrically connected to these doped regions and the gate). For example, the interlayer dielectric layer 154 and the etch stop layer 156 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like, respectively.

As described above, by providing the gate coupling layer 132, the capacitive coupling between the control gate 134 and the floating gate 120 can be increased. Specifically, compared to forming the control gate into another comb-shaped structure to be capacitively coupled with the comb-shaped portion CM of the floating gate 120 laterally, the floating gate 120 of the embodiment of the present disclosure has vertical and horizontal directions. Both are capacitively coupled to the control gate 134 via the gate coupling layer 132 . By increasing the capacitive coupling between the floating gate 120 and the control gate 134, the operating voltage of the floating gate transistor FT can be effectively reduced.

FIG. 2 is a fabrication flow diagram of the semiconductor structure 100 shown in FIG. 1A in accordance with some embodiments. 3A-3I are schematic cross-sectional views of structures at various stages during the manufacturing flow shown in FIG. 2 .

Referring to FIG. 2 and FIG. 3A , step S100 is performed to form the isolation structure 104 and the active area AA and the active area AA' in the substrate 102 . In the embodiment in which the isolation structure 104 is a trench isolation structure, the method for forming the isolation structure 104 may include forming a recess on the surface of the substrate 102 through a lithography process and an etching process, and then filling the recess with an insulating material to form the isolation structure 104. On the other hand, the active area AA and the active area AA' can be formed in the exposed area of the substrate 102 by a lithography process and an ion implantation process. In some embodiments, the isolation structure 104 may be formed first, and then the active area AA and the active area AA' may be formed. In another alternative embodiment, the active area AA and the active area AA' can also be formed first, and then the isolation structure 104 can be formed.

2 and FIG. 3B , step S102 is performed to form the gate dielectric layer 112 and the gate dielectric layer 142 , the gate electrode 106 and the gate electrode 136 , the tunnel dielectric layer 124 and the floating gate electrode 120 on the substrate 102 . . In some embodiments, an oxide layer can be selectively formed on the surfaces of the active area AA and the active area AA' by a thermal oxidation process. Then, a fully covered gate material layer can be formed on the isolation structure 104 and the oxide layer by a deposition process (eg, a chemical vapor deposition process). Next, some parts of the gate material layer and the oxide layer under the parts are removed by a lithography process and an etching process. The remaining portion of the oxide layer may form the gate dielectric layer 112 , the gate dielectric layer 142 and the tunnel dielectric layer 124 . On the other hand, the remaining portion of the gate material layer forms the gate 106 , the gate 136 and the floating gate 120 .

2 and 3C, step S104 is performed to form the lightly doped region 116, the lightly doped region 128 and the lightly doped region 146 in the active area AA and the active area AA'. In some embodiments, the above-mentioned lightly doped regions can be formed by an ion implantation process. During this ion implantation process, the gate 106 , the gate 136 , the floating gate 120 and the isolation structure 104 can be used as masks, so that only the active area AA and the exposed portion of the active area AA' are ion implanted as Lightly doped region 116 , lightly doped region 128 and lightly doped region 146 .

2 and 3D, step S106 is performed to form spacers 114, 126 and 144 on the active area AA and the active area AA', and form doping in the active area AA and the active area AA' Region 108 , doped region 110 , doped region 122 , doped region 138 and doped region 140 . In some embodiments, one or more layers of spacer material are formed on the current structure by a deposition process (eg, a chemical vapor deposition process), followed by an etch-back process (eg, using an anisotropic etch process) to remove Remove some portion of the spacer material layer. The remaining portion of the spacer material layer may form the spacer 114 , the spacer 126 and the spacer 144 . In addition, in some embodiments, the gate 106 , the gate 136 , the floating gate 120 , the spacer 114 , the spacer 126 , the spacer 144 and the isolation structure 104 are used as masks to perform the ion implantation process to The active area AA and the exposed portion of the active area AA′ form the doped area 108 , the doped area 110 , the doped area 122 , the doped area 138 and the doped area 140 .

Referring to FIG. 2 and FIG. 3E, step S108 is performed to form a dielectric layer 300 on the current structure. The dielectric layer 300 fully and conformally covers the structure shown in FIG. 3D. In steps that will be described with reference to FIG. 3H , the dielectric layer 300 will be patterned to form the intergate dielectric layer 130 . In some embodiments, the dielectric layer 300 is formed by a deposition process, such as a chemical vapor deposition process.

Referring to FIG. 2 and FIG. 3F , step S110 is performed to form the conductor layer 302 on the current structure. The conductor layer 302 completely covers the dielectric layer 300 . In steps that will be described with reference to FIG. 3H , the conductor layer 302 will be patterned to form the gate coupling layer 132 . In some embodiments, the conductor layer 302 is formed by a deposition process, such as a chemical vapor deposition process.

Referring to FIG. 2 and FIG. 3G , step S112 is performed to form a mask pattern 304 on the extending portion 120 e of the floating gate 120 . The mask pattern 304 covers the extending portion 120e of the floating gate 120 and the surrounding spacers 126 and the dielectric layer 300 and the conductor layer 302 above. On the other hand, the floating gate 120 , the spacer 126 , other parts of the dielectric layer 300 and the conductor layer 302 , and the access transistor T and the transistor T are not covered by the mask pattern 304 . In some embodiments, the mask pattern 304 is a photoresist pattern. In such embodiments, the mask pattern 304 may be formed by a lithography process.

Referring to FIG. 2 and FIG. 3H , step S114 is performed to remove the portions of the dielectric layer 300 and the conductor layer 302 that are not covered by the mask pattern 304 . In this way, the gate 106 of the access transistor AT, the portion other than the extended portion 120e of the floating gate 120 of the floating gate transistor FT, and the gate 136 of the transistor T are exposed. In addition, a portion of the doped region 108, the doped region 110, the doped region 122, the doped region 138, the doped region 140, and the isolation structure 104 are also exposed. The remaining portion of the dielectric layer 300 forms the inter-gate dielectric layer 130 , and the remaining portion of the conductor layer 302 forms the gate coupling layer 132 . In some embodiments, the above-mentioned removing step is accomplished by an etching process. During this etching process, the mask pattern 304 can serve as an etching mask.

After the above-mentioned removing steps are completed, the mask pattern 304 can be removed. After removing the mask pattern 304, the gate coupling layer 132 is exposed. In some embodiments, the mask pattern 304 is removed by a stripping process.

Referring to FIG. 2 and FIG. 3I , step S116 is performed to form the metal silicide layer 150 . The metal silicide layer 150 is selectively formed on the gate coupling layer 132, the portion other than the extended portion 120e of the floating gate 120, the gate 106, the gate 136, the doped region 108, the doped region 110, the doped region Region 122 is on the surface of doped region 138 and doped region 140 , but may not cover exposed portions of isolation structure 104 . In some embodiments, a metal layer is fully coated on the structure shown in FIG. 3H by a deposition process (eg, a physical vapor deposition process), and the silicon-containing material and the metal are formed by a heat treatment process. The layers react to form metal silicides. Subsequently, unreacted portions of the metal layer can be removed. The remaining metal silicide forms the metal silicide layer 150 .

Referring to FIG. 2 and FIG. 1A , step S118 is performed to form the etch stop layer 156 and the interlayer dielectric layer 154 . The etch stop layer 156 fully and conformally covers the structure shown in FIG. 3I , and the interlayer dielectric layer 154 is fully formed on the etch stop layer 156 . In some embodiments, the etch stop layer 156 and the interlayer dielectric layer 154 are formed by a deposition process (eg, a chemical vapor deposition process), respectively.

Next, step S120 is performed to form the conductive plugs 134 a and the conductive plugs 152 . In some embodiments, methods of forming conductive plugs 134a, conductive plugs 152 include forming vias through interlayer dielectric layer 154 and etch stop layer 156, followed by deposition processes, plating processes, or a combination thereof. The through holes are filled with conductive material to form the conductive plugs 134 a and the conductive plugs 152 .

So far, the semiconductor structure 100 shown in FIG. 1A has been completed by the manufacturing methods of some embodiments. Although not shown, more metallization layers and ILD layers can be formed on the ILD layer 154 subsequently, and a packaging process can be performed to form a semiconductor die. It should be noted that even if the manufacturing process of the gate coupling layer 132 is not formed, a lithography process similar to that shown in FIG. 3G is required to define the position where the metal silicide layer is to be formed. In the disclosed embodiment, the above-mentioned lithography process is used to pattern the conductor layer 302 to form the metal silicide layer 150 . In other words, compared with the manufacturing process in which the gate coupling layer 132 is not formed, the embodiment of the present disclosure does not add an additional lithography process due to the additional formation of the gate coupling layer 132 .

FIG. 4A is a schematic cross-sectional view of a semiconductor structure 400 embedded with a memory device 40 according to other embodiments of the present disclosure. FIG. 4B is a schematic plan view of the memory device 40 shown in FIG. 4A . The semiconductor structure 400 and the memory device 40 shown in FIGS. 4A and 4B are similar to the semiconductor structure 100 and the memory device 10 shown in FIGS. 1A and 1B . Only the differences between different embodiments will be described below, and the same or similar points will not be repeated. In addition, similar reference numerals represent similar components (eg, gate coupling layer 132 and gate coupling layer 432).

4A and 4B, the gate coupling layer 432 located on the extension portion 120e of the floating gate 120 extends along the extension portion 120e of the floating gate 120, and may not cover the surrounding spacers 126 and Isolated structure 104 . However, considering the process error, the gate coupling layer 432 may also partially cover the spacer 126 around the extended portion 120 e of the floating gate 120 . In addition, the inter-gate dielectric layer 430 is located between the gate coupling layer 432 and the extension 120e of the floating gate 120 and may not cover or partially cover the spacers 126 around the extension 120e of the floating gate 120 . Furthermore, since the gate coupling layer 432 is stacked on the extension portion 120e of the floating gate 120 and does not completely cover the extension portion 120e of the floating gate 120 and its surrounding spacers 126 and the isolation structure 104, the metal silicide is The material layer 450 may selectively cover the top surface of the stack structure, and may not (or only partially) extend over the spacers 126 surrounding the stack structure.

In some embodiments, the control gate 434 includes a conductive plug 434a and a conductive wall 434b. As shown in FIG. 4A , the conductive plug 434 a stands on the gate coupling layer 432 . As shown in FIG. 4B , in some embodiments, the conductive walls 434 b extend from the sides of the strip patterns of the comb-shaped portion CM of the floating gate 120 , and can be substantially parallel to the strip patterns. In such embodiments, the spacing between the strip patterns of the comb portion CM of the floating gate 120 may be adjusted such that the space between the strip patterns is sufficient to accommodate the conductive walls 434b. In this way, as shown in FIG. 4A , the control gate 434 can be capacitively coupled with the floating gate 120 in the vertical direction through the gate coupling layer 432 and the inter-gate dielectric layer 430 through the conductive plug 434a. On the other hand, the control gate 434 may be capacitively coupled with the floating gate 120 in the horizontal direction through the spacer 126 by the conductive wall 434b. As shown in FIG. 4A , in some embodiments, the conductive plug 434a may extend from the top surface of the metal silicide layer 450 to the top surface of the interlayer dielectric layer 154 , and the conductive wall 434b may extend from the top surface of the isolation structure 104 to the interlayer The top surface of the dielectric layer 154 . In such embodiments, the height of the conductive wall 434b is greater than the height of the conductive plug 434a. Additionally, in some embodiments, the conductive plugs 434a and the conductive walls 434b are connected to each other by additional conductive vias, conductive traces, and/or other conductive members (none of which are shown).

5A-5B are schematic cross-sectional views of some stages in the process of fabricating the semiconductor structure 400 shown in FIG. 4A.

Regarding the manufacturing process of the semiconductor structure 400 shown in FIG. 4A , steps S100 to S110 described with reference to FIG. 2 and FIGS. 3A to 3F may be performed first. Next, referring to FIG. 2 and FIG. 5A , in step S112 , a mask pattern 600 is formed on the conductor layer 302 . In subsequent steps, the mask pattern 600 will be used to define the inter-gate dielectric layer 430 and the gate coupling layer 432 . The mask pattern 600 covers the strip patterns of the comb-shaped portion CM of the floating gate 120 and extends along the strip patterns. Furthermore, the mask pattern may not (or only partially) cover the spacers 126 around these strip patterns. In some embodiments, the mask pattern 600 is a photoresist pattern, and the mask pattern 600 can be formed by a lithography process.

Referring to FIG. 2 and FIG. 5B , in step S114 , the parts of the dielectric layer 300 and the conductor layer 302 that are not covered by the mask pattern 600 are removed. The remaining portion of the dielectric layer 300 forms the inter-gate dielectric layer 430 , and the remaining portion of the conductor layer 302 forms the gate coupling layer 432 . In some embodiments, the above-mentioned removing step is accomplished by an etching process. During this etching process, the mask pattern 600 can serve as an etching mask. After the above-mentioned removing steps are completed, the mask pattern 600 can be removed. After removing the mask pattern 600, the gate coupling layer 432 is exposed. In some embodiments, the mask pattern 600 is removed by a stripping process.

Subsequently, at step S116, a metal silicide layer 450 is formed. Metal silicide layer 450 is selectively formed on floating gate 120 , gate 106 , gate 136 , gate coupling layer 432 , doped region 108 , doped region 110 , doped region 122 , doped region 138 and on the exposed surface of the doped region 140 , but may not cover the exposed surface of the isolation structure 104 . In some embodiments, the metal silicide layer 450 shown in FIG. 5B may be formed by the method of forming the metal silicide layer 150 described with reference to FIG. 3I .

Referring to FIG. 2 and FIG. 4A , in step S118 , an etch stop layer 156 and an interlayer dielectric layer 154 are formed. The etch stop layer 156 fully and conformally covers the structure shown in FIG. 5B , and the interlayer dielectric layer 154 is fully formed on the etch stop layer 156 .

Subsequently, at step S120, the conductive plugs 434a, the conductive walls 434b and the conductive plugs 152 are formed. In some embodiments, the method of forming the conductive plugs 434a, the conductive walls 434b and the conductive plugs 152 includes forming vias and trenches through the interlayer dielectric layer 154 and the etch stop layer 156, followed by a deposition process, a plating process A conductive material is filled in the through holes, or a combination thereof, to form the conductive plugs 434 a , the conductive walls 434 b and the conductive plugs 152 .

So far, the semiconductor structure 400 shown in FIG. 4A has been completed by the manufacturing method of some embodiments. Although not shown, more metallization layers and ILD layers can be formed on the ILD layer 154 subsequently, and a packaging process can be performed to form a semiconductor die.

To sum up, by arranging the gate coupling layer between the floating gate and the conductive plug of the control gate, the capacitive coupling area between the control gate and the floating gate can be increased. In some embodiments, the gate coupling layer covers the top surface and sidewalls of the floating gate, so that the control gate electrically connected to the gate coupling layer can be capacitively connected to the gate coupling layer in the vertical and horizontal directions through the gate coupling layer. coupled to the floating gate. In other embodiments, the gate coupling layer can be used to improve the capacitive coupling between the control gate and the floating gate in the vertical direction, and the control gate can further include a conductive wall extending from the side of the floating gate. In this way, the control gate can still be capacitively coupled to the floating gate in the vertical and horizontal directions.

10, 40: Memory components 100, 400: Semiconductor structure 100A: memory area 100B: Logical area 102: Substrate 104: Isolation Structure 106, 136: gate 108, 110, 122, 138, 140: doped regions 112, 142: gate dielectric layer 114, 114a, 114b, 126, 126a, 126b, 144, 144a, 144b: spacers 116, 128, 146: Lightly doped regions 120: floating gate 120e: Extensions 124: Through Dielectric Layer 130, 430: Intergate dielectric layer 132, 432: gate coupling layer 134, 434: control gate 134a, 152, 434a: conductive plugs 150, 450: metal silicide layer 154: Interlayer dielectric layer 156: Etch stop layer 300: Dielectric layer 302: Conductor layer 304, 600: mask pattern 434b: Conductive Wall AA, AA': Active area AT: access transistor BR: connecting part CM: Comb FT: floating gate transistor S100, S102, S104, S106, S108, S110, S112, S114, S116, S118, S120: Steps T: Transistor X: direction Y: direction

1A is a schematic cross-sectional view of a semiconductor structure embedded with a memory device according to some embodiments of the present disclosure. FIG. 1B is a schematic plan view of the memory device shown in FIG. 1A . 2 is a fabrication flow diagram of the semiconductor structure shown in FIG. 1A in accordance with some embodiments. 3A-3I are schematic cross-sectional views of structures at various stages during the manufacturing flow shown in FIG. 2 . 4A is a schematic cross-sectional view of a semiconductor structure embedded with a memory device according to some embodiments of the present disclosure. FIG. 4B is a schematic plan view of the memory device shown in FIG. 4A . 5A-5B are schematic cross-sectional views at some stages in the process of fabricating the semiconductor structure shown in FIG. 4A.

10: Memory Components 100: Semiconductor Structure 100A: memory area 100B: Logical area 102: Substrate 104: Isolation Structure 106, 136: gate 108, 110, 122, 138, 140: doped regions 112, 142: gate dielectric layer 114, 114a, 114b, 126, 126a, 126b, 144, 144a, 144b: spacers 116, 128, 146: Lightly doped regions 120: floating gate 120e: Extensions 124: Through Dielectric Layer 130: Intergate dielectric layer 132: gate coupling layer 134: Control gate 134a, 152: conductive plug 150: metal silicide layer 154: Interlayer dielectric layer 156: Etch stop layer AA, AA': Active area AT: access transistor CM: Comb FT: floating gate transistor T: Transistor

Claims (10)

A memory device comprising: a floating gate electrode, disposed on the substrate and having a comb-shaped portion, wherein the comb-shaped portion has a plurality of strip-shaped patterns laterally spaced apart from each other; an inter-gate dielectric layer covering the upper surface of the comb-shaped portion of the floating gate; a gate coupling layer covering the inter-gate dielectric layer; and A control gate includes a conductive plug standing on the gate coupling layer and is electrically connected to the gate coupling layer, wherein the control gate is capacitively coupled to the gate coupling layer in vertical and horizontal directions the comb portion of the floating gate. The memory device of claim 1, wherein the inter-gate dielectric layer and the gate coupling layer substantially completely cover the upper surface of the comb portion of the floating gate. The memory device of claim 1, further comprising a metal silicide layer formed on the gate coupling layer, wherein the conductive plug of the control gate is electrically connected through the metal silicide layer connected to the gate coupling layer. The memory device of claim 1, wherein the floating gate further has another portion extending over the active region of the substrate and in contact with the active region through a tunneling dielectric layer. The memory device of claim 4, further comprising an isolation structure disposed in the substrate and surrounding the active region. The memory device of claim 5, wherein the comb portion of the floating gate, the inter-gate dielectric layer, and the gate coupling layer overlap the isolation structure. The memory device of claim 1, wherein the inter-gate dielectric layer further covers sidewalls of the comb-shaped portion of the floating gate, and the gate coupling layer is further filled in the floating gate A space between the plurality of strip patterns of the comb portion of the gate is placed. The memory device of claim 1, wherein the inter-gate dielectric layer has a plurality of portions laterally spaced from each other, respectively covering the plurality of strips of the comb portion of the floating gate like pattern, and wherein the gate coupling layer also has a plurality of portions laterally spaced apart from each other, respectively covering the plurality of portions of the inter-gate dielectric layer. The memory device of claim 8, wherein the control gate further comprises at least one conductive wall extending between adjacent strip patterns of the comb-shaped portion of the floating gate. A method of manufacturing a memory device, comprising: forming a floating gate over the substrate, wherein the floating gate has a comb portion, and the comb portion has a plurality of stripe patterns laterally spaced from each other; forming an inter-gate dielectric layer on the comb-shaped portion of the floating gate; forming a gate coupling layer on the inter-gate dielectric layer; and A control gate is formed on the substrate, wherein the control gate includes a conductive plug standing on the gate coupling layer and is electrically connected to the gate coupling layer, and wherein the control gate is The comb portion is capacitively coupled to the floating gate in a vertical direction and a horizontal direction.

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