TWI393263B - An improved split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing - Google Patents

An improved split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing Download PDF

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TWI393263B
TWI393263B TW097127416A TW97127416A TWI393263B TW I393263 B TWI393263 B TW I393263B TW 097127416 A TW097127416 A TW 097127416A TW 97127416 A TW97127416 A TW 97127416A TW I393263 B TWI393263 B TW I393263B
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gate
region
floating gate
floating
length
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TW200917495A (en
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Xian Liu
Amitay Levi
Alexander Kotov
Yuri Tkachev
Viktor Markov
James Yingbo Jia
Chien-Sheng Su
Yaw Wen Hu
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Silicon Storage Tech Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

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  • Non-Volatile Memory (AREA)
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Description

具有浮動閘、控制閘、選擇閘及具有在該浮動閘上方之突出部的抹除閘之改良分裂閘極非依電性快閃記憶體晶胞、陣列及製造方法Improved split gate non-electricity flash memory cell, array and manufacturing method with floating gate, control gate, selection gate and erasing gate with protruding portion above the floating gate 發明領域Field of invention

本發明是關於具有選擇閘、浮動閘、控制閘及具有與該浮動閘呈某一尺寸比的突出部的抹除閘之非依電性快閃記憶體晶胞。本發明還關於此種快閃記憶體晶胞之陣列及製造此種晶胞與陣列的方法。The present invention relates to a non-electrical flash memory cell having a wiper, a floating gate, a control gate, and a wiper having a protrusion in a certain size ratio to the floating gate. The invention also relates to arrays of such flash memory cells and methods of making such cells and arrays.

發明背景Background of the invention

具有選擇閘、浮動閘、控制閘及抹除閘之分裂閘極非依電性快閃記憶體在該領域中是眾所周知的。例如見美國專利第6,747,310號案。具有在該浮動閘上方之突出部的抹除閘在該領域中也是眾所周知的。例如見美國專利第5,242,848號案。前述兩個揭露都在此以參照形式全部被併入本文。Split gate non-electrical flash memories having select gates, floating gates, control gates, and erase gates are well known in the art. See, for example, U.S. Patent No. 6,747,310. A wiper having a projection above the floating gate is also well known in the art. See, for example, U.S. Patent No. 5,242,848. Both of the foregoing disclosures are hereby incorporated by reference in their entirety.

在此以前，先前技術不能教示或揭露在某種限制之內的抹除閘對浮動閘的突出部提高抹除效率。Prior to this, prior art techniques have not been taught or disclosed that the wiper within certain limits increases the erasing efficiency of the projections of the floating gate.

因此，本發明的目的之一是藉由在抹除閘與浮動閘之間的某一尺寸關係來提高這樣一晶胞的抹除效率。Accordingly, one of the objects of the present invention is to improve the erasing efficiency of such a unit cell by a certain dimensional relationship between the erase gate and the floating gate.

發明概要Summary of invention

在本發明中，一分裂閘極非依電性記憶體晶胞在一第一導電型的一實質上單晶基體中被製造，該晶胞具有一第二導電型的一第一區域、該第二導電型的一第二區域、及 該基體中的該第一區域與第二區域之間的一通道區。該晶胞具有與該通道區的一第一部分絕緣且隔離的一選擇閘。該晶胞進一步具有與該通道區的一第二部分絕緣且隔離的一浮動閘。該浮動閘具有離該選擇閘最近的一第一端及離該選擇閘最遠的一第二端。一抹除閘與該基體絕緣且隔離，且最接近該浮動閘的該第二端。一控制閘與該浮動閘、該選擇閘及該抹除閘絕緣且隔離，且位於該浮動閘上方，且在該抹除閘與該選擇閘之間。該抹除閘進一步具有兩個電氣連接部分：與該浮動閘的該第二端橫向相鄰且絕緣的一第一部分，及覆蓋在該浮動閘上方且與該浮動閘絕緣且與該控制閘相鄰的一第二部分。該抹除閘的該第二部分與該浮動閘隔著一第一長度，該第一長度是在實質上垂直於從該第一區域到該第二區域的方向的一方向上量測的。該抹除閘的該第二部分具有離該控制閘最近的一端，及該抹除閘的該第一部分具有離該浮動閘最近的一端，該抹除閘的該第二部分覆蓋在該浮動閘上方一第二長度處，該第二長度是在實質上垂直於該第一長度方向的一方向上從該抹除閘之離該控制閘最近的該第二部分的該端到該抹除閘之離該浮動閘最近的該第一部分的該端量測的。最後，該第二長度與該第一長度的比大約在1.0與2.5之間。In the present invention, a split gate non-electric memory cell is fabricated in a substantially single crystal substrate of a first conductivity type, the cell having a first region of a second conductivity type, a second region of the second conductivity type, and a channel region between the first region and the second region in the substrate. The unit cell has a select gate that is insulated and isolated from a first portion of the channel region. The unit cell further has a floating gate insulated from and isolated from a second portion of the channel region. The floating gate has a first end closest to the selection gate and a second end farthest from the selection gate. A wiper is insulated from and isolated from the substrate and is closest to the second end of the floating gate. A control gate is insulated from and isolated from the floating gate, the selection gate and the erase gate, and is located above the floating gate and between the erase gate and the selection gate. The wiper gate further has two electrical connection portions: a first portion laterally adjacent to the second end of the floating gate and insulated, and covering the floating gate and insulated from the floating gate and connected to the control gate A second part of the neighborhood. The second portion of the wiper is spaced from the floating gate by a first length, the first length being measured in a direction substantially perpendicular to a direction from the first region to the second region. The second portion of the erasing gate has an end closest to the control gate, and the first portion of the erasing gate has an end closest to the floating gate, the second portion of the erasing gate covering the floating gate At a second length above, the second length is in a direction substantially perpendicular to the first length direction from the end of the second portion of the erase gate closest to the control gate to the wiper gate The end of the first portion closest to the floating gate is measured. Finally, the ratio of the second length to the first length is between about 1.0 and 2.5.

本發明還關於前述記憶體晶胞的一陣列。The invention also relates to an array of the aforementioned memory cells.

圖式簡單說明Simple illustration

第1A圖是本發明的一改良非依電性記憶體晶胞的一橫截面圖。Figure 1A is a cross-sectional view of a modified non-electric memory cell of the present invention.

第1B圖是第1A圖中所顯示的該晶胞的一部分的一放大圖，其中抹除閘的突出部與浮動閘之間的尺寸關係被較詳細地顯示。Fig. 1B is an enlarged view of a portion of the unit cell shown in Fig. 1A, in which the dimensional relationship between the projection of the erase gate and the floating gate is shown in more detail.

第2圖是顯示藉由本發明的改良晶胞改良抹除效率的一圖形。Fig. 2 is a graph showing the improvement of the erasing efficiency by the improved unit cell of the present invention.

第3(A－L)圖是製造本發明的記憶體晶胞的一實施例的一製程的橫截面圖。The third (A-L) diagram is a cross-sectional view of a process for fabricating an embodiment of the memory cell of the present invention.

第4(A－L)圖是製造本發明的記憶體晶胞的另一實施例的另一製程的橫截面圖。The fourth (A-L) diagram is a cross-sectional view of another process for fabricating another embodiment of the memory cell of the present invention.

較佳實施例之詳細說明Detailed description of the preferred embodiment

參見第1A圖，顯示的是本發明的一改良非依電性記憶體晶胞10的一橫截面圖。該記憶體晶胞10在P導電型之一實質上單晶基體12(諸如單晶矽)中被製造。在該基體12裏面是一第二導電型的一第一區域14。如果該第一導電型是P型，則該第二導電型是N型。與該第一區域隔離的是該第二導電型的一第二區域16。在該第一區域14與該第二區域16之間是一通道區18，該通道區18提供在該第一區域14與該第二區域16之間的電荷的傳導。Referring to Figure 1A, a cross-sectional view of a modified non-electric memory cell unit 10 of the present invention is shown. The memory cell 10 is fabricated in one of the P conductive types substantially single crystal substrate 12, such as a single crystal germanium. Inside the substrate 12 is a first region 14 of a second conductivity type. If the first conductivity type is a P type, the second conductivity type is an N type. Isolated from the first region is a second region 16 of the second conductivity type. Between the first region 14 and the second region 16 is a channel region 18 that provides conduction of electrical charge between the first region 14 and the second region 16.

位於該基體12上方，且與該基體12隔離且絕緣的是一選擇閘20，也被稱為字線20。該選擇閘20位於該通道區18的一第一部分上方。該通道區18的該第一部分直接鄰接該第一區域14。因此，該選擇閘20與該第一區域14具有少的或沒有重疊。一浮動閘22也位於該基體12上方，且與該基 體12隔離且絕緣。該浮動閘22位於該通道區18的一第二部分及該第二區域16的一部分上方。該通道區18的該第二部分不同於該通道區18的該第一部分。因此，該浮動閘22與該選擇閘20橫向隔離且絕緣，且相鄰於該選擇閘20。一抹除閘24位於該第二區域16上方且與該第二區域16隔離，且與該基體12絕緣。該抹除閘24與該浮動閘22橫向絕緣且隔離。該選擇閘20在該浮動閘22的一側，及該抹除閘24在該浮動閘22的另一側。最後，位於該浮動閘22上方且與其絕緣且隔離的是一控制閘26。該控制閘26與該抹除閘24及該選擇閘20絕緣且隔離，且位於該抹除閘24及該選擇閘20之間。因此，到目前為止，該記憶體晶胞10的前述描述被揭露在美國專利第6,747,310號案中。Located above the substrate 12 and isolated from and insulated from the substrate 12 is a select gate 20, also referred to as a word line 20. The selector gate 20 is located above a first portion of the channel region 18. The first portion of the passage region 18 directly adjoins the first region 14. Thus, the selector gate 20 has little or no overlap with the first region 14. A floating gate 22 is also located above the substrate 12, and the base Body 12 is isolated and insulated. The floating gate 22 is located above a second portion of the channel region 18 and a portion of the second region 16. The second portion of the passage region 18 is different from the first portion of the passage region 18. Therefore, the floating gate 22 is laterally isolated and insulated from the selection gate 20 and adjacent to the selection gate 20. A wiper 24 is located above and spaced from the second region 16 and is insulated from the substrate 12. The wiper gate 24 is laterally insulated and isolated from the floating gate 22. The selector gate 20 is on one side of the floating gate 22 and the wiper gate 24 is on the other side of the floating gate 22. Finally, a control gate 26 is located above and insulated from and isolated from the floating gate 22. The control gate 26 is insulated and isolated from the erase gate 24 and the selection gate 20 and is located between the erase gate 24 and the selection gate 20. Thus, the foregoing description of the memory cell 10 has been disclosed in the U.S. Patent No. 6,747,310.

在本發明的改良中，該抹除閘24具有突出於該浮動閘22之上的一部分。這被較詳細地顯示在第1B圖中。該抹除閘24由被電氣連接的兩個部分組成。在較佳實施例中，該兩個部分形成一單石結構，雖然在本發明之內該兩個部分可以是分離的部分且可以被電氣連接。該抹除閘24的一第一部分與該浮動閘22直接橫向相鄰，且在該第二區域16上方。該抹除閘24的該第一部分具有離該浮動閘22最近的一端32。該抹除閘24的第二部分與該控制閘26橫向相鄰，且突出於該浮動閘22的一部分之上。該抹除閘的該第二部分具有離該控制閘26最近的一端34。該端34與該端32之間的水平距離(如該第一區域14與該第二區域16之間的一方向上所量測的)被稱為“EG Overhang”，如在第1B圖中所顯 示。該抹除閘24之與該控制閘26橫向相鄰且突出於該浮動閘22之上的該第二部分還與該浮動閘22垂直隔離。該浮動閘22與該抹除閘24的該第二部分之間的垂直距離，如在該“垂直”方向上所量測的，被稱為“Tox”，如在第1B圖中所顯示。該垂直距離“Tox”是在實質上垂直于該水平距離“EG Overhang”的一方向上量測的。In a refinement of the invention, the wiper gate 24 has a portion that protrudes above the floating gate 22. This is shown in more detail in Figure 1B. The wiper gate 24 consists of two parts that are electrically connected. In the preferred embodiment, the two portions form a monolithic structure, although within the present invention the two portions may be separate portions and may be electrically connected. A first portion of the wiper gate 24 is directly laterally adjacent to the floating gate 22 and above the second region 16. The first portion of the wiper gate 24 has an end 32 that is closest to the floating gate 22. The second portion of the wiper gate 24 is laterally adjacent to the control gate 26 and protrudes over a portion of the float gate 22. The second portion of the wiper has an end 34 that is closest to the control gate 26. The horizontal distance between the end 34 and the end 32 (as measured in the direction between the first region 14 and the second region 16) is referred to as "EG Overhang", as in Figure 1B. Display Show. The second portion of the wiper gate 24 that is laterally adjacent to the control gate 26 and protrudes above the floating gate 22 is also vertically isolated from the floating gate 22. The vertical distance between the floating gate 22 and the second portion of the erase gate 24, as measured in the "vertical" direction, is referred to as "Tox" as shown in Figure 1B. The vertical distance "Tox" is measured in a direction substantially perpendicular to the horizontal distance "EG Overhang".

如在美國專利第6,747,310號案中所描述，該記憶體晶胞10藉由透過Fowler－Nordheim機制從該浮動閘22穿隧到該抹除閘的電子來抹除。而且，為了改良抹除機制，該浮動閘22可以具有離該抹除閘24最近的一尖稜角以在抹除期間增強局部電場且接著增強從該浮動閘22的該稜角到該抹除閘24的電子流。已被發現的是，當“EG Overhang”與“Tox”之比大約在1.0與2.5之間時，抹除效率被提高。這被顯示在第2圖中，參見第2圖，顯示的是作為“EG Overhang”/“Tox”之比的函數的FTV、CR、及Verase的一圖形30。Verase是在抹除操作期間施加給該抹除閘24的電壓，該抹除操作可以充分地抹除該晶胞到“1”狀態。Verase＝(FTV＋QFG /Ctotal )/(1－CR)。Ctotal 是該浮動閘22與所有周圍節點之間的總電容。CR是該抹除閘24與該浮動閘22之間的偶合比率。CR＝CEG－FG /Ctotal ，這裏CEG－FG 是該抹除閘24與該浮動閘22之間的電容。QFG 是對應於“1”狀態的該浮動閘上的淨電荷。FTV是用以抹除該晶胞到“1”狀態所需的該抹除閘24與該浮動閘22之間的電壓差。當“EG Overhang”明顯小於“Tox”時，與浮動閘22的該稜角相鄰的隧道氧化物中的電子穿隧 障壁(tunneling barrier)被電氣地暴露於附近的耦合閘26的較低電位，導致FTV的增加，且接著導致Verase的增加。當“EG Overhang”明顯大於“Tox”時，CR被增加，其接著也增加Verase。如在第2圖中所顯示，該圖形30顯示當“EG Overhang”/“Tox”大約在1.6處時Verase的一最小值。隨著Verase需求被減少，對電荷幫浦的需求同樣地被減少。因此，抹除效率被提高。The memory cell 10 is erased by tunneling the floating gate 22 to the eraser electrons through a Fowler-Nordheim mechanism as described in U.S. Patent No. 6,747,310. Moreover, to improve the erasing mechanism, the floating gate 22 can have a sharper corner closest to the erasing gate 24 to enhance the local electric field during erasing and then enhance the corner from the floating gate 22 to the erasing gate 24 The flow of electrons. It has been found that when the ratio of "EG Overhang" to "Tox" is between about 1.0 and 2.5, the erasing efficiency is improved. This is shown in Figure 2, see Figure 2, which shows a graph 30 of FTV, CR, and Verase as a function of the ratio of "EG Overhang" / "Tox". Verase is the voltage applied to the erase gate 24 during the erase operation, which erases the cell to the "1" state. Verase=(FTV+Q FG /C total )/(1-CR). C total is the total capacitance between the floating gate 22 and all surrounding nodes. CR is the coupling ratio between the erase gate 24 and the floating gate 22. CR = C EG - FG / C total , where C EG - FG is the capacitance between the erase gate 24 and the floating gate 22. Q FG is the net charge on the floating gate corresponding to the "1" state. The FTV is the voltage difference between the wiper gate 24 and the floating gate 22 required to erase the cell to the "1" state. When "EG Overhang" is significantly smaller than "Tox", the electron tunneling barrier in the tunnel oxide adjacent to the corner of the floating gate 22 is electrically exposed to the lower potential of the nearby coupling gate 26, This leads to an increase in FTV and then to an increase in Verase. When "EG Overhang" is significantly larger than "Tox", CR is increased, which in turn increases Verase. As shown in Fig. 2, the graph 30 shows a minimum value of Verase when "EG Overhang" / "Tox" is approximately at 1.6. As Verase requirements are reduced, the demand for charge pumps is likewise reduced. Therefore, the erasing efficiency is improved.

這裡有本發明的該記憶體晶胞10的兩個實施例。該記憶體晶胞10的該選擇閘20與該浮動閘被一絕緣區W1分離。在該記憶體晶胞10的第一實施例中，該區域W1是二氧化矽。這被稱為該晶胞10選項A。在該記憶體晶胞10的第二實施例中，該區域W1是包含二氧化矽、氮化矽及二氧化矽的一複合層，且這實施例被稱為該晶胞10選項B。There are two embodiments of the memory cell 10 of the present invention. The selection gate 20 of the memory cell 10 is separated from the floating gate by an insulating region W1. In the first embodiment of the memory cell 10, the region W1 is cerium oxide. This is called the unit cell option A. In a second embodiment of the memory cell 10, the region W1 is a composite layer comprising hafnium oxide, hafnium nitride and hafnium oxide, and this embodiment is referred to as the cell cell 10 option B.

參見第3(A－L)圖，顯示的是製造本發明的一晶胞10選項A的製程中的步驟的橫截面圖。以第3A圖開始，顯示的是在該P型單晶矽基體12上的一二氧化矽層40的形成。對於90 nm(或120 nm)製程而言，該二氧化矽層40在80－100埃的等級上。之後，一第一多晶矽(或非晶矽)層42被沉積或形成在該二氧化矽層40上。再一次為了達到説明該90 nm製程的目的，該第一多晶矽層42在300－800埃的等級上。隨後該第一多晶矽層42在垂直於該選擇閘20的一方向上被圖案化。Referring to Figure 3(A-L), there is shown a cross-sectional view of the steps in the process of making a cell 10 option A of the present invention. Starting from Fig. 3A, the formation of a cerium oxide layer 40 on the P-type single crystal germanium substrate 12 is shown. For the 90 nm (or 120 nm) process, the ceria layer 40 is on the order of 80-100 angstroms. Thereafter, a first polysilicon (or amorphous germanium) layer 42 is deposited or formed on the germanium dioxide layer 40. Again for the purpose of illustrating the 90 nm process, the first polysilicon layer 42 is on the order of 300-800 angstroms. The first polysilicon layer 42 is then patterned in a direction perpendicular to the selection gate 20.

參見第3B圖，顯示的是製造本發明的該晶胞10選項A的製程中的接下去的步驟的一橫截面圖。另一絕緣層44，諸如二氧化矽(或甚至諸如ONO之複合層)，被沉積或形成 在該第一多晶矽層42上。根據材料是否是二氧化矽或ONO而定，該層44可以在100－200埃的等級上。然後，一第二多晶矽層46被沉積或形成在該層44上。該第二多晶矽層46在500－4000埃厚的等級上。另一絕緣體層48被沉積或形成在該第二多晶矽層46上，且在隨後的干式蝕刻期間作為一硬質遮罩被使用。在較佳實施例中，該層48是包含氮化矽48a、二氧化矽48b及氮化矽48c的一複合層。在該90 nm製程的較佳實施例中，層48a的尺寸是200－600埃，層48b的尺寸是200－600埃及層48c的尺寸是500－3000埃。Referring to Figure 3B, there is shown a cross-sectional view of the subsequent steps in the process of making the unit cell option A of the present invention. Another insulating layer 44, such as hafnium oxide (or even a composite layer such as ONO), is deposited or formed On the first polysilicon layer 42. Depending on whether the material is cerium oxide or ONO, the layer 44 can be on the order of 100-200 angstroms. A second polysilicon layer 46 is then deposited or formed on the layer 44. The second polysilicon layer 46 is on the order of 500-4000 angstroms thick. Another insulator layer 48 is deposited or formed on the second polysilicon layer 46 and used as a hard mask during subsequent dry etching. In a preferred embodiment, the layer 48 is a composite layer comprising tantalum nitride 48a, hafnium oxide 48b, and tantalum nitride 48c. In the preferred embodiment of the 90 nm process, layer 48a has a size of 200-600 angstroms and layer 48b has a size of 200-600. The layer of 48c has a size of 500-3000 angstroms.

參見第3C圖，顯示的是在製造本發明的該晶胞10選項A的製程中的接下去的步驟的一橫截面圖。光阻材料(未顯示出)被沉積在第3B圖中所顯示的結構上，且一遮罩步驟被執行，暴露該光阻材料的已選定部分。該光阻被形成，及使用該光阻作為一遮罩，該結構被蝕刻。接著，該複合層48、該第二多晶矽層46、該絕緣層44被異向性蝕刻，直到該第一多晶矽層42被暴露。由此產生的結構被顯示在第3C圖中。雖然只有兩個“堆疊”S1及S2被顯示，但是應該清楚的是這裏有許多彼此分離的此種“堆疊”。Referring to Figure 3C, there is shown a cross-sectional view of the next step in the process of making the unit cell option A of the present invention. A photoresist material (not shown) is deposited on the structure shown in Figure 3B, and a masking step is performed to expose selected portions of the photoresist material. The photoresist is formed and the photoresist is used as a mask, and the structure is etched. Next, the composite layer 48, the second polysilicon layer 46, and the insulating layer 44 are anisotropically etched until the first polysilicon layer 42 is exposed. The resulting structure is shown in Figure 3C. Although only two "stacks" S1 and S2 are shown, it should be clear that there are many such "stacks" separated from one another.

參見第3D圖，顯示的是製造本發明的該晶胞10選項A的製程中的接下去的步驟的一橫截面圖。二氧化矽49被沉積或形成在該結構上。緊接著是氮化矽層50的沉積。該二氧化矽49及氮化矽50被異向性蝕刻，在該等堆疊S1及S2的每一個周圍留下一隔片51(其是該二氧化矽49及該氮化矽50的組合)。由此產生的結構被顯示在第3D圖中。Referring to Figure 3D, there is shown a cross-sectional view of the next step in the process of making the unit cell option A of the present invention. Cerium oxide 49 is deposited or formed on the structure. This is followed by the deposition of the tantalum nitride layer 50. The cerium oxide 49 and the cerium nitride 50 are anisotropically etched, leaving a spacer 51 (which is a combination of the cerium oxide 49 and the tantalum nitride 50) around each of the stacks S1 and S2. . The resulting structure is shown in the 3D map.

參見第3E圖，顯示的是製造本發明的該晶胞10選項A的製程中的接下去的步驟的一橫截面圖。一光阻遮罩被形成在該等堆疊S1及S2與其他交替對堆疊之間的區域上方。為達到討論目的，在該等堆疊S1及S2之間的區域將被稱為“內部區域”，及沒被該光阻覆蓋的區域將被稱為“外部區域”。該等外部區域中的該暴露的第一多晶矽42被異向性蝕刻。該氧化層40同樣地被異向性蝕刻。由此產生的結構被顯示在第3E圖中。Referring to Figure 3E, there is shown a cross-sectional view of the next step in the process of making the unit cell option A of the present invention. A photoresist mask is formed over the area between the stacks S1 and S2 and the other alternating pairs of stacks. For purposes of discussion, the area between the stacks S1 and S2 will be referred to as the "internal area" and the area not covered by the photoresist will be referred to as the "outer area." The exposed first polysilicon 42 in the outer regions is anisotropically etched. This oxide layer 40 is likewise anisotropically etched. The resulting structure is shown in Figure 3E.

參見第3F圖，顯示的是製造本發明的該晶胞10選項A的製程中的接下去的步驟的一橫截面圖。該光阻材料從在第3E圖中所顯示的該結構中被移除。然後，一氧化層52被沉積或形成。然後，該氧化層52經歷一異向性蝕刻，留下與該等堆疊S1及S2相鄰的隔片52。由此形成的結構被顯示在第3F圖中。Referring to Figure 3F, there is shown a cross-sectional view of the subsequent steps in the process of making the unit cell option A of the present invention. The photoresist material is removed from the structure shown in Figure 3E. An oxide layer 52 is then deposited or formed. The oxide layer 52 then undergoes an anisotropic etch, leaving spacers 52 adjacent the stacks S1 and S2. The structure thus formed is shown in Fig. 3F.

參見第3G圖，顯示的是製造本發明的該晶胞10選項A的製程中的接下去的步驟的一橫截面圖。然後，光阻材料被沉積及被遮罩，在該等堆疊S1及S2之間的該等內部區域中留下開口。此外，與在第3E圖中所顯示的圖式相似，該光阻在其他交替對堆疊之間。該等堆疊S1及S2(及其他交替對堆疊)之間的該等內部區域中的該多晶矽42被異向性蝕刻。在該多晶矽42之下的該二氧化矽層40也可以被異向性蝕刻。由此產生的結構經歷一高電壓離子植入，形成該等第二區域16。由此產生的結構被顯示在第3G圖中。Referring to Figure 3G, there is shown a cross-sectional view of the next step in the process of making the unit cell option A of the present invention. The photoresist material is then deposited and masked leaving an opening in the interior regions between the stacks S1 and S2. Moreover, similar to the pattern shown in Figure 3E, the photoresist is between other alternating pairs of stacks. The polysilicon 42 in the inner regions between the stacks S1 and S2 (and other alternating pairs) is anisotropically etched. The ceria layer 40 under the polysilicon 42 can also be anisotropically etched. The resulting structure undergoes a high voltage ion implantation to form the second regions 16. The resulting structure is shown in the 3G map.

參見第3H圖，顯示的是製造本發明的該晶胞10選項A 的製程中的接下去的步驟的一橫截面圖。藉由例如一濕式蝕刻或一干式等向性蝕刻，該內部區域中與該等堆疊S1及S2相鄰的該氧化物隔片52被移除。由此產生的結構被顯示在第3H圖中。Referring to Figure 3H, it is shown that the unit cell 10 option A of the present invention is fabricated. A cross-sectional view of the next step in the process. The oxide spacer 52 in the inner region adjacent to the stacks S1 and S2 is removed by, for example, a wet etch or a dry isotropic etch. The resulting structure is shown in Figure 3H.

參見第3I圖，顯示的是製造本發明的該晶胞10選項A的製程中的接下去的步驟的一橫截面圖。在該等堆疊S1及S2的該等外部區域中的該光阻材料被移除。二氧化矽54被到處沉積或形成。由此產生的結構被顯示在第3I圖中。Referring to Figure 3I, there is shown a cross-sectional view of the subsequent steps in the process of making the unit cell option A of the present invention. The photoresist material in the outer regions of the stacks S1 and S2 is removed. The cerium oxide 54 is deposited or formed everywhere. The resulting structure is shown in Figure 3I.

參見第3J圖，顯示的是製造本發明的該晶胞10選項A的製程中的接下去的步驟的一橫截面圖。該結構再次被光阻材料覆蓋，且一遮罩步驟被執行，暴露該等堆疊S1及S2的該等外部區域及讓光阻材料覆蓋該等堆疊S1及S2之間的該內部區域。一氧化物異向性蝕刻被執行以減小在該等堆疊S1及S2的該等外部區域中的該隔片54的厚度，及從該等外部區域中的該暴露的矽基體12中完全移除二氧化矽。由此產生的結構被顯示在第3J圖中。Referring to Figure 3J, there is shown a cross-sectional view of the subsequent steps in the process of making the unit cell option A of the present invention. The structure is again covered by the photoresist material, and a masking step is performed exposing the outer regions of the stacks S1 and S2 and allowing the photoresist material to cover the inner region between the stacks S1 and S2. An oxide anisotropic etch is performed to reduce the thickness of the spacers 54 in the outer regions of the stacks S1 and S2 and to completely shift from the exposed ruthenium substrate 12 in the outer regions In addition to cerium oxide. The resulting structure is shown in Figure 3J.

參見第3K圖，顯示的是製造本發明的該晶胞10選項A的製程中的接下去的步驟的一橫截面圖。在20－100埃等級上的二氧化矽薄層56被形成在該結構上。這氧化層56是該選擇閘與該基體12之間的閘極氧化物。由此產生的結構被顯示在第3K圖中。Referring to Figure 3K, there is shown a cross-sectional view of the next step in the process of making the unit cell option A of the present invention. A thin layer 56 of ruthenium dioxide on the order of 20-100 angstroms is formed on the structure. This oxide layer 56 is the gate oxide between the selection gate and the substrate 12. The resulting structure is shown in Figure 3K.

參見第3L圖，顯示的是製造本發明的該晶胞10選項A的製程中的接下去的步驟的一橫截面圖。多晶矽60被到處沉積。然後，該多晶矽層60經歷一異向性蝕刻，在該等堆 疊S1及S2的該等外部區域中形成隔片，其等形成共用一共用第二區域16的彼此相鄰的兩個記憶體晶胞10的該等選擇閘20。另外，在該等堆疊S1及S2的該等內部區域內的該等隔片被合併在一起形成一單一抹除閘24，該單一抹除閘24被該兩個記憶體晶胞10共用。一絕緣體層62被沉積在該結構上，且被異向性蝕刻以形成緊鄰該等選擇閘20的隔片62。在較佳實施例中，絕緣體62是包含二氧化矽及氮化矽的一複合層。之後，一離子植入步驟被執行，形成該等第一區域14。在另一側上的各該記憶體晶胞共用一共用第一區域14。隨後，絕緣體及金屬化層被沉積且被圖樣化以形成位元線70及位元線接點72。Referring to Figure 3L, there is shown a cross-sectional view of the next step in the process of making the unit cell option A of the present invention. The polysilicon 60 is deposited everywhere. The polysilicon layer 60 then undergoes an anisotropic etch in the stack The spacers are formed in the outer regions of the stacks S1 and S2, which form the select gates 20 of the two memory cells 10 adjacent to each other sharing a common second region 16. Additionally, the spacers in the interior regions of the stacks S1 and S2 are combined to form a single wiper gate 24 that is shared by the two memory cells 10. An insulator layer 62 is deposited over the structure and is anisotropically etched to form spacers 62 proximate the select gates 20. In a preferred embodiment, insulator 62 is a composite layer comprising hafnium oxide and tantalum nitride. Thereafter, an ion implantation step is performed to form the first regions 14. Each of the memory cells on the other side shares a common first region 14. Subsequently, the insulator and metallization layer are deposited and patterned to form bit line 70 and bit line contact 72.

參見第4(A－L)圖，顯示的是製造本發明的一晶胞10選項B的製程中的步驟的橫截面圖。以下提出的步驟及描述與以上對於形成第3(A－L)圖中所顯示及描述的該等記憶體晶胞10選項A的方法的步驟及描述相似。因此，同樣的數字將被用於同樣的部分。以第4A圖開始，顯示的是在P型單晶矽的該基體12上的一二氧化矽層40的形成。對於90 nm製程而言，該二氧化矽層40在80－100埃的等級上。之後，一第一多晶矽(或非晶矽)層42被沉積或形成在該二氧化矽層40上。再一次為了達到説明該90 nm製程的目的，該第一多晶矽層42在400－800埃的等級上。隨後該第一多晶矽層42在垂直於該選擇閘20的一方向上被圖案化。Referring to Fig. 4(A-L), there is shown a cross-sectional view of the steps in the process of making a cell 10 option B of the present invention. The steps and descriptions set forth below are similar to the steps and description of the above method for forming the memory cell 10 option A shown and described in the third (A-L) diagram. Therefore, the same numbers will be used for the same part. Starting from Fig. 4A, the formation of a cerium oxide layer 40 on the substrate 12 of a P-type single crystal germanium is shown. For the 90 nm process, the ceria layer 40 is on the order of 80-100 angstroms. Thereafter, a first polysilicon (or amorphous germanium) layer 42 is deposited or formed on the germanium dioxide layer 40. Again for the purpose of illustrating the 90 nm process, the first polysilicon layer 42 is on the order of 400-800 angstroms. The first polysilicon layer 42 is then patterned in a direction perpendicular to the selection gate 20.

參見第4B圖，顯示的是製造本發明的該晶胞10選項B的製程中的接下去的步驟的一橫截面圖。另一絕緣層44， 諸如二氧化矽(或甚至諸如ONO之複合層)，被沉積或形成在該第一多晶矽層42上。根據材料是否是二氧化矽或ONO而定，該層44可以在100－200埃的等級上。然後，一第二多晶矽層46被沉積或形成在該層44上。該第二多晶矽層46在500－4000埃厚的等級上。另一絕緣體層48被沉積或形成在該第二多晶矽層46上，且在隨後的干式蝕刻期間作為一硬質遮罩被使用。在較佳實施例中，該層48是包含氮化矽48a、二氧化矽48b及氮化矽48c的一複合層。在該90 nm製程的較佳實施例中，層48a的尺寸是200－600埃；層48b的尺寸是200－600埃及層48c的尺寸是500－4000埃。Referring to Figure 4B, there is shown a cross-sectional view of the next step in the process of making the unit cell option B of the present invention. Another insulating layer 44, A layer such as germanium dioxide (or even a composite layer such as ONO) is deposited or formed on the first polysilicon layer 42. Depending on whether the material is cerium oxide or ONO, the layer 44 can be on the order of 100-200 angstroms. A second polysilicon layer 46 is then deposited or formed on the layer 44. The second polysilicon layer 46 is on the order of 500-4000 angstroms thick. Another insulator layer 48 is deposited or formed on the second polysilicon layer 46 and used as a hard mask during subsequent dry etching. In a preferred embodiment, the layer 48 is a composite layer comprising tantalum nitride 48a, hafnium oxide 48b, and tantalum nitride 48c. In the preferred embodiment of the 90 nm process, layer 48a is 200-600 angstroms in size; layer 48b is 200-600. The thickness of layer 48c is 500-4000 angstroms.

參見第4C圖，顯示的是製造本發明的該晶胞10選項B的製程中的接下去的步驟的一橫截面圖。光阻材料(未顯示出)被沉積在第4B圖中所顯示的結構上，且一遮罩步驟被執行，暴露該光阻材料的已選定部分。該光阻被形成，及使用該光阻作為一遮罩，該結構被蝕刻。接著，該複合層48、該第二多晶矽層46、該絕緣層44被異向性蝕刻，直到該第一多晶矽層42被暴露。由此產生的結構被顯示在第4C圖中。雖然只有兩個“堆疊”S1及S2被顯示，但是應該清楚的是這裏有許多彼此分離的此種“堆疊”。Referring to Figure 4C, there is shown a cross-sectional view of the next step in the process of making the unit cell option B of the present invention. A photoresist material (not shown) is deposited on the structure shown in Figure 4B, and a masking step is performed to expose selected portions of the photoresist material. The photoresist is formed and the photoresist is used as a mask, and the structure is etched. Next, the composite layer 48, the second polysilicon layer 46, and the insulating layer 44 are anisotropically etched until the first polysilicon layer 42 is exposed. The resulting structure is shown in Figure 4C. Although only two "stacks" S1 and S2 are shown, it should be clear that there are many such "stacks" separated from one another.

參見第4D圖，顯示的是製造本發明的該晶胞10選項B的製程中的接下去的步驟的一橫截面圖。一光阻遮罩被形成在該等堆疊S1及S2與其他交替對堆疊之間的區域上方。為達到討論目的，該等堆疊S1及S2之間的區域將被稱為“內部區域”，及沒被該光阻抗蝕劑覆蓋的區域將被稱為“外部 區域”。在該等外部區域中的該暴露的第一多晶矽42被異向性蝕刻。該氧化層40同樣地被異向性蝕刻。由此產生的結構被顯示在第4D圖中。Referring to Fig. 4D, there is shown a cross-sectional view of the next step in the process of making the unit cell option B of the present invention. A photoresist mask is formed over the area between the stacks S1 and S2 and the other alternating pairs of stacks. For the purposes of discussion, the area between the stacks S1 and S2 will be referred to as the "internal area" and the area not covered by the photoresist will be referred to as "external" The exposed first polysilicon 42 in the outer regions is anisotropically etched. The oxide layer 40 is likewise anisotropically etched. The resulting structure is shown in Figure 4D.

參見第4E圖，顯示的是製造本發明的該晶胞10選項B的製程中的接下去的步驟的一橫截面圖。二氧化矽49被沉積或形成在該結構上。緊接著是氮化矽層50的沉積。該二氧化矽49及氮化矽50被異向性蝕刻，在該等堆疊S1及S2的每一個周圍留下一隔片51(其是該二氧化矽49及該氮化矽50的組合)。由此產生的結構被顯示在第4E圖中。Referring to Figure 4E, there is shown a cross-sectional view of the next step in the process of making the unit cell option B of the present invention. Cerium oxide 49 is deposited or formed on the structure. This is followed by the deposition of the tantalum nitride layer 50. The cerium oxide 49 and the cerium nitride 50 are anisotropically etched, leaving a spacer 51 (which is a combination of the cerium oxide 49 and the tantalum nitride 50) around each of the stacks S1 and S2. . The resulting structure is shown in Figure 4E.

參見第4F圖，顯示的是製造本發明的該晶胞10選項B的製程中的接下去的步驟的一橫截面圖。然後，一氧化層52被沉積或形成。然後，該氧化層52經歷一異向性蝕刻，留下與該等堆疊S1及S2相鄰的隔片52。由此形成的結構被顯示在第4F圖中。Referring to Figure 4F, there is shown a cross-sectional view of the next step in the process of making the unit cell option B of the present invention. An oxide layer 52 is then deposited or formed. The oxide layer 52 then undergoes an anisotropic etch, leaving spacers 52 adjacent the stacks S1 and S2. The structure thus formed is shown in Fig. 4F.

參見第4G圖，顯示的是製造本發明的該晶胞10選項B的製程中的接下去的步驟的一橫截面圖。然後，光阻材料被沉積及被遮罩，在該等堆疊S1及S2之間的該等內部區域中留下開口。此外，該光阻在其他交替對堆疊之間。該等堆疊S1及S2(及其他交替對堆疊)之間的該等內部區域中的該多晶矽42被異向性蝕刻。該多晶矽42之下的該二氧化矽層40也可以被異向性蝕刻。由此產生的結構經歷一高電壓離子植入，形成該等第二區域16。由此產生的結構被顯示在第4G圖中。Referring to Fig. 4G, there is shown a cross-sectional view of the next step in the process of making the unit cell option B of the present invention. The photoresist material is then deposited and masked leaving an opening in the interior regions between the stacks S1 and S2. In addition, the photoresist is between the other alternating pairs of stacks. The polysilicon 42 in the inner regions between the stacks S1 and S2 (and other alternating pairs) is anisotropically etched. The ceria layer 40 under the polysilicon 42 can also be anisotropically etched. The resulting structure undergoes a high voltage ion implantation to form the second regions 16. The resulting structure is shown in Figure 4G.

參見第4H圖，顯示的是製造本發明的該晶胞10選項B 的製程中的接下去的步驟的一橫截面圖。藉由例如一濕式蝕刻或一干式等向性蝕刻，該內部區域中與該等堆疊S1及S2相鄰的該氧化物隔片52被移除。由此產生的結構被顯示在第4H圖中。Referring to Figure 4H, there is shown the option of fabricating the unit cell 10 of the present invention. A cross-sectional view of the next step in the process. The oxide spacer 52 in the inner region adjacent to the stacks S1 and S2 is removed by, for example, a wet etch or a dry isotropic etch. The resulting structure is shown in Figure 4H.

參見第4I圖，顯示的是製造本發明的該晶胞10選項B的製程中的接下去的步驟的一橫截面圖。在該等堆疊S1及S2的該等外部區域中的該光阻材料被移除。二氧化矽54被到處沉積或形成。由此產生的結構被顯示在第4I圖中。Referring to Figure 4I, there is shown a cross-sectional view of the next step in the process of making the unit cell option B of the present invention. The photoresist material in the outer regions of the stacks S1 and S2 is removed. The cerium oxide 54 is deposited or formed everywhere. The resulting structure is shown in Figure 4I.

參見第4J圖，顯示的是製造本發明的該晶胞10選項B的製程中的接下去的步驟的一橫截面圖。該結構再次被光阻材料覆蓋，且一遮罩步驟被執行，暴露該等堆疊S1及S2的該等外部區域及讓光阻材料覆蓋該等堆疊S1及S2之間的該內部區域。一氧化物異向性蝕刻被執行以減小在該等堆疊S1及S2的該等外部區域中的該氧化物隔片54的厚度，及從該等外部區域中的該暴露的矽基體12中完全移除二氧化矽。由此產生的結構被顯示在第4J圖中。Referring to Figure 4J, there is shown a cross-sectional view of the subsequent steps in the process of making the unit cell option B of the present invention. The structure is again covered by the photoresist material, and a masking step is performed exposing the outer regions of the stacks S1 and S2 and allowing the photoresist material to cover the inner region between the stacks S1 and S2. An oxide anisotropic etch is performed to reduce the thickness of the oxide spacer 54 in the outer regions of the stacks S1 and S2, and from the exposed germanium substrate 12 in the outer regions The cerium oxide is completely removed. The resulting structure is shown in Figure 4J.

參見第4K圖，顯示的是製造本發明的該晶胞10選項B的製程中的接下去的步驟的一橫截面圖。在20－100埃等級上的二氧化矽薄層56被形成在該結構上。這氧化層56是該選擇閘與該基體12之間的閘極氧化物。由此產生的結構被顯示在第4K圖中。Referring to Fig. 4K, there is shown a cross-sectional view of the next step in the process of making the unit cell option B of the present invention. A thin layer 56 of ruthenium dioxide on the order of 20-100 angstroms is formed on the structure. This oxide layer 56 is the gate oxide between the selection gate and the substrate 12. The resulting structure is shown in Figure 4K.

參見第4L圖，顯示的是製造本發明的該晶胞10選項B的製程中的接下去的步驟的一橫截面圖。多晶矽60被到處沉積。然後，該多晶矽層60經歷一異向性蝕刻，在該等堆 疊S1及S2的該等外部區域中形成隔片，其等形成共用一共用第二區域16的彼此相鄰的兩個記憶體晶胞10的該等選擇閘20。另外，該等堆疊S1及S2的該等內部區域內的該等隔片被合併在一起形成一單一抹除閘24，該單一抹除閘24被該兩個記憶體晶胞10共用。一絕緣體層62被沉積在該結構上，且被異向性蝕刻以形成緊鄰該等選擇閘20的隔片62。在較佳實施例中，絕緣體62是包含二氧化矽及氮化矽的一複合層。之後，一離子植入步驟被執行，形成該等第一區域14。在另一側上的各該記憶體晶胞共用一共用第一區域14。隨後，絕緣體及金屬化層被沉積且被圖樣化以形成位元線70及位元線接點72。Referring to Figure 4L, there is shown a cross-sectional view of the next step in the process of making the unit cell option B of the present invention. The polysilicon 60 is deposited everywhere. The polysilicon layer 60 then undergoes an anisotropic etch in the stack The spacers are formed in the outer regions of the stacks S1 and S2, which form the select gates 20 of the two memory cells 10 adjacent to each other sharing a common second region 16. Additionally, the spacers in the interior regions of the stacks S1 and S2 are combined to form a single wiper gate 24 that is shared by the two memory cells 10. An insulator layer 62 is deposited over the structure and is anisotropically etched to form spacers 62 proximate the select gates 20. In a preferred embodiment, insulator 62 is a composite layer comprising hafnium oxide and tantalum nitride. Thereafter, an ion implantation step is performed to form the first regions 14. Each of the memory cells on the other side shares a common first region 14. Subsequently, the insulator and metallization layer are deposited and patterned to form bit line 70 and bit line contact 72.

規劃、讀取及抹除的操作及較特別地，將被施加的電壓，可以與USP第6,747,310中提出的那些一樣，其全部揭露在此以參照形式被併入本文。The operations of planning, reading, and erasing, and more particularly, the voltages to be applied, may be the same as those set forth in U.S. Patent No. 6,747,310, the entire disclosure of which is incorporated herein by reference.

然而，操作條件還可以是不同的。例如，對於抹除操作而言，下面的電壓可以被施加。However, the operating conditions can also be different. For example, for an erase operation, the following voltage can be applied.

在抹除期間，在－6伏到－9伏等級上的一負電壓可以被施加給該選擇控制閘26。在那種情況下，施加給該選擇抹除閘24的電壓可以被降低到大約7－9伏。該抹除閘24的“突出部”為穿隧障壁遮蔽施加給該選擇控制閘26的負電壓。During the erase, a negative voltage on the -6 volt to -9 volt level can be applied to the select control gate 26. In that case, the voltage applied to the select erase gate 24 can be reduced to approximately 7-9 volts. The "protrusion" of the erase gate 24 shields the tunneling barrier from the negative voltage applied to the select control gate 26.

對於規劃而言，下面的電壓可以被施加。For planning, the following voltage can be applied.

在規劃期間，在通道之浮動閘下方的該部分反轉的情況下，透過有效熱電子注入，已選定的晶胞被規劃。3－6伏的中壓被施加給該選擇SL以產生該等熱電子。該選擇控制閘26及抹除閘24被加偏壓至一高電壓(6－9伏)以利用高耦合比率及使耦合到該浮動閘的電壓最大化。耦合到該浮動閘的該高電壓引起FG通道反轉及使橫向電場集結在分裂區域中，以較有效地產生熱電子。此外，該等電壓提供一高的垂直電場以吸引熱電子進入該浮動閘及減小注入能量障壁。During planning, the selected unit cell is planned through effective hot electron injection in the event that the portion below the floating gate of the channel is inverted. A medium voltage of 3-6 volts is applied to the selection SL to produce the hot electrons. The select control gate 26 and wiper gate 24 are biased to a high voltage (6-9 volts) to take advantage of the high coupling ratio and maximize the voltage coupled to the floating gate. The high voltage coupled to the floating gate causes the FG channel to reverse and cause the transverse electric field to build up in the split region to produce hot electrons more efficiently. In addition, the voltages provide a high vertical electric field to attract hot electrons into the floating gate and reduce the injected energy barrier.

對於讀取而言，下面的電壓可以被施加。For reading, the following voltage can be applied.

讀取期間，根據規劃與讀取之間的平衡而定，該選擇控制閘26及該選擇抹除閘24上的電壓可以被平衡，因為每一個都被耦接到該浮動閘。因此，施加給該選擇控制閘26及該選擇抹除閘24每一個的電壓可以是範圍從0伏到3.7伏的電壓的一組合，以達到最理想的窗。另外，因為由於RC 耦合，該選擇控制閘上的電壓是不利的，所以該選擇抹除閘24上的電壓可以產生一較快的讀取操作。During reading, depending on the balance between planning and reading, the voltages on the selection control gate 26 and the selection wiper 24 can be balanced because each is coupled to the floating gate. Thus, the voltage applied to each of the select control gate 26 and the select erase gate 24 can be a combination of voltages ranging from 0 volts to 3.7 volts to achieve the most desirable window. Also, because of the RC Coupling, the selection of the voltage on the control gate is unfavorable, so the selection of the voltage on the erase gate 24 can result in a faster read operation.

10‧‧‧改良非依電性記憶體晶胞10‧‧‧Modified non-electrical memory cell

12‧‧‧基體/矽晶體12‧‧‧Body/矽 crystal

14‧‧‧第一區域14‧‧‧First area

16‧‧‧第二區域16‧‧‧Second area

18‧‧‧通道區18‧‧‧Channel area

20‧‧‧選擇閘/字線20‧‧‧Select gate/word line

22‧‧‧浮動閘22‧‧‧Floating gate

24‧‧‧抹除閘24‧‧‧ wipe the gate

26‧‧‧控制閘/耦合閘26‧‧‧Control gate/coupling gate

30‧‧‧圖形30‧‧‧ graphics

32－34‧‧‧端32-34‧‧‧

40‧‧‧二氧化矽層/氧化層40‧‧‧2O2 layer/oxide layer

42‧‧‧第一多晶矽層/第一多晶矽42‧‧‧First polysilicon layer/first polysilicon

44‧‧‧絕緣層44‧‧‧Insulation

46‧‧‧第二多晶矽層46‧‧‧Second polysilicon layer

48‧‧‧絕緣體層/複合層48‧‧‧Insulator/Composite

48a‧‧‧氮化矽48a‧‧‧ nitride

48b‧‧‧二氧化矽48b‧‧‧2D

48c‧‧‧氮化矽48c‧‧‧ nitride

49‧‧‧二氧化矽49‧‧‧2 cerium oxide

50‧‧‧氮化矽層/氮化矽50‧‧‧ nitride layer/nitride layer

51‧‧‧隔片51‧‧‧ spacer

52‧‧‧氧化層/隔片52‧‧‧Oxide/separator

54‧‧‧二氧化矽/隔片54‧‧‧2 cerium oxide/separator

56‧‧‧二氧化矽薄層/氧化層56‧‧‧2 bismuth dioxide/oxide layer

60‧‧‧多晶矽/多晶矽層60‧‧‧Polysilicon/polycrystalline layer

62‧‧‧絕緣體層/絕緣體/隔片62‧‧‧Insulator/Insulator/Separator

70‧‧‧位元線70‧‧‧ bit line

72‧‧‧位元線接點72‧‧‧ bit line contacts

第1A圖是本發明的一改良非依電性記憶體晶胞的一橫截面圖。Figure 1A is a cross-sectional view of a modified non-electric memory cell of the present invention.

第1B圖是第1A圖中所顯示的該晶胞的一部分的一放大圖，其中抹除閘的突出部與浮動閘之間的尺寸關係被較詳細地顯示。Fig. 1B is an enlarged view of a portion of the unit cell shown in Fig. 1A, in which the dimensional relationship between the projection of the erase gate and the floating gate is shown in more detail.

第2圖是顯示藉由本發明的改良晶胞改良抹除效率的一圖形。Fig. 2 is a graph showing the improvement of the erasing efficiency by the improved unit cell of the present invention.

第3(A－L)圖是製造本發明的記憶體晶胞的一實施例的一製程的橫截面圖。The third (A-L) diagram is a cross-sectional view of a process for fabricating an embodiment of the memory cell of the present invention.

第4(A－L)圖是製造本發明的記憶體晶胞的另一實施例的另一製程的橫截面圖。The fourth (A-L) diagram is a cross-sectional view of another process for fabricating another embodiment of the memory cell of the present invention.

10‧‧‧改良非依電性記憶體晶胞10‧‧‧Modified non-electrical memory cell

12‧‧‧基體/矽晶體12‧‧‧Body/矽 crystal

14‧‧‧第一區域14‧‧‧First area

16‧‧‧第二區域16‧‧‧Second area

18‧‧‧通道區18‧‧‧Channel area

20‧‧‧選擇閘/字線20‧‧‧Select gate/word line

22‧‧‧浮動閘22‧‧‧Floating gate

24‧‧‧抹除閘24‧‧‧ wipe the gate

26‧‧‧控制閘/耦合閘26‧‧‧Control gate/coupling gate

W1‧‧‧絕緣區W1‧‧‧Insulated area

Claims (19)

一種在第一導電型的實質上單晶基體中的非依電性記憶體晶胞，其具有：一第二導電型的一第一區域、該第二導電型的一第二區域、及該基體中的該第一區域與該第二區域之間的一通道區；與該通道區的一第一部分絕緣且隔離的一選擇閘；與該通道區的一第二部分絕緣且隔離的一浮動閘；該浮動閘具有離該選擇閘最近的一第一端及離該選擇閘最遠的一第二端；與離該浮動閘的該第二端最近的該基體絕緣且隔離的一抹除閘；於該浮動閘的該第二端處之一個末端與該抹除閘之間的一穿隧障壁，在一抹除操作期間會穿越該穿隧障壁發生穿隧作用；與該浮動閘、該選擇閘及該抹除閘絕緣且隔離、且位於該浮動閘上方及在該抹除閘與該選擇閘之間的一控制閘，其中改良包含：該抹除閘具有兩個電氣連接的部分：與該浮動閘的該第二端橫向相鄰且絕緣的一第一部分，及覆蓋在該浮動閘上方且與該浮動閘絕緣且與該控制閘相鄰的一第二部分；其中該抹除閘的該第二部分與該浮動閘隔著在實質上與從該第一區域到該第二區域的方向垂直的一方向上量測到的一第一長度，並且遮蔽該穿隧障壁使之隔離於該控制閘；其中該抹除閘的該第二部分具有離該控制閘最近的一端，及該抹除閘的該第一部分具有離該浮動閘最近 的一端；其中該抹除閘的該第二部分覆蓋在該浮動閘上方一第二長度處，該第二長度是在實質上垂直於該第一長度方向的一方向上從該抹除閘之離該控制閘最近的該第二部分的該端到該抹除閘之離該浮動閘最近的該第一部分的該端量測的；及其中該第二長度與該第一長度之比大約在1.0與2.5之間。 A non-electrical memory cell in a substantially single crystal substrate of a first conductivity type, comprising: a first region of a second conductivity type, a second region of the second conductivity type, and the a channel region between the first region and the second region in the substrate; a selection gate insulated from and isolated from a first portion of the channel region; and a floating isolation and isolation from a second portion of the channel region a floating gate having a first end closest to the selection gate and a second end farthest from the selection gate; and a wiper insulated and isolated from the base closest to the second end of the floating gate a tunneling barrier between the end of the second end of the floating gate and the eraser gate, tunneling occurs through the tunnel barrier during an erasing operation; and the floating gate, the selection And a control gate that is insulated and isolated from the wiper and located above the float gate and between the wiper gate and the select gate, wherein the improvement comprises: the wiper gate has two electrically connected portions: The second end of the floating gate is laterally adjacent and insulated by a first And a second portion overlying the floating gate and insulated from the floating gate and adjacent to the control gate; wherein the second portion of the wiper is substantially separated from the floating gate a first length measured from a direction perpendicular to a direction from the first region to the second region, and shielding the tunnel barrier from the control gate; wherein the second portion of the wiper has The most proximal end of the control gate, and the first portion of the wiper has the closest to the floating gate One end of the eraser gate covering a second length above the floating gate, the second length being away from the erase gate in a direction substantially perpendicular to the first length direction The end of the second portion of the control gate closest to the end of the first portion of the erase gate that is closest to the floating gate; and wherein the ratio of the second length to the first length is approximately 1.0 Between 2.5 and 2.5. 如申請專利範圍第1項所述之非依電性記憶體晶胞，其中該抹除閘的該兩個部分被單石化地形成。 The non-electrical memory unit cell of claim 1, wherein the two portions of the erasing gate are formed monolithically. 如申請專利範圍第1項所述之非依電性記憶體晶胞，其中該抹除閘的該兩個部分是被電氣連接在一起的兩個分離的部分。 A non-electrical memory cell as described in claim 1 wherein the two portions of the eraser are two separate portions that are electrically connected together. 如申請專利範圍第2項所述之非依電性記憶體晶胞，其中該浮動閘具有一尖稜角，該稜角在該浮動閘之離該抹除閘的該第一部分最近的該第二端處。 The non-electric memory cell as described in claim 2, wherein the floating gate has a sharp corner at a second end of the floating gate that is closest to the first portion of the erase gate At the office. 如申請專利範圍第4項所述之非依電性記憶體晶胞，其中在該抹除操作期間，該稜角促進從該浮動閘到該抹除閘的電子流。 A non-electrical memory cell as described in claim 4, wherein the edge promotes electron flow from the floating gate to the eraser during the erasing operation. 如申請專利範圍第2項所述之非依電性記憶體晶胞，其中該浮動閘與該第二區域的一部分絕緣且隔離，及該抹除閘與該第二區域絕緣且隔離。 The non-electric memory cell according to claim 2, wherein the floating gate is insulated and isolated from a portion of the second region, and the erase gate is insulated and isolated from the second region. 如申請專利範圍第6項所述之非依電性記憶體晶胞，其中該通道區的該第一部分鄰接該第一區域，在該通道區 的該第一部分上方的該選擇閘與該通道區的該第一部分絕緣且隔離。 The non-electric memory cell according to claim 6, wherein the first portion of the channel region is adjacent to the first region, and the channel region The selector gate above the first portion is insulated and isolated from the first portion of the channel region. 如申請專利範圍第2項所述之非依電性記憶體晶胞，其中該選擇閘與該浮動閘的該第一端被一複合絕緣材料分離。 The non-electric memory cell according to claim 2, wherein the selection gate is separated from the first end of the floating gate by a composite insulating material. 如申請專利範圍第8項所述之非依電性記憶體晶胞，其中該複合絕緣材料是二氧化矽及氮化矽。 The non-electrical memory unit cell according to claim 8, wherein the composite insulating material is cerium oxide and cerium nitride. 如申請專利範圍第2項所述之非依電性記憶體晶胞，其中該選擇閘與該浮動閘的該第一端被一均質絕緣材料分離。 The non-electric memory cell according to claim 2, wherein the selection gate is separated from the first end of the floating gate by a homogeneous insulating material. 如申請專利範圍第10項所述之非依電性記憶體晶胞，其中該均質絕緣材料是二氧化矽。 The non-electrical memory unit cell according to claim 10, wherein the homogeneous insulating material is cerium oxide. 一種製造非依電性記憶體晶胞陣列的方法，其包含：在一第一導電型的基體中形成一第二導電型的數個第一區域與第二區域，該第二區域和第一區域相隔離；在該第一區域的對面於該基體之上形成多對成疊對的控制閘與浮動閘，每個成疊對具有一控制閘位置在一浮動閘上方，浮動閘位於該基體上方，該浮動閘與控制閘各具有從該第一區域到該第二區域的一方向量測的一長度，及該控制閘具有小於該浮動閘之該長度的一長度，最接近該第一區域的每個浮動閘具有一未被該控制閘覆蓋於上方的暴露部分，並且有一末端；在一成疊對的控制閘與浮動閘之間於該基體上在第一區域之上形成一抹除閘，該抹除閘有兩個部分：一第 一部分在該等浮動閘的暴露部分間且與該浮動閘的末端藉由一穿隧障壁予以絕緣，電荷在抹除操作期間會穿隧通過該穿隧障壁，且具有一離該浮動閘最近的一第一端；與一第二部分電氣連接於該第一部分，該第二部分在該浮動閘的該暴露部分的上方且與該浮動閘的末端藉由該穿隧障壁絕緣，來屏蔽該穿隧障壁使之隔離於該控制閘，其中該抹除閘的該第二部分與該浮動閘隔著一第一長度，該第一長度是在實質上垂直於長度方向的一方向上量測的；該第二部分具有離該控制閘最近的一第一端，該抹除閘的該第二部分具有一第二長度，該第二長度係從該抹除閘之該第二部分的該第一端至對齊於該抹除閘之該第一部分的該第一端之一垂直線在實質上平行於該長度方向的一方向上量測的；其中該第二長度與該第一長度之比在大約1.0與2.5之間；在該成疊對的控制閘與浮動閘與該第二區域之間在該基體之上形成選擇閘。 A method of fabricating a non-electrical memory cell array, comprising: forming a plurality of first and second regions of a second conductivity type in a first conductivity type substrate, the second region and the first The region is isolated; a plurality of pairs of control gates and floating gates are formed on the opposite side of the first region, each of the stacked pairs having a control gate position above a floating gate, and the floating gate is located at the substrate Upper, the floating gate and the control gate each have a length measured from a first area to a second area of the second area, and the control gate has a length smaller than the length of the floating gate, closest to the first Each of the floating gates of the region has an exposed portion that is not covered by the control gate, and has an end; an eraser is formed on the substrate between the first region and the floating gate between the stack of control gates and the floating gate Gate, the wiper has two parts: one A portion is insulated between the exposed portions of the floating gates and the end of the floating gate by a tunneling barrier, and the charge tunnels through the tunneling barrier during the erasing operation and has a closest to the floating gate a first end; and a second portion electrically connected to the first portion, the second portion being shielded from the exposed portion of the floating gate and insulated from the end of the floating gate by the tunneling barrier The tunnel barrier is isolated from the control gate, wherein the second portion of the wiper is spaced apart from the floating gate by a first length, the first length being measured in a direction substantially perpendicular to the length direction; The second portion has a first end closest to the control gate, the second portion of the wiper has a second length, the second length being the first portion of the second portion of the erase gate A vertical line of the first end aligned to the first end of the erase gate is measured in a direction substantially parallel to the length direction; wherein the ratio of the second length to the first length is approximately Between 1.0 and 2.5; in the control of the stack Between the gate and the second floating gate region formed above the select gate matrix. 如申請專利範圍第12項所述的方法，其中該等選擇閘與該等抹除閘在同個步驟形成。 The method of claim 12, wherein the selection gates are formed in the same step as the erase gates. 如申請專利範圍第13項所述的方法，其中藉沉積一層矽在該等成疊的閘上、之間與旁邊，且移除在該等成疊之閘上與第二區域上的矽之部分，來形成該等選擇閘與該等抹除閘。 The method of claim 13, wherein a layer of crucible is deposited on, between, and adjacent the stacked gates, and the crucibles on the stacking gate and the second region are removed. Part to form the selection gates and the erasers. 如申請專利範圍第12項所述的方法，其中該第一區域在該成疊對的控制閘與浮動閘形成後形成。 The method of claim 12, wherein the first region is formed after the stack of control gates and floating gates are formed. 如申請專利範圍第15項所述的方法，其中該第二區域在該等選擇閘與抹除閘形成後形成。 The method of claim 15, wherein the second region is formed after the selection gates and erase gates are formed. 如申請專利範圍第16項所述的方法，其中該等第一區域與第二區域藉由離子植入形成。 The method of claim 16, wherein the first region and the second region are formed by ion implantation. 一種提高非依電性記憶體晶胞抹除效率的方法，該晶胞之類型屬具有一第一導電型的一實質上單晶材料基體者，有一第二導電型的一第一區域，及該第二導電型的一第二區域，從該第一區域隔離，於其間形成一通道區域；該記憶體晶胞具有與相鄰於該第一區域之該通道區域的一第一部分絕緣且隔離的一選擇閘；且具有與該通道區域的一第二部分絕緣且隔離的一浮動閘；該浮動閘具有離選擇閘最近的一第一端，及第二端有一末端離該選擇閘最遠；該浮動閘具有在相對面的一頂面與一底面，該底面面向該通道區域；該記憶體晶胞具有一控制閘有在相對面的一頂面與一底面，該底面絕緣於且面向該浮動閘的該頂面；該控制閘與該選擇閘絕緣且相鄰，該控制閘具有離選擇閘最近的一第一端及離該選擇閘最遠的一第二端；其中該控制閘的該第二端比該浮動閘的該第二端更靠近一對齊於該浮動閘的該第一端的垂直線，藉此該浮動閘的該頂面的一部分未面向該控制閘的該底面；該記憶體晶胞更具有一抹除閘，其具有與該基體的第二區域絕緣且隔離的一第一部分，及具有藉由一穿隧障壁從該浮動閘的該第二端處的末端分離之一第一端，且一第二部分電氣連接該第一部分並具有一第 一端；其中該方法包含：藉由安置該抹除閘的該第二部分於浮動閘之上並且藉由穿隧障壁予以絕緣來屏蔽該穿隧障壁使之隔離於該控制閘，該第一端相鄰該控制閘，該抹除閘的該第二部分與該浮動閘隔著一第一長度，該第一長度是在實質上與從該第一區域到該第二區域的方向垂直的一方向上量測的；該第二部分的該第一端離該控制閘的該第二端最近，該抹除閘的該第二部分具有一第二長度，該第二長度係從該抹除閘之該第二部分的該第一端至對齊於該抹除閘之該第一部分的該第一端之一垂直線在實質上與從該第一區域到該第二區域之方向平行的一方向上量測的；並且其中該第二長度與該第一長度之比在大約1.0與2.5之間。 A method for improving the cell erasing efficiency of a non-electrical memory cell, the type of the cell being a substantially single crystal material matrix having a first conductivity type, a first region of a second conductivity type, and a second region of the second conductivity type is isolated from the first region to form a channel region therebetween; the memory cell has an isolation and isolation from a first portion of the channel region adjacent to the first region And a floating gate insulated from and isolated from a second portion of the channel region; the floating gate having a first end closest to the selection gate, and the second end having a distal end furthest from the selection gate The floating gate has a top surface and a bottom surface on the opposite side, the bottom surface facing the channel area; the memory unit cell has a control gate having a top surface and a bottom surface on the opposite surface, the bottom surface being insulated and facing The top surface of the floating gate; the control gate is insulated and adjacent to the selection gate, the control gate has a first end closest to the selection gate and a second end farthest from the selection gate; wherein the control gate The second end of the floating gate The second end is closer to a vertical line aligned with the first end of the floating gate, whereby a portion of the top surface of the floating gate does not face the bottom surface of the control gate; the memory cell has a wiper a gate having a first portion insulated from and isolated from the second region of the substrate, and having a first end separated from an end at the second end of the floating gate by a tunnel barrier, and a second Partially electrically connected to the first part and has a One end; wherein the method includes: shielding the tunneling barrier from the control gate by placing the second portion of the wiper over the floating gate and insulating by a tunneling barrier, the first end Adjacent to the control gate, the second portion of the wiper is spaced apart from the floating gate by a first length, the first length being substantially perpendicular to a direction from the first region to the second region Measured upwardly; the first end of the second portion is closest to the second end of the control gate, the second portion of the wiper has a second length, the second length is from the erase gate a vertical line of the first end of the second portion to the first end of the first portion of the wiper gate is substantially parallel to a direction parallel to a direction from the first region to the second region Measured; and wherein the ratio of the second length to the first length is between about 1.0 and 2.5. 如申請專利範圍第18項所述之方法，更包含在一抹除操作期間於該控制閘外加一負電壓。 The method of claim 18, further comprising applying a negative voltage to the control gate during an erasing operation.
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