TWI566433B - 形成微發光二極體陣列的方法 - Google Patents
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F21—LIGHTING
- F21V—FUNCTIONAL FEATURES OR DETAILS OF LIGHTING DEVICES OR SYSTEMS THEREOF; STRUCTURAL COMBINATIONS OF LIGHTING DEVICES WITH OTHER ARTICLES, NOT OTHERWISE PROVIDED FOR
- F21V7/00—Reflectors for light sources
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
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- H01L33/26—Materials of the light emitting region
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- H01L33/26—Materials of the light emitting region
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- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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Description
本申請案主張於2011年11月18日提出申請的美國臨時專利申請案第61/561,706號及於2012年2月3日提出申請的美國臨時專利申請案第61/594,919號的優先權權益,該等申請案之全部揭示內容以引用之方式併入本文。
本發明係關於微半導體元件。更特定而言,本發明之實施例係關於形成用於傳送至不同基板之微元件陣列(例如,發光二極體;LEDs)的方法。
基於氮化鎵(GaN)的發光二極體(LEDs)有望用於未來高效發光應用設備,來代替白熾燈與熒光燈。當前基於GaN的LED元件係藉由在外來基板材料上的異質磊晶生長技術製備的。典型的晶圓級LED元件結構可包括形成在藍寶石生長基板上的下部n型摻雜GaN層、單個量子阱(SQW)或多個量
子阱(MWQ),以及上部p型摻雜GaN層。
在一個實施中,藉由蝕刻穿過p型摻雜GaN層、量子阱層並進入n型摻雜GaN層來將晶圓級LED元件結構圖案化為藍寶石生長基板上的檯面陣列。上部p型電極形成在檯面陣列之頂部p型摻雜GaN表面上,且n型電極形成在與檯面陣列接觸之n型摻雜GaN層之一部分上。在最終產品中,檯面LED元件保留在藍寶石生長基板上。
在另一實施中,將晶圓級LED元件結構從生長基板傳遞至受體基板,該受體基板諸如具有比GaN/藍寶石複合結構更易於被分割形成個別晶片的優點之矽基板。在此實施中,晶圓級LED元件結構永久地接合至具永久性接合層的受體(矽)基板。舉例而言,形成在檯面陣列之p型摻雜GaN表面上的p型電極可接合至具永久性接合層的受體(矽)基板。隨後移除藍寶石生長基板以暴露倒轉的晶圓級LED元件結構,隨後薄化該倒轉的晶圓級LED元件結構以暴露檯面陣列。隨後與暴露的n型摻雜GaN產生n型接點,並在與p型電極電接觸的矽表面上產生p型接點。在最終產品中,檯面LED元件保留在受體基板上。亦可分割GaN/矽複合物以形成個別晶片。
描述微發光二極體(LED)及形成用於傳遞至接收基板之微LED陣列的方法。舉例而言,接收基板可為(但不局限於)顯示基板、發光基板、具有諸如電晶體或積體電路(ICs)
之功能元件的基板,或具有金屬再分配線之基板。在一實施例中,微LED結構包括微p-n型二極體及金屬化層,其中金屬化層在微p-n型二極體與形成在基板上的接合層之間。金屬化層可包括一或更多個層。舉例而言,金屬化層可包括電極層及電極層與接合層之間的障壁層。微p-n型二極體及金屬化層之每者可具有頂表面、底表面及側壁。在一實施例中,微p-n型二極體之底表面比微p-n型二極體之頂表面寬,且側壁為自頂到底向外楔形的。微p-n型二極體之頂表面亦可比p-n型二極體之底表面寬,或者微p-n型二極體之頂表面與p-n型二極體之底表面具有近似相同的寬度。在一實施例中,微p-n型二極體之底表面比金屬化層之頂表面寬。微p-n型二極體之底表面亦可比金屬化層之頂表面寬,或者微p-n型二極體之底表面與金屬化層之頂表面具有近似相同的寬度。
等形介電質障壁層可視情況地形成在微p-n型二極體及其他暴露表面上方。等形介電質障壁層可比微p-n型二極體、金屬化層及可選的接合層薄以使等形介電質障壁層形成構形的輪廓,該等形介電質障壁層形成在該構形上。在一實施例中,等形介電質障壁層橫跨微p-n型二極體之側壁,並可覆蓋微p-n型二極體中的量子阱層。等形介電質障壁層亦可部分地橫跨微p-n型二極體之底表面,並且橫跨金屬化層之側壁。在一些實施例中,等形介電質障壁層亦橫跨圖案化接合層之側壁。接點開口可形成在等形介電質障壁層中,暴露微p-n型二極體之頂表面。接點開口可具有大於、小於或近似等於微p-n型二極體之頂表面之寬度的寬度。在一個實施例中,
接點開口具有小於微p-n型二極體之頂表面之寬度的寬度,且等形介電質障壁層形成繞微p-n型二極體之頂表面邊緣的唇部。
在一些實施例中,接合層可由具有低於近350℃或更具體而言低於近200℃之液相線溫度或熔融溫度的材料形成。舉例而言,接合層可包括銦、錫或熱塑性聚合物(諸如,聚乙烯或聚丙烯)。接合層在基板上可為橫向連續的,或亦可形成在橫向獨立位置中。舉例而言,接合層之橫向獨立位置可具有小於或近似等於微p-n型二極體或金屬化層之底表面寬度的寬度。
在一實施例中,微LED陣列包括載體基板上之接合層的複數個位置及接合層之複數個位置上的相應複數個微LED結構。每一微LED結構包括微p-n型二極體及金屬化層,其中金屬化層在微p-n型二極體與接合層之各別位置之間。等形介電質障壁層可沉積在基板上之微LED陣列上,其中等形介電質障壁層橫跨每一微p-n型二極體之側壁。等形介電質障壁層亦可部分地橫跨每一微p-n型二極體之底表面及每一金屬化層之側壁。複數個接點開口可形成在等形介電質障壁層中,暴露每一微p-n型二極體之頂表面,其中每一接點開口具有可大於、小於或近似等於每一相應微p-n型二極體之頂表面寬度的寬度。
接合層之複數個位置可為或可不為彼此橫向獨立的。在一些實施例中,接合層之複數個位置係橫向獨立的且等形介電質障壁層橫跨接合層之複數個橫向獨立位置之每一
者的側壁。在一些實施例中,基板包括各別複數個支柱,接合層之複數個位置形成在該各別複數個支柱上。舉例而言,每一微p-n型二極體可包括一底表面,該底表面與各別支柱之頂表面具有近似相同寬度或比各別支柱之頂表面寬。支柱亦可具有大於接合層之位置之各別厚度的高度。在一實施例中,各別高度為各別厚度的至少兩倍。
可使用現有的異質生長技術形成微LED結構及微LED陣列。在一實施例中,將p-n型二極體層及金屬化層自生長基板傳遞至載體基板。根據本發明之實施例,可在將p-n型二極體層及金屬化層傳遞至載體基板之前或之後圖案化p-n型二極體層及金屬化層。將p-n型二極體層及金屬化層傳遞至載體基板之步驟可包括以下步驟:將金屬化層接合至載體基板上的接合層。舉例而言,接合層可具有低於近350℃或更具體而言低於200℃之液相線溫度或熔融溫度。舉例而言,接合層可由銦或銦合金形成。在圖案化p-n型二極體層及金屬化層以形成複數個獨立微p-n型二極體及金屬化層之複數個獨立位置後,橫跨複數個獨立微p-n型二極體之側壁形成等形介電質障壁層。等形介電質障壁層可形成構形之輪廓,該等形介電質障壁層形成至該構形上,且該等形介電質障壁層可比微p-n型二極體及金屬化層薄。舉例而言,可藉由原子層沉積(ALD)形成等形介電質障壁層。等形介電質障壁層亦可形成在每一獨立微p-n型二極體之底表面的一部分上。
在一實施例中,將p-n型二極體層及包括p-n型二極體層上之金屬化層之複數個獨立位置的圖案化金屬化層從
生長基板傳遞至載體基板。在將p-n型二極體層從生長基板傳遞至載體基板之前,可部分地圖案化該p-n型二極體層以形成在p-n型二極體層中由凹溝所分隔的微檯面。在一實施例中,在將p-n型二極體層及圖案化金屬化層傳遞至載體基板之前,在載體基板上形成複數個支柱。在將p-n型二極體層及圖案化金屬化層傳遞至載體基板之前,可在載體基板上之複數個支柱上方形成接合層。
在一實施例中,在將金屬化層及p-n型二極體層從生長基板傳遞至載體基板之後,圖案化金屬化層以形成金屬化層之複數個獨立位置。在此實施例中,圖案化p-n型二極體層以形成複數個獨立微p-n型二極體,隨後圖案化金屬化層。金屬化層之圖案化可包括以下步驟:蝕刻金屬化層直到金屬化層之複數個獨立位置的最大寬度小於複數個獨立微p-n型二極體之每一者之底表面的寬度。在一實施例中,在將p-n型二極體層及金屬化層從生長基板傳遞至載體基板之後,圖案化接合層。舉例而言,可蝕刻接合層直到接合層之複數個獨立位置的最大寬度小於複數個獨立微p-n型二極體之每一者之底表面的寬度。在將p-n型二極體層及金屬化層從生長基板傳遞至載體基板之前,亦可在載體基板上形成複數個支柱。在將p-n型二極體層及圖案化金屬化層傳遞至載體基板之前,可在載體基板上之複數個支柱上方形成接合層。
一旦形成微LED結構及微LED陣列,則該微LED結構及該微LED陣列可被拾取並傳遞至接收基板。傳遞頭可定位於載體基板上方,該載體基板具有微LED結構陣列設置
於該載體基板上,且執行操作以在接合層中產生微LED結構之至少一者的相變。舉例而言,操作可為加熱接合層至高於接合層之液相線溫度或熔融溫度,或改變接合層之晶相。包括微p-n型二極體及金屬化層的至少一個微LED結構以及視情況用於微LED結構之至少一者的接合層之一部分可用傳遞頭拾取並放置在接收基板上。若已經形成等形介電質障壁層,則亦可隨著微p-n型二極體及金屬化層拾取等形介電質障壁層之一部分。或者,等形介電質障壁層在被放置於接收基板上之後可形成在微LED結構或複數個微LED結構上方。
在一實施例中,等形介電質障壁層橫跨微p-n型二極體之底表面的一部分,橫跨金屬化層之側壁,並橫跨鄰近金屬化層之接合層的一部分。可在使微LED結構與傳遞頭接觸及/或在接合層中產生相變後切割等形介電質障壁層,此舉可在用傳遞頭拾取微p-n型二極體及金屬化層之前。舉例而言,切割等形介電質障壁層之步驟可包括以下步驟:將壓力從傳遞頭傳遞至等形介電質障壁層及/或加熱接合層至高於接合層的液相線溫度。
101‧‧‧基板
110‧‧‧半導體元件層
112‧‧‧塊狀GaN層
114‧‧‧n型摻雜層
116‧‧‧量子阱
118‧‧‧p型摻雜層
120‧‧‧金屬化層
121‧‧‧頂表面
122‧‧‧電極層
124‧‧‧障壁層
130‧‧‧微檯面
132‧‧‧楔形側壁
134‧‧‧凹溝
135‧‧‧微p-n型二極體
140‧‧‧遮罩層
150‧‧‧微p-n型二極體
151‧‧‧底表面
152‧‧‧頂表面
160‧‧‧等形介電質障壁層
153‧‧‧楔形側壁
201‧‧‧載體基板
162‧‧‧接點開口
203‧‧‧頂表面
202‧‧‧支柱
204‧‧‧側壁
206‧‧‧凹溝
210‧‧‧液態接合層
211‧‧‧頂表面
300‧‧‧傳遞頭
302‧‧‧基底基板
304‧‧‧檯面結構
306‧‧‧側壁
307‧‧‧側壁
308‧‧‧頂表面
309‧‧‧頂表面
310‧‧‧鈍化層
316A‧‧‧電極
316B‧‧‧電極
320‧‧‧介電層
321‧‧‧頂表面
410‧‧‧驅動器接點
400‧‧‧接收基板
1300‧‧‧操作
420‧‧‧接觸線
1320‧‧‧操作
1310‧‧‧操作
1330‧‧‧操作
A‧‧‧實例
B‧‧‧實例
C‧‧‧實例
D‧‧‧實例
E‧‧‧實例
F‧‧‧實例
G‧‧‧實例
H‧‧‧實例
I‧‧‧實例
J‧‧‧實例
K‧‧‧實例
L‧‧‧實例
M‧‧‧實例
N‧‧‧實例
O‧‧‧實例
P‧‧‧間距
S‧‧‧空隙
W‧‧‧寬度
第1A圖係根據本發明之實施例之塊狀LED基板的剖面側視圖圖解。
第1B圖係根據本發明之實施例之圖案化金屬化層的剖面側視圖圖解。
第1C圖係根據本發明之實施例之圖案化p-n型二極
體層的剖面側視圖圖解。
第2A圖至第2E圖係根據本發明之實施例具接合層之載體基板的剖面側視圖圖解。
第3圖係根據本發明之實施例將生長基板與載體基板接合在一起的剖面側視圖圖解。
第4圖係根據本發明之實施例在將生長基板與載體基板接合在一起之後的各種可能結構的剖面側視圖圖解。
第5圖係根據本發明之實施例從接合結構移除生長基板的剖面側視圖圖解。
第6圖係根據本發明之實施例漸薄的p-n型二極體層之剖面側視圖圖解。
第7圖係根據本發明之實施例蝕刻p-n型二極體層以形成微p-n型二極體的剖面側視圖圖解。
第7'圖至第7"圖係根據本發明之實施例蝕刻層的剖面側視圖圖解。
第8圖係根據本發明之實施例之各個微LED結構的剖面側視圖圖解。
第9圖至第9'圖係根據本發明之實施例在微LED陣列中形成接點開口的剖面側視圖圖解。
第10圖至第10"圖係根據本發明之實施例在微LED陣列中形成接點開口的剖面側視圖圖解。
第11A圖至第11C圖係根據本發明之實施例向上毛細作用接合層的剖面側視圖圖解。
第12A圖至第12B圖包括根據本發明之實施例包括
微p-n型二極體之微LED結構陣列與載體晶圓的剖面俯視圖圖解與剖面側視圖圖解。
第13圖係根據本發明之實施例從載體基板拾取並傳遞微LED結構至接收基板之方法的圖解。
第14圖係根據本發明之實施例從載體基板拾取微LED結構之傳遞頭的剖面側視圖圖解。
第15圖係根據本發明之實施例之雙極微元件傳遞頭的剖面側視圖圖解。
第16圖係根據本發明之實施例具複數個微LED之接收基板的剖面側視圖圖解。
本發明之實施例描述微半導體元件與形成傳遞至接收基板之微半導體元件(諸如,微發光二極體(LEDs))陣列的方法。舉例而言,接收基板可為(但不局限於)顯示基板、發光基板、具有諸如電晶體或積體電路(ICs)之功能元件的基板,或具有金屬再分配線之基板。儘管具體關於包含p-n型二極體之微LED描述本發明之實施例,但應理解本發明之實施例不受此限制且某些實施例亦可適用於以此方式經設計以用受控方式執行預定電子功能(例如,二極體、電晶體、積體電路)或光子功能(LED、雷射)的其他微半導體元件。
在各種實施例中,參照諸圖作出描述。然而,可在無此等具體細節之一或更多者的情況下,或結合其他已知的方法與配置實踐某些實施例。在下文描述中,闡述許多具體
細節(諸如,具體配置、尺寸及製程等),以提供對本發明之透徹理解。在其他情況下,不以特定細節描述熟知的半導體製程及生產技術以免不必要地模糊本發明。貫穿此說明書中對「一個實施例」、「一實施例」等之引用意指結合實施例描述之特定特徵結構、結構、功能或特徵被包括在本發明之至少一個實施例中。因此,貫穿此說明書中之不同地方出現之用語「在一個實施例中」、「在一實施例中」等未必係指本發明之相同實施例。此外,可在一或更多個實施例中以任一適合的方式組合特定特徵結構、結構、配置或特徵。
如本文所使用之術語「橫跨」、「在...上方」、「至」、「在...之間」及「在...上」可指一個層相對於其他層的相對位置。「橫跨」另一層、在另一層「上方」或在另一層「上」或接合「至」另一層之一個層可直接接觸其他層或可具有一或更多個插入層。在層「之間」的一個層可直接接觸層或可具有一或更多個插入層。
如本文所使用之術語「微」元件、「微」p-n型二極體或「微」LED結構可指根據本發明之實施例的某些元件或結構之描述性尺寸。如本文所使用,術語「微」元件或結構意指1 μm至100 μm之尺度。然而,應理解本發明之實施例不必受此限制,且實施例之某些態樣可適用於更大或可能更小之尺寸尺度。
在一個態樣中,本發明之實施例描述將塊狀LED基板處理成準備被拾取並傳遞至接收基板之微LED結構陣列的方法。以此方式,有可能將微LED結構整合並組裝成異質整
合系統。可個別地、成群組地或作為整個陣列地拾取並傳遞微LED結構。因此,使微LED結構陣列中之微LED結構準備被拾取並以高傳遞速率傳遞至接收基板(諸如,範圍從微顯示器至大面積顯示器之任一尺寸的顯示基板)。在一些實施例中,將準備被拾取的微LED結構陣列描述成具有10 μm×10 μm間距或5 μm×5 μm間距。以此等密度,例如6吋基板可容納近1.65億個具10 μm×10 μm間距的微LED結構,或近6.6億個具5 μm×5 μm間距的微LED結構。因此,可以具有具體功能性之高密度預製微元件準備被拾取並傳遞至接收基板的方式產生該等微元件。本文描述之技術不局限於微LED結構,且該等技術亦可用於其他微元件之製造。
在另一態樣中,本發明之實施例描述微LED結構及微LED陣列,在該微LED結構及該微LED陣列中之每一微p-n型二極體形成在接合層之各別位置上方。接合層之各別位置可為或可不為橫向獨立位置。可在微LED拾取製程期間在對應於微LED之接合層的各別位置上執行操作,在該微LED拾取製程中,接合層之各別位置經歷協助拾取製程的相變。舉例而言,接合層之各別位置可回應於溫度循環自固態變化至液態。在液態中,接合層之各別位置可經由表面張力保持微p-n型二極體在載體基板上之適當位置,並亦提供從中可容易地釋放微p-n型二極體的媒體。另外,若在拾取製程期間傳遞頭與微LED結構接觸,則液態可作為緩衝或減震器以吸收由傳遞頭施加的力。以此方式,液態可藉由回應於由傳遞頭施加的壓縮力在下層表面上方變平滑來補償微LED陣列或傳
遞頭陣列之構形中的不均勻性。在其他實施例中,接合層之各別位置可不經歷完整的相變。舉例而言,接合層之各別位置在部分地保持在固態的同時可變為回應於溫度循環實質上更具延展性的。在另一實施例中,接合層之各別位置可經歷回應於操作(諸如,溫度循環)的晶相轉換。
現參照第1圖,半導體元件層110可形成在基板101上。在一實施例中,半導體元件層110可包括一或更多個層且半導體元件層110以此方式經設計以受控的方式執行預定電子功能(例如,二極體、電晶體、積體電路)或光子功能(LED、雷射)。應理解,儘管半導體元件層110可以此方式經設計來以受控的方式執行預定功能,但是可不完全地功能化半導體元件層110。舉例而言,亦可不形成諸如陽極或陰極之接點。為了簡明且不模糊本發明之實施例,關於半導體元件層110作為根據習知異質生長條件生長在生長基板101上的p-n型二極體層110做出以下描述。
p-n型二極體層110可包括複合半導體,該複合半導體具有對應於光譜中之具體區域的能帶隙。舉例而言,p-n型二極體層110可包括基於II-VI族材料(例如,ZnSe)或III-V氮族化物材料(例如,GaN、AlN、InN,以及以上之合金)的一或更多個層。生長基板101可包括任何適合的基板(諸如(但不限於),矽、SiC、GaAs、GaN及藍寶石(Al2O3))。
在一特定實施例中,生長基板101係藍寶石,且p-n型二極體層110係由GaN形成。儘管藍寶石相對於GaN具有較大晶格常數及熱膨脹係數失配,但是藍寶石成本相當低、
獲得方式廣泛且藍寶石之透明度與基於準分子雷射的升離(lift-off;LLO)技術相配。在另一實施例中,另一材料(諸如,SiC)可用作用於GaN p-n型二極體層110之生長基板101。類似於藍寶石,SiC基板可為透明的。若干生長技術可用於生長p-n型二極體層110,該若干生長技術諸如金屬有機的化學氣相澱積(MOCVD)。可藉由在將藍寶石生長基板101加熱至高溫(諸如,800℃至1000℃)的情況下同時將三甲基鎵(TMGa)前驅物及氨(NH3)前驅物引入至反應腔室中來生長例如GaN。在圖示於第1A圖中之特定實施例中,p-n型二極體層110可包括塊狀GaN層112、n型摻雜層114、量子阱116及p型摻雜層118。塊狀GaN層112可為由於矽或氧污染的n型摻雜,或有意摻雜有諸如矽之供體。n型摻雜GaN層114可同樣摻雜有諸如矽之供體,而p型摻雜層118可摻雜有諸如鎂之受體。可使用各種替代性p-n型二極體配置來形成p-n型二極體層110。同樣地,可使用各種單個量子阱(SQW)或多個量子阱(MQW)配置來形成量子阱116。另外,視情況而定可包括各緩衝層。在一個實施例中,藍寶石生長基板101具有近200 μm之厚度,塊狀GaN層112具有近5 μm之厚度,n型摻雜層114具有近0.1 μm-3 μm之厚度,量子阱層116具有小於近0.3 μm之厚度且p型摻雜層118具有近0.1 μm-1 μm之厚度。
金屬化層120可隨後形成在p-n型二極體層110上方。如第1A圖所圖示,金屬化層120可包括電極層122及視情況的障壁層124,但可包括其他層。在一實施例中,金屬化
層具有近0.1 μm-2 μm之厚度。電極層122可與p型摻雜GaN層118歐姆接觸,並可由高功函數金屬(諸如,Ni、Au、Ag、Pd及Pt)形成。在一實施例中,電極層122對光發射可為反射性的。在另一實施例中,電極層122對光發射亦可為透明的。可藉由使電極層非常薄以最小化光吸收來實現透明性。障壁層124可視情況地包括在金屬化層120中以防止雜質擴散進入p-n型二極體110中。舉例而言,障壁層124可包括(但不限於)Pd、Pt、Ni、Ta、Ti及TiW。在某些實施例中,障壁層124可防止組份從接合層擴散進入p-n型二極體層110中。
根據本發明之某些實施例,p-n型二極體層110及金屬化層120生長在生長基板101上並隨後傳遞至載體基板201,諸如,第2A圖至第2E圖中圖示及在以下描述中更詳細地描述之載體基板。如在以下諸圖及描述中更詳細地描述,可在將金屬化層120及p-n型二極體層110傳遞至載體基板201前圖案化該金屬化層120及該p-n型二極體層110。亦可在將p-n型二極體層110及金屬化層120傳遞至載體基板201前圖案化載體基板201及接合層210。因此,在形成微LED陣列用於後續傳遞至接收基板期間可以眾多變化實施本發明之實施例。
現參照第1B圖,可在將金屬化層120傳遞至載體基板201前圖案化該金屬化層120。在一實施例中,可藉由在將圖案化光阻層形成在p-n型二極體層110上方之後沉積金屬化層120來實現第1B圖之結構。隨後升離光阻層(連同光阻層
上之金屬化層的部分),留下第1B圖圖示之金屬化層120的橫向獨立位置。在某些實施例中,對應於微LED陣列之間距,金屬化層120之橫向獨立位置的間距可為5 μm、10 μm或更大。舉例而言,5 μm間距可由以2 μm空隙分隔之金屬化層120的3 μm寬的橫向獨立位置形成。10 μm間距可由以2 μm空隙分隔之金屬化層120的8 μm寬的橫向獨立位置形成。但是,此等尺寸意為示例性且本發明之實施例不受此限制。在一些實施例中,如在以下描述及諸圖中進一步詳細地論述,金屬化層120之橫向獨立位置的寬度小於或等於微p-n型二極體150陣列之底表面的寬度。
現參照第1C圖,金屬化層120之圖案化之後可為p-n型二極體層110之圖案化。在一實施例中,可藉由將第二圖案化光阻層形成在金屬化層120之橫向獨立位置上方來實現第1C圖之結構,且施加蝕刻劑以蝕刻p-n型二極體層110來蝕刻凹溝134並形成複數個微檯面130。再次參照第1A圖中之p-n型二極體層110的放大區段,在一實施例中,執行蝕刻步驟以蝕刻凹溝穿過p型摻雜層118、量子阱116並進入n型摻雜層114或塊狀層112中。可使用乾式電漿蝕刻技術(諸如,反應式離子蝕刻(RIE)、電子迴旋加速器諧振源(ECR)、感應耦合的電漿反應式離子蝕刻(ICP-RIE)及化學輔助離子束蝕刻(CAIBE))執行GaN p-n型二極體層110之蝕刻。蝕刻化學可為基於鹵素的,包含諸如Cl2、BCl3或SiCl4之物種。在第1C圖所圖示的特定實施例中,微檯面130可具有高達15度的楔形側壁132。舉例而言,可使用具基於氯之蝕刻化學的
RIE。或者,側壁可為垂直的。舉例而言,可使用為基於氯之蝕刻化學的ICP-RIE來獲得垂直的側壁。
在某些實施例中,微檯面130之間距可為5 μm、10 μm或更大。舉例而言,具5 μm間距的微檯面130陣列可由以2 μm空隙分隔的3 μm寬微檯面形成。具10 μm間距的微檯面130陣列可由以2 μm空隙分隔的8 μm寬微檯面形成。但是,此等尺寸意謂示例性且本發明之實施例不受此限制。
第2A-2E圖係載體基板201之各種實施例的剖面側視圖圖解,該載體基板201具有接合層210用於接合至生長基板101上的金屬化層120。第2A圖圖示在接合之前不被圖案化的接合層210及載體基板201。第2B-2D圖圖示已經圖案化以形成具有側壁204並由凹溝206分隔的複數個支柱202的載體基板201。支柱202可具有等於或小於微p-n型二極體135、150之寬度的最大寬度,如將在以下描述及諸圖中變得更加顯而易見。在一實施例中,凹溝支柱202之高度為接合層210之厚度的至少兩倍。在一實施例中,接合層210可具有近0.1 μm-2 μm的厚度,且凹溝支柱具有至少0.2 μm-4 μm的高度。在第2B圖所圖示之特定實施例中,等形接合層210形成在支柱202上方,並在側壁204上且在凹溝206內。在第2C圖所圖示的特定實施例中,非均質地沉積接合層210,以使接合層210僅形成在支柱202之頂表面上及凹溝206內,而非大量沉積在側壁204上。在第2D圖所圖示的特定實施例中,接合層210僅形成在支柱202之頂表面上。可藉由以相同的圖案化光阻劑圖案化支柱202及接合層210來形成此配
置。在第2E圖所圖示之特定實施例中,可以光阻劑升離技術形成接合層210之橫向獨立位置,在光阻劑升離技術中,接合層之毯覆層沉積在圖案化光阻層上方,隨後升離該等毯覆層(連同光阻層上之部分接合層)留下第2E圖圖示之接合層210之橫向獨立位置,但是可使用其他處理技術。
如上文關於第2B圖至第2E圖及第1B圖至第1C圖所描述,本發明之某些實施例包括金屬化層120之橫向獨立位置及/或接合層210之橫向獨立位置。關於第2B圖,在第2B圖中,等形接合層210形成在支柱202上方,並在側壁204上及在凹溝206內,支柱202之頂部上之接合層的特定位置係由凹溝206橫向地分隔。因此,即使等形接合層210係連續的,支柱202之頂部上的接合層210之位置仍為橫向獨立位置。同樣地,藉由第2E圖中之接合層210之個別不連續位置之間的空間橫向分隔該等位置。在存在支柱202的情況下,接合層210厚度與支柱202高度的關係可成為接合層210之位置之橫向間隔的因素。
接合層210可由各種適合的材料形成。接合層可由能夠將微LED結構黏附至載體基板的材料形成。在一實施例中,接合層210可經歷回應於操作(諸如,溫度變化)的相變。在一實施例中,接合層由於相變可為可移除的。在一實施例中,接合層可為可再熔融的或可再流動的。在一實施例中,接合層可具有低於近350℃或更具體而言低於近200℃之液相線溫度或熔融溫度。在此等溫度處,接合層可經歷相變而不實質上影響微LED結構之其他組分。舉例而言,接合層
可由金屬或金屬合金或可移除的熱塑性聚合物形成。在一實施例中,接合層可為導電的。舉例而言,在接合層回應於溫度變化而經歷從固態至液態之相變的情況下,接合層的一部分可在如以下描述中以更多細節描述之拾取操作期間保持在微LED結構上。在此實施例中,接合層由導電材料形成可為有利的,以使該接合層在隨後傳遞至接收基板時不會不利地影響微LED結構。在此情況下,在傳遞操作期間保持在微LED結構上之導電接合層的部分可幫助將微LED結構接合至接收基板上的導電墊。
焊料可為用於接合層210之適合的材料,因為許多焊料在自身固態中通常為韌性材料並展現與半導體及金屬表面有利的潤濕。典型的合金並非在單個溫度而是在溫度範圍中熔融。因此,焊料合金之特徵通常在於對應於合金保持液態所處之最低溫度的液相線溫度,以及對應於合金保持固態所處之最高溫度的固相線溫度。在表1中提供可用於本發明之實施例之低熔融焊料材料的示例性列表。
在表2中提供可用於本發明之實施例之熱塑性聚合物的示例性列表。
根據本發明之實施例,可以均勻厚度形成接合層210並可藉由取決於特定成分之各種適合的方法沉積接合層210。舉例而言,可濺鍍焊料成分、藉由電子束(E-束)蒸鍍來沉積焊料成分或以晶種層電鍍焊料成分以獲得均勻厚度。
支柱202可由各種材料及技術形成。在一實施例中,可藉由以蝕刻或壓印製程圖案化載體基板201來與載體
基板201整體形成支柱202。舉例而言,載體基板201可為具有整體形成之支柱202的矽基板。在另一實施例中,支柱可形成在載體基板201之頂部上。舉例而言,可藉由電鍍及光阻劑升離技術來形成支柱202。支柱可由包括半導體、金屬、聚合物、介電質等之任何適合的材料形成。
現參照第3圖,生長基板101及載體基板201可在熱量及/或壓力下接合在一起。應理解,儘管第3圖圖示第1B圖之圖案化結構與第2A圖之未圖案化結構的接合,但是根據本發明之實施例設想第1A圖至1C圖及第2A圖至第2E圖之任一組合。另外,儘管已經描述接合層210在接合之前形成在載體基板201上,但是接合層210亦有可能在接合之前形成在生長基板101之金屬化層120上。舉例而言,在第1B圖所圖示之金屬化層之橫向獨立位置形成期間,接合層210可形成在金屬化層120上方並用金屬化層120圖案化該接合層210。儘管未圖示,但是取決於形成在基板上以接合在一起的層之特定佈置及成分,抗氧化膜可在接合前形成在基板之任一者或兩者的頂表面上以防止氧化。舉例而言,在一個實施例中,薄金膜可沉積在金屬化層120及接合層210之暴露表面的任一者或兩者上。在第3圖所圖示的基板之接合期間,接合層210在基板之間的接合介面處可部分地吸取金膜產生金合金。
第4圖係在將生長基板101與載體基板201接合之後的各個非限制性可能結構的剖面側視圖圖解。在表3中描述基板之特定組合。舉例而言,在實例4A中所說明之特定實
施例表示第2D圖所圖示之載體基板接合至第1C圖所圖示之生長基板。
如上文所描述,亦可藉由將接合層210形成在生長基板上,隨後將生長基板101接合至載體基板201來產生實例之許多實例的結構。舉例而言,亦可藉由圖案化在生長基板101上的接合層210及金屬化層120,隨後將生長基板101接合至載體基板201來產生實例4O。
現參照第5圖,已經從接合結構移除生長基板101。若生長基板係透明的,則可藉由適合的方法(諸如,化學蝕刻或基於準分子雷射的升離(LLO))移除生長基板101。在一實施例中,藉由以來自紫外線雷射(諸如,Nd-YAG雷射或KrF準分子雷射)之短脈衝(例如,數十毫微秒)照射101/110層介面穿過透明的藍寶石生長基板101來完成GaN p-n型二極體層110從透明的藍寶石生長基板101之LLO。在介面處
之GaN p-n型二極體層110中之吸收造成介面之局部加熱,該局部加熱造成介面處GaN分解成液態Ga金屬及氮氣。一旦已照射期望的區域,可藉由在加熱板上再熔融Ga來移除透明的藍寶石生長基板101。
現參照第6圖,p-n型二極體層110變薄至期望的厚度。回頭參照第1A圖中擴大的p-n型二極體層110,移除預定量之塊狀GaN層112(可為n型)或一部分n型GaN層114以在p-n型二極體變薄後保持可操作的p-n型二極體。取決於下層的結構,可使用適用技術(諸如,研磨、濕式蝕刻或乾式蝕刻)執行薄化製程。舉例而言,可執行研磨及/或定時蝕刻的組合達到期望厚度。在存在下層的圖案化結構(諸如,柱件或微檯面)的環境中,可執行定時蝕刻達到期望厚度以免破壞圖案化結構。如預圖案化p-n型二極體層110以形成微檯面130的實例6A、實例6B、實例6C、實例6I及實例6J所示,該等微檯面130此刻係獨立式的微p-n型二極體135。
如第6圖所圖示,若生長基板101或載體基板201結構之任一者在接合之前未被預圖案化或僅部分地被預圖案化,則可在p-n型二極體層110變薄後執行額外的圖案化。如第7圖中所圖示,圖案化遮罩層140可形成在未圖案化的p-n型二極體層110上方用於蝕刻p-n型二極體層110,以形成獨立式的微p-n型二極體150。遮罩層140可由光阻劑或比光阻劑對GaN蝕刻條件更具抗性之諸如金屬(例如,鉻、鎳)或介電質(氮化矽、氧化矽)之各種材料形成。可使用乾式電漿蝕刻技術(諸如,反應式離子蝕刻(RIE)、電子迴旋加速器
諧振源(ECR)、感應耦合的電漿反應式離子蝕刻(ICP-RIE)及化學輔助離子束蝕刻(CAIBE))執行GaN p-n型二極體層110之蝕刻。蝕刻化學可為基於鹵素的,包含諸如Cl2、BCl3或SiCl4之物種。
在第7圖所圖示之特定實施例中,微p-n型二極體150可具有達15度的向外楔形側壁153(自微p-n型二極體150之頂部至底部)。舉例而言,可使用具基於氯之蝕刻化學的RIE。或者,側壁153可為垂直的。舉例而言,可使用為基於氯之蝕刻化學的ICP-RIE來獲得垂直的側壁。如在第16圖之描述中將變得更加明白,在一些實施例中,當形成已被拾取且傳遞至接收基板之一系列微LED結構上方的共用接點時,向外楔形側壁可為有利的。在某些實施例中,微p-n型二極體150之間的間距可為5μm、10μm或更大。舉例而言,具5μm間距的微p-n型二極體150陣列可由以2μm空隙分隔的3μm寬微p-n型二極體形成。具10μm間距之微p-n型二極體150陣列可由以2μm空隙分隔的8μm寬微p-n型二極體形成。
現參照第7'圖至第7"圖,可在金屬化層120及/或接合層210中使用基於特定材料的適合蝕刻化學來在金屬化層120及/或接合層210上視情況地繼續蝕刻。在第7'圖所圖示的某些實施例中,可使用具有乾式蝕刻化學之各向異性刻蝕來蝕刻金屬化層120及/或接合層210以使層120、210具有匹配微p-n型二極體150之上覆下表面的寬度。在第7"圖所圖示的某些實施例中,如實例7"D-7"H所圖示,可使用濕式蝕
刻「底切」在微p-n型二極體150之上覆下表面下部的金屬化層120及/或接合層210。儘管未具體圖示,但是應理解亦可執行蝕刻以「底切」在微p-n型二極體135下部之下層的層120、210。
在完成微p-n型二極體、金屬化層或接合層之蝕刻製程之後,可例如藉由使用選擇性蝕刻技術移除遮罩層140,產生如第8圖所圖示之微LED陣列。如圖所示,微LED陣列包括載體基板201、載體基板上之接合層210的複數個位置(該等位置可為或可不為橫向獨立的),以及接合層210之複數個位置上方之各別複數個獨立微p-n型二極體135、150。金屬化層120之複數個獨立位置形成在各別複數個獨立微p-n型二極體135、150與接合層210之複數個位置之間。在一些實施例中,載體基板包括各別複數個支柱202,在該各別複數個支柱202上形成接合層210之複數個橫向獨立位置,如實例8A-8F及實例8K-8M所圖示。
在一些實施例中,微p-n型二極體150(以及微p-n型二極體135)包括頂表面152及底表面151,且金屬化層120包括頂表面121及底表面,且微p-n型二極體150(以及微p-n型二極體135)之底表面151比金屬化層120之頂表面121寬。
在一些實施例中,複數個微p-n型二極體135、150之各者包括與各別複數個支柱202之每一者的頂表面203具有近似相同寬度的底表面151。在其他實施例中,複數個微p-n型二極體135、150之各者包括比各別複數個支柱202之
每一者之頂表面203寬的底表面151。微p-n型二極體135、150底部寬度與下層的支柱202頂表面的關係可影響拾取製程。舉例而言,若接合層210在拾取製程期間展現從固態至液態的相變,則微p-n型二極體135、150基本上浮動在液態層上。液化的接合層210中之表面張力可使微p-n型二極體135、150保持在支柱202之頂部上的適當位置。特定言之,與支柱202之頂表面之邊緣相關的表面張力可進一步協助使微p-n型二極體135、150維持在支柱202頂表面寬度小於或近似等於p-n型二極體135、150底部寬度的適當位置。
在一些實施例中,複數個微p-n型二極體135、150設置在未圖案化的接合層210上方。舉例而言,如實例6I與實例8N所圖示,接合層210可為載體基板上之均勻的層,且接合層210之相應的複數個位置彼此非橫向獨立。在其他實施例中,複數個微p-n型二極體135、150設置在圖案化接合層210上方。舉例而言,如實例8A-8M及實例8O所圖示,圖案化接合層可包括接合層210之複數個橫向獨立位置。在一實施例中,複數個微p-n型二極體135、150各自包括具有與接合層210之複數個橫向獨立位置之相應頂表面211相同或更大寬度的底表面151。
如先前所描述,接合層在拾取製程期間可吸收與使微LED結構與傳遞頭接觸相關之壓縮力。因此,接合層可吸收壓縮力並橫向隆起。在圖案化每一微LED結構以具有小分隔距離(例如,具有2μm之小分隔距離)的情況下,應最小化自每一微LED結構橫向突出之接合層的量以免在拾取製程
期間干擾鄰近的微LED結構。在凹溝206存在於支柱202之間的某些實施例中,凹溝可作為接合層儲集器,熔融接合層可流動進入該等儲集器而不干擾鄰近的微LED結構。
在一些實施例中,第8圖之微LED結構或微LED結構陣列(以及移除層140之後的第7圖實例7'D-7'I及第6圖實例6I的微LED結構)準備好例如用關於第14圖至第16圖更詳細地描述之傳遞頭300拾取並傳遞至接收基板。在其他實施例中,可在微p-n型二極體135、150被拾取並傳遞至接收基板之前由微p-n型二極體135、150之任何微p-n型二極體135、150的陣列形成薄等形介電質障壁層。現參照第9'圖至第9'圖,薄等形介電質障壁層160可形成在第7'圖至第7"圖之微p-n型二極體150之任何微p-n型二極體150的陣列上方。在一個實施例中,薄等形介電質障壁層160在拾取製程期間可免受鄰近的微p-n型二極體150之間的電弧放電,並藉此使鄰近的微p-n型二極體150在拾取製程期間避免黏附在一起。薄等形介電質障壁層160亦可保護微p-n型二極體150之側壁153、量子阱層116及底表面151免受可能影響微p-n型二極體150之完整性的污染。舉例而言,如在以下描述中關於第11A圖至第11C圖更詳細地描述,薄等形介電質障壁層160可用作對接合層材料210向上沿微p-n型二極體150之側壁及量子層116的毛細作用的實體障壁。一旦微p-n型二極體150放置在接收基板上,薄等形介電質障壁層160亦可絕緣微p-n型二極體150。在一實施例中,薄等形介電質障壁層160為近50-600埃厚的氧化鋁(Al2O3)。可藉由各種適用技
術(諸如(但不限於)原子層沉積(ALD))來沉積等形介電質障壁層160。
可使用遮罩層升離技術形成薄等形介電層及接點開口。參照第9圖至第9'圖,第7圖所圖示之用於圖案化微p-n型二極體150的遮罩層140亦可用在用於形成薄等形介電質障壁層160及接點開口162的升離技術中。薄等形介電質障壁層160可形成在第7圖、第7'圖或第7"圖之微p-n型二極體150之任何微p-n型二極體150陣列上方且等形於並橫跨遮罩層140之暴露的表面,以及p-n型二極體150之側壁153及底表面151。等形介電質障壁層160亦可橫跨金屬化層120、接合層210之暴露表面,以及載體基板及支柱202(若存在載體基板及支柱202)。隨後移除遮罩層140,升離形成在遮罩層140上的薄等形介電質障壁層160之部分,產生第9'圖所圖示包括接點開口162的結構。在第9'圖所圖示之特定實施例中,等形介電質障壁層160並非形成在微p-n型二極體150之頂表面152上。
參照第10圖至第10"圖,薄等形介電層亦可形成在第8圖之微p-n型二極體135、150陣列(以及在移除層140之後,第7圖實例7'D-7'I及第6圖實例6I之微LED結構)上方,隨後圖案化該薄等形介電層以產生接點開口162。如第9圖所圖示,薄等形介電質障壁層160可形成在微p-n型二極體150之任何微p-n型二極體150陣列上方並等形於且橫跨p-n型二極體150之暴露的頂表面及側壁。介電質障壁層160亦可橫跨p-n型二極體135、150之暴露底表面151及金屬化
層120、接合層210之表面,以及載體基板201及支柱202(若存在)。毯覆式光阻層隨後可形成在p-n型二極體陣列及載體基板201上方,並隨後圖案化毯覆式光阻層以形成每一微p-n型二極體135、150上方的開口。隨後可蝕刻薄等形介電質障壁層160以形成每一微p-n型二極體135、150之頂表面上的接點開口162。接點開口162圖示於移除圖案化光阻劑後的第10'圖至第10"圖中。如第10'圖所圖示,接點開口162與微p-n型二極體135、150之頂表面相比可具有略小的寬度。寬度上的差異原因可能為用於圖案化光阻劑中對準容限之調整。因此,等形介電質障壁層160可形成環繞微p-n型二極體135、150之頂表面及側壁的唇部。如第10"圖所圖示,接點開口162與微p-n型二極體135、150之頂表面相比可具有略大的寬度。在第10”圖所圖示之實施例中,接點開口162暴露微p-n型二極體150之頂表面及微p-n型二極體150之側壁的上部,而介電質障壁層160覆蓋並絕緣量子阱層116。
現參照第11A圖至第11C圖,根據本發明之一些實施例,以下行為係可能的:一定量的接合層210在第3圖所圖示的接合操作期間沿金屬化層120之側表面及沿p-n型二極體層110之底表面151向上毛細滲透。參照第11B圖,以下行為係可能的:在形成微p-n型二極體150後,向上毛細滲透的一定量接合層210在後續處理期間可能潛在地繼續該一定量接合層210沿微p-n型二極體150之側壁153的遷移。朝量子阱層116之繼續的遷移可能干擾微p-n型二極體150之操作。現參照第11C圖,根據本發明之實施例,等形介電質障
壁層160在後續溫度循環(特別是在高於接合層材料210之液相線溫度或熔融溫度之溫度處)期間(諸如,在自載體基板拾取微元件並將微元件釋放在接收基板上之期間)可用作實體障壁以保護微p-n型二極體150之量子阱層116及側壁153免受接合層材料210的污染。儘管已參照微p-n型二極體150圖示及描述了第11A圖至第11C圖,但是亦應設想到,以下情況係可能的:一定量的接合層210在第3圖所圖示的接合操作期間可向上毛細滲透並繼續該一定量的接合層210沿用於形成微p-n型二極體135的微檯面130之側壁的遷移。等形介電質障壁層160可類似地用作實體障壁以保護微p-n型二極體135之側壁及量子阱層116免受接合層材料210的污染。
第12A圖至第12B圖包括根據本發明之實施例之載體基板201及微LED結構陣列的剖面俯視圖圖解與剖面側視圖圖解。在所圖示的特定實施例中,自包括微p-n型二極體150之實例10'N的微LED結構產生陣列。然而,應理解,第12A圖至第12B圖意謂示例性的,且微LED結構陣列可由先前描述的微LED結構之任何微LED結構形成。在第12A圖所圖示的實施例中,每一個別微p-n型二極體150圖示為一對同心圓,該對同心圓具有對應於微p-n型二極體150之頂表面及底表面之不同寬度以及橫跨在頂表面及底表面之間的相應楔形側壁的不同直徑或寬度。在第12B圖所圖示的實施例中,每一個別微p-n型二極體150圖示為具有楔形角或圓角的一對同心正方形,其中每一正方形具有對應於微p-n型二極體
150之頂表面及底表面之不同寬度以及從頂表面及底表面橫跨的相應楔形側壁之不同直徑或寬度。然而,本發明之實施例不需要楔形側壁,且微p-n型二極體150之頂表面及底表面可具有相同的直徑或寬度以及垂直的側壁。如第12A圖至第12B圖所圖示,微LED結構陣列被描述為具有間距(P)、每一微LED結構之間的空隙(S)及每一微LED結構之最大寬度(W)。為了明晰且簡明,在俯視圖圖解中用虛線僅圖示x尺寸,但是應理解可存在類似的y尺寸且類似的y尺寸可具有相同的或不同的尺寸值。在第12A圖至第12B圖所圖示之特定實施例中,x尺寸值及y尺寸值在俯視圖圖解中係相同的。在一個實施例中,微LED結構陣列可具有10 μm之間距(P),其中每一微LED結構具有2 μm之空隙(S)及8 μm之最大寬度(W)。在另一實施例中,微LED結構陣列可具有5 μm之間距(P),其中每一微LED結構具有2 μm之空隙(S)及3 μm之最大寬度(W)。然而,本發明之實施例不局限於此等具體尺寸,且可使用任何適合尺寸。
將微LED結構傳遞至接收基板之方法的實施例係描述於第13圖中。在此實施例中,提供具有微LED結構陣列設置在該載體基板上的載體基板。如上文所描述,每一微LED結構可包括微p-n型二極體及金屬化層,其中金屬化層在微p-n型二極體與在基板上的接合層之間。等形介電質障壁層可視情況橫跨微p-n型二極體之側壁。等形介電質障壁層可另外橫跨微p-n型二極體之底表面的一部分,以及金屬化層及接合層(若存在接合層)之側壁。隨後在操作1310處,在用於微
LED結構之至少一者之接合層中產生相變。舉例而言,相變可與以下步驟相關:加熱接合層至高於形成接合層之材料的熔融溫度或液相線溫度,或者改變形成接合層之材料的晶相。隨後可在操作1320處用傳遞頭拾取微p-n型二極體及金屬化層、視情況用於微LED結構之至少一者之等形介電質障壁層的一部分,以及接合層210之可選的一部分,且隨後在操作1330處將該等經拾取的部分放置在接收基板上。
於第14圖中提供根據實施例之操作1320的一般性圖解,在第14圖中,傳遞頭300拾取微p-n型二極體、金屬化層、用於微LED結構之至少一者的等形介電質障壁層之一部分以及一部分接合層210。在所圖示的特定實施例中,已形成等形介電質障壁層,然而在其他實施例中,可能不存在等形介電質障壁層。在一些實施例中,可用微LED結構升離接合層210的一部分(諸如,近一半)。儘管圖示包括微p-n型二極體150的具體微LED結構,但是應理解,可拾取包括本文描述之微p-n型二極體150之任何微p-n型二極體150的微LED結構之任何微LED結構。另外,儘管第14圖中所圖示的實施例圖示拾取單個微LED結構的傳遞頭300,但是在其他實施例中傳遞頭300可拾取微LED結構之群組。
仍參照第14圖,在所圖示的特定實施例中,微p-n型二極體150之底表面比金屬化層120之頂表面寬,且等形介電質障壁層160橫跨微p-n型二極體150之側壁、微p-n型二極體150之底表面的一部分及金屬化層120之側壁。此情況亦可適用於微p-n型二極體135。在一個態樣中,在微p-n
型二極體135、150下部包覆的等形介電質障壁層160之部分保護微p-n型二極體150之側壁上的等形介電質障壁層160在用傳遞頭300之拾取操作期間免於碎裂或斷裂。可能在鄰近金屬化層210或接合層210之等形介電質障壁層160中,特別是在具銳角的角落及位置處產生應力點。在使微LED結構與傳遞頭300接觸及/或在接合層中產生相變後,此等應力點變成等形介電質障壁層160中的天然斷點,在此等斷點處可切割等形介電層。在一實施例中,在使微LED結構與傳遞頭接觸及/或在接合層中產生相變後,可在天然斷點處切割等形介電質障壁層160,此舉可在拾取微p-n型二極體及金屬化層之前或期間。如先前所描述,液態的接合層可回應於與使微LED結構與傳遞頭接觸相關的壓縮力在下層的結構上方變平滑。在一實施例中,在使微LED結構與傳遞頭接觸後,在接合層中產生相變之前在微LED結構之頂表面上摩擦傳遞頭。摩擦可去除可能存在於傳遞頭或微LED結構之任一者之接觸面上的任何顆粒。摩擦亦可將壓力傳遞至等形介電質障壁層。因此,將壓力從傳遞頭300傳送至等形介電質障壁層160以及加熱接合層至高於接合層之液相線溫度兩者皆可有助於在微p-n型二極體135、150下部之位置處切割等形介電質障壁層160並可保持微LED結構及量子阱層之完整性。在一實施例中,微p-n型二極體135、150之底表面比金屬化層120之頂表面寬,以使存在空間用於等形介電質障壁層160形成在微p-n型二極體135、150之底表面上並產生斷點,但是此距離亦可由微影容差決定。在一實施例中,微p-n型二極
體135、150之每一側上的0.25 μm至1 μm的距離容納50埃至600埃厚的等形介電質障壁層160。
根據本發明之實施例,可使用各種適合的傳遞頭來幫助拾取操作1320及放置操作1330。舉例而言,傳遞頭300可根據真空原理、磁學原理、黏接原理或靜電原理施加拾取壓力於微LED結構上以拾取微LED結構。
第15圖係根據本發明之實施例之雙極微元件傳遞頭的剖面側視圖圖解,該雙極微元件傳遞頭根據靜電原理操作以拾取微LED結構。如圖所示,微元件傳遞頭300可包括基底基板302、包括頂表面308及側壁306的檯面結構304、形成在檯面結構304上方並包括頂表面309及側壁307的可選鈍化層310、形成在檯面結構304(及可選鈍化層310)上方的一對電極316A、316B以及具有覆蓋電極316A、316B之頂表面321的介電層320。基底基板302可由能夠提供結構支撐的各種材料(諸如,矽、陶瓷及聚合物)形成。在一實施例中,基底基板具有103 ohm-cm與1018 ohm-cm之間的電導率。基底基板302可另外包括電線(未圖示)以將微元件傳遞頭300連接至靜電夾持器組件的工作電子裝置。
第16圖係根據本發明之實施例之接收基板400的圖解,已將複數個微LED結構放置於該接收基板400上。舉例而言,接收基板可為(但不局限於)顯示基板、發光基板、具有諸如電晶體之功能元件的基板,或具有金屬再分配線之基板。在所圖示的特定實施例中,可將每一微LED結構放置在驅動器接點410上方。共用接觸線420可隨後形成在一系
列微p-n型二極體135、150上方。如圖所示,微p-n型二極體135、150之楔形側壁可提供促進形成連續的接觸線之構形。在一實施例中,共用接觸線420可形成在一系列發紅光、發綠光或發藍光微LED上方。在某些實施例中,共用接觸線420將由透明的接點材料(諸如,銦錫氧化物(ITO))形成。在一個實施例中,複數個微LED可排列成包括發紅光微LED、發綠光微LED及發藍光微LED之三個微LED的像素群組。
仍然參照第16圖,提供根據本發明之實施例的p-n型二極體135、150的放大圖解。在一個實施例中,p-n型二極體135、150可包括具有近0.1μm-3μm之厚度的頂部n型摻雜層114、具有小於近0.3μm之厚度的量子阱層116(可為SQW或MQW),以及具有近0.1μm-1μm之厚度的下部p型摻雜層118。在一實施例中,頂部n型摻雜層114可為0.1μm-6μm厚(該頂部n型摻雜層114可包括或替換先前所描述的塊狀層112)。在一具體實施例中,p-n型二極體135、150可具有小於3μm之厚度及小於10μm之寬度。
在使用本發明之各個態樣中,熟習此項技術者將顯而易見:以上實施例之組合或變化對於形成準備被拾取並傳遞至接收基板的微LED結構陣列係可能的。儘管已經用特定於結構特微及/或方法論動作的語言描述本發明,但是應瞭解在隨附申請專利範圍中定義的本發明不必局限於所描述的具體特徵結構或動作。所揭示之具體特徵結構及動作應被理解成用於說明本發明之所主張的本發明之特別得體的實施。
160‧‧‧等形介電質障壁層
162‧‧‧接點開口
A-O‧‧‧實例
Claims (18)
- 一種形成一微發光二極體陣列的方法,該方法包含以下步驟:傳遞一p-n型二極體層及一金屬化層至一載體基板,且將該金屬化層接合至該載體基板上的一接合層,其中該接合層具有低於近350℃的液相線溫度;圖案化該p-n型二極體層以形成複數個獨立微p-n型二極體;形成橫跨該複數個獨立微p-n型二極體之側壁的一等形介電質障壁層。
- 如請求項1所述之方法,其中傳遞該p-n型二極體層及該金屬化層至該載體基板之步驟進一步包含以下步驟:從一生長基板傳遞該p-n型二極體層及該金屬化層至該載體基板上之複數個支柱。
- 如請求項1所述之方法,其中該等形介電質障壁層比該複數個獨立微p-n型二極體及該金屬化層薄。
- 如請求項3所述之方法,該方法進一步包含以下步驟:形成部分地沿每一獨立微p-n型二極體之一底表面的該等形介電質障壁層。
- 如請求項4所述之方法,該方法進一步包含以下步驟:藉由原子層沉積(ALD)形成該等形介電質障壁層。
- 如請求項1所述之方法,該方法進一步包含以下步驟:在傳遞該p-n型二極體層及該金屬化層至該載體基板之前,圖案化該載體基板上之該接合層以形成該接合層之各別複數個橫向獨立位置。
- 如請求項1所述之方法,其中傳遞該p-n型二極體層及該金屬 化層至該載體基板之步驟包含以下步驟:傳遞一圖案化金屬化層至該載體基板,其中該圖案化金屬化層包括該p-n型二極體層上之該金屬化層的複數個獨立位置。
- 如請求項2所述之方法,其中傳遞該p-n型二極體層及該金屬化層至該載體基板之步驟包含以下步驟:傳遞一圖案化金屬化層至該載體基板,其中該圖案化金屬化層包括該p-n型二極體層上之該金屬化層的複數個獨立位置。
- 如請求項8所述之方法,該方法進一步包含以下步驟:在將該p-n型二極體層及該圖案化金屬化層從該生長基板傳遞至該載體基板之前,圖案化該p-n型二極體層以形成該p-n型二極體層中之複數個微檯面。
- 如請求項8所述之方法,該方法進一步包含以下步驟:在將該p-n型二極體層及該圖案化金屬化層傳遞至該載體基板之前,在該載體基板上形成該複數個支柱。
- 如請求項10所述之方法,該方法進一步包含以下步驟:在將該p-n型二極體層及該圖案化金屬化層傳遞至該載體基板之前,在該載體基板上之該複數個支柱上方形成該接合層。
- 如請求項2所述之方法,該方法進一步包含以下步驟:在傳遞該p-n型二極體層及該金屬化層至該載體基板之後並在圖案化該p-n型二極體層以形成複數個獨立微p-n型二極體之後,圖案化該金屬化層以形成該金屬化層之各別複數個獨立位置;及圖案化該載體基板上之該接合層以形成該接合層之各別複數個橫向獨立位置。
- 如請求項12所述之方法,該方法進一步包含以下步驟:形成橫跨該複數個獨立微p-n型二極體之側壁、該複數個獨立金屬 化層之側壁,以及接合層之該複數個橫向獨立位置之側壁的該等形介電質障壁層。
- 如請求項12所述之方法,其中圖案化該金屬化層之步驟包含以下步驟:蝕刻該金屬化層直到該金屬化層之該複數個獨立位置之每一者的一最大寬度小於該複數個獨立微p-n型二極體之每一者之一底表面的一寬度。
- 如請求項12所述之方法,其中圖案化該接合層之步驟包含以下步驟:蝕刻該接合層直到該接合層之該複數個橫向獨立位置之每一者的一最大寬度小於該複數個獨立微p-n型二極體之每一者之一底表面的一寬度。
- 如請求項12所述之方法,該方法進一步包含從下步驟:在將該p-n型二極體層及該圖案化金屬化層從該生長基板傳遞至該載體基板之前,在該載體基板上形成複數個支柱。
- 如請求項16所述之方法,該方法進一步包含以下步驟:在將該p-n型二極體層及該圖案化金屬化層傳遞至該載體基板之前,在該載體基板上之該複數個支柱上方形成該接合層。
- 如請求項2所述之方法,其中圖案化該p-n型二極體層以形成複數個獨立微p-n型二極體之步驟包含薄化該p-n型二極體層。
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