TWI229435B - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device Download PDF

Info

Publication number
TWI229435B
TWI229435B TW092115930A TW92115930A TWI229435B TW I229435 B TWI229435 B TW I229435B TW 092115930 A TW092115930 A TW 092115930A TW 92115930 A TW92115930 A TW 92115930A TW I229435 B TWI229435 B TW I229435B
Authority
TW
Taiwan
Prior art keywords
film
aforementioned
manufacturing
semiconductor device
semiconductor wafer
Prior art date
Application number
TW092115930A
Other languages
English (en)
Other versions
TW200405534A (en
Inventor
Takashi Noma
Hiroyuki Shinogi
Yukihiro Takao
Original Assignee
Sanyo Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co filed Critical Sanyo Electric Co
Publication of TW200405534A publication Critical patent/TW200405534A/zh
Application granted granted Critical
Publication of TWI229435B publication Critical patent/TWI229435B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Pressure Sensors (AREA)

Description

1229435 玖、發明說明： 【發明所屬之技術領域】 本發明係關於半導體裝置之製造方法，更進一步而 言’係關於具有球狀導電端子之BGA(BaU Gdd心㈣㈣ 之半導體裝置之製造方法。 【先前技術】 BGA型半導體裝置為表面安裝型半導體裝置之一 種。此種裝置係將經由銲錫等金屬材料形成之球狀導電端 子，以格子狀方式複數排列於封裝基板之一個主面上並 與搭載於基板之其他主面上之半導體晶片接合並封裝。缺 後，於組裝於電子機器時’將各導電端子熱溶接於印刷基 板上之配線圖案，使半導體晶片與印刷基板上搭載之外部 電路電性連接。 此種BGA型之半導體裝£，相較於在半導體裝置側 面具有突出之引線接腳之s〇p(Small 〇utHne或 QFP(Quad Flat Package)等其他表面安裝型半導體裝置，可 設置更多連接端子，更有利於達到小型化之目的。 近年來，此種BGA型半導體裝置被運用在ccd影像 感測器領域’並做為内建於極需小型化之搭栽於行動電話 上的數位相機的影像感測器晶片使用。 *另外，晶圓等級的CSP(Chip package)技術與使用 Si貝通技術之三次元安裝技術也逐漸受到注目。這些技 術’ 1前正朝著將晶片貼合數層後，將Si予以貫通、或由 表面貝通Si晶圓後，向上堆積的方法等方向研究。 314700R0] 6 1229435 【發明内容】 (發明所欲解決之技術問題） #、 2疋’由於現有之三次元安裝技術為先自表面進行矽 再以銅充填貫通孔（via hole)而形成，因此表 面側必須進行 CMP(ChemiealMeehanieaipGHshing)處理， 銅’I層（Cu via)形成後必須進行連接該銅介層與鲜塾之 再配線’而有製造步驟變多之缺點。另外，使用銅的技術， 由於適合微細化作業之銅本身的成本偏高，且必須另外購 置特別的裝置’因此目前無法避免造成成本偏高的問題。 (解決問題之技術手段） 基於上述情形，本發明提供一種半導體裝置之製造方 法包括·隔著第1絕緣膜在半導體晶圓上形成金屬銲墊 之步私，隔著薄膜將前述半導體晶圓與支撐該半導體晶圓 之支撐基板貼合之步驟；蝕刻前述半導體晶圓背面而形成 ^邛後，於鈾述半導體晶圓背面與前述開口部内形成第 2絕緣膜之步驟；將前述第2絕緣膜蝕刻後，形成連接至 C金屬#塾之配線之步驟，於前述配線上形成保護膜之 步驟’於未為前述保護膜覆蓋之前述配線上形成電極之步 驟’自則述半導體晶圓背面切割至前述薄膜之步驟；以及 將前述半導體晶圓與前述支撐基板分離之步驟。 另外’本發明之半導體裝置之製造方法，係包括··隔 著第1絕緣膜在半導體晶圓上形成金屬鋅墊之步驟；隔著 薄膜將前述半導體晶圓與支撐該半導體晶圓之支撐基板貼 合之步驟；形成從前述半導體晶圓背面貫通至前述金屬銲 7 314700R01 1229435 :之：Π之步驟；在前述開口之 後，於該開口内形成金 /成弟2、.，巴緣朕 電極之步驟.自& ' 乂驟，於前述金屬膜上形成 驟；以及將、t 曰日α月面切割至前述薄膜之步 X及將刖述+導體晶圓與 ^ V ^ 、支撐基板分離之步驟。 另外，隔著薄臈將前述半導體曰士# ^ 圓之切基板貼合的步驟，#、Ha_支㈣半導體晶 撐基板中n t I k y 、則述半導體晶圓與前述支 土攸t間夾置外徑小於前 之外抑沾-^ 牛導體日日圓與前述支撐基板 貼合。 彳在周知邛利用環氧樹脂使兩者 另外’别述薄膜為可溶解於 合解於丙嗣溶液之有機系薄膜 另外，前述薄膜為有黏著性之薄膜。 另外’在使用UV膠帶作為箭；十、锋时士 ^ ^ 贡1下马刖述潯膜時，係使用透明 玻璃作為前述支撑基板，並在前述切割步驟後進行uvss 射0 …、 、…另外，具有在前述薄膜上塗抹uv系黏著劑以黏合前 达+導體晶圓與支撐基板，並在某—步驟後對前述uv系 黏著劑進行UV照射使之硬化，錢在將該半導體晶圓與 支撐基板剝離後，切割前述半導體晶圓之步驟。 另外，在前述金屬膜上形成電極之步驟中，係具有於 該金屬膜上形成金屬配線，並在該金屬配線上形成電極之 步驟。 【實施方式】 以下參照附圖說明與本發明之半導體裝置之製造方 法相關之第1實施形態。 314700R01 8 1229435 下稱作Si其/ θ所不，在膜厚大約6〇0 P的石夕晶圓（以 '反υ上形成氧化膜，在該氧化膜上形成複數的 cVD . f、· A1或是A1合金）鲜墊2a、2b，形成經由電漿 形成之Si〇2膜或是PSG膜以覆蓋住該銲墊“， 二膜併同則迷氧化膜形成預定膜厚之第】氧化膜3前述銲 a、2b與Si基板上所構成之各半導體元件連接。另外， 2別需要平坦性時，可對第1氧化膜3進行例如物理研 1〆化予蝕刻等處理。然後，以未圖式之光阻劑膜為遮罩 ，刻鲜塾2卜2b上的第1氧化膜3，使該銲墊2a、2b — 冲：(表面部)露出；之後，於銲墊2a、几表面配置鋁⑷ 或疋Α1 σ金）之第i配線4。另外在本實施形態中，前 述第1氧化膜3之膜厚，整體約為5//m。 *接著’如第2圖所示’在第！配線4的表面上形成聚 醯亞胺膜5，以未圖式之光阻劑膜為遮罩，姓刻該聚酿亞 胺膜5,並在連接前述銲塾2^之^配線4上形成開 口部。在第2圖中’係顯示在聚醯亞胺膜5的兩端部形成 該開口部之狀態。 然後，在前述開口部形成鎳（Ni)、金（Au)後，經由一 般半導體後製程所使用之電鑛裝置’在其上鍵銅（Cu)而埋 入Cu柱6。或在該Cu柱6上進行鍍金處理以防止該cu 柱6腐蝕。此外於本實施形態中’埋設於前述開口部内之 導電材料（Ni(鎳）、Au(金）、Cu(銅）、Au(金））的膜厚，整體 約2 5 // m左右。 在本發明中，如本製程非使用於三次元製程而使用於 314700R01 9 1229435 CSP製程時 部。 可王面塗抹聚醯亞胺膜5而無需形成開 基板1上：:=!酿亞胺膜5的狀態，利用黏著薄膜在si 、口後述之支撐基板8亦可。 胺膜本製程使用於CCD影像感測11時，前述聚醯亞 、 /、使用網版印刷法形成透明性之聚酸亞胺¥， 透明玻璃環氧樹脂等。 ❾胺膜，或 又，亦可採用以環氧樹脂貼合玻璃板材者。 接著，如第3圖所示，於包含前述Cu柱6(金）上之 2醯亞胺膜5上貼上黏著薄膜7，再藉由該黏著薄膜7接 合支撐基板8與前述Si基板1側。 在此，前述支撐基板8係在後述Si基板1之背面研磨 (BaCk-Grind;BG)時，防止&基板i發生龜裂等情形而使 用之支樓材’舉例來說可使用石夕基板、氧化膜（玻璃基板） 或是陶瓷等，$外，在本實施形態中，支撐材所需要的膜 厚，大約是400 # m左右。 另外，前述黏著薄膜7,基於提高後述Si基板丨與支 撐基板8之分離工杈的作業性的目的，乃採用可溶解於丙 _之有機膜。另外，在本實施形態中，黏著薄膜7之膜厚 大約為1 00 // m左右。該黏著薄膜7係配置於作為充填後 述環氧樹脂9用之晶圓邊緣内側2mm左右處。 在此，也可使用無接合力之薄膜替代黏著薄膜，在該 薄膜兩側塗上黏著劑以貼合前述支撐基板8、前述薄膜、 與前述Si基板1側。在此情形下，黏著劑可使用可溶解之 314700R01 1229435 溶劑。 第3圖（b)為弟3圖⑷之概略圖與平面圖 便係除去支撐基板8時之平面圖)。 …月方 #該黏著薄膜7之外周部，如第3®(b)所*，可藉由充 填環氧樹脂9,密封該黏著薄膜7,使其固定藉此可防止在 各=業過程中之有機溶劑等藥液之侵人在此之環氧樹脂 9亦可以疋聚醯亞胺系之樹脂。 接著，如第4圖（a)所示，對Si基板】側進行郎處理， 將该S i基板之膜展：¾胳儿 土败（胰谷存媒化至大約10至1〇〇心。此時，前 ^支撐基板8在BG工程中支樓Si基板卜然後姓刻經過 二處理…板1之背面側及第1氧化膜以形成露 出則述I于墊2a、2b之開口部K1。 另外，如第4圖（b)所示，將第2氧化膜1〇堆積於si J板…匕面側後，以未圖式之光阻劑膜為遮罩而蝕刻該 第2乳化膜10，以形成第2開口部K2。在此，第工氧化 為位於銲塾2a與銲塾以間之帛}氧化膜3的钱刻殘 刀。另外’所述第2氧化膜1〇，亦可使用氮化石夕膜或 聚醯亞胺膜等代替。 進v而a，在本實施形態中，如第4圖（a)所示，緊 接於Si基板！之钱刻步驟之後，尚有餘刻第玉氧化膜3之 步驟’在包含開口部K1之Si基板i上形成第2氧化膜， 並蝕刻疏第2氧化膜} 〇以形成開口部K2，但是，例如， 亦可藉由相當於第4圖⑷之步驟，只單獨㈣&基板i， 且在桿2"，2bT留下第1氧化膜3的狀態下，形成第2 314700R01 11 1229435 氧匕膜1〇再蝕刻該第2氧化膜10以及第1氧化膜3而 形成開口部K2。 接著，如第5圖所示，於第2氧化膜10表面之希望 =置上形成緩衝材料n，並藉由濺錢法形成可覆蓋該緩衝 材枓π之表面，第2氧化膜1()之表面，以及前述第：開 口部=2之！呂⑷或是^合金），並形成第2配線Η。另 外，第2配線丨2亦可以是銅配線。 著如第6圖所不，以未圖式之光阻劑膜為遮罩蝕 刻前述第2配線12，使第1氧化膜3a得以露出。亦即， 舜：蝕刻使鋅墊’ 2b背面之露出面可由第2配線1 2 所覆蓋、，銲墊2a，2b的端部與第2配線12之#刻斷面會 形成略為一致的情形。其結果導致，銲墊2a，2b與第2 配線12均有ί 〇 $ ，Λ A , p 、 至數100 左右之面接觸。在形成該配 各後，進行鎳（Ni)或金（Au)之無電解電鍍。 另外，亦可以鈦鎢（TiW)濺鍍取代鋁A1濺鍍，在形成 阻』後，進行銅之電解電鐘，並在除去該阻劑後，藉由姓 刻欽嫣（Tiw)層而形成第2配線12。 之後’在第2配線12表面形成銲錫遮罩（以下稱為保 )▲)在4保濩膜1 3上進行銲錫膏之網版印刷，並藉 ，/麵錫《進仃迴流焊接（refl〇w)處理，於前述第2配線 形成銲錫球（以下稱為導電端子14)。另外，在本實施 ㈣卜係使用由在攝氏2⑽度下可醯亞胺化之敷層（新日 本理化社製品）所製成《聚酿亞胺獏作為保言蔓膜！ 3。 接著進行切割（dieing)，如第7圖⑷所示;在第i氧 314700R01 12 1229435 化膜3a形成切割線D，該切割線D係為了將晶圓上之半 導體晶片個別分離而設，第7圖⑼為第7圖⑷之概略圖與 平面圖（為求說明方便，係將支撐基板8除去時之平面圖），' 在第7圖（b)之概略圖中，切割線D係形成至黏著薄膜7 之所在位置，在平面圖中，該切割線D係呈現格子狀。 之後，藉由將該Si基板丨浸泡於未圖式之丙酮溶液槽 内，如第7圖（b)所示，丙酮自前述切割線D侵入，溶解^ 述黏著薄膜7,其結果造成前述Si基板1(各晶片）與支^ 基板8自動分離，而形成如第8圖所示之單體csp晶片' 如上所述，在本實施形態中，由於係使用可溶解於丙 酮之有機系黏著薄膜7貼合Si基板i與支樓基板8，因此 在：割後’只需將Si基板卜浸泡於丙酮中即可簡單地將兩 者分離，而具有良好之作業性。 外，亦可使用黏著力較弱之薄膜取代前述黏著薄膜 7，在切割後，以物理方式將晶片剝下。更進一步而士在 使用透明玻璃作為切基板8的情形下，只要貼上^’膜 ▼做為有機系薄膜7，並在切割後進行 片剝下即可。 丹將曰曰 又，在取代黏著薄膜7而在無接合力之薄膜塗上Μ 系黏著劑以黏接前述Si基板i與支撐基板8時，亦可在某 一步驟完成後，對前述UV系黏著劑進行…照射使之硬 =將忒Si基板丨與支撐基板8相剝離後，再切割Si基 自晶圓背面以 除此之外，亦可在進行切割後，例如 3i470〇R〇] 13 1229435 加熱片加熱，使晶圓盥古 7)溶解軟化後，再將樓基板8之間的有機膜（黏著薄膜 时兩者相剝離。此時， 溶解於丙酮之有機膜_ 钻者溥膜7為可 利用聚酿亞胺膜時，、攝氏200度左右的加熱，而 該黏著薄膜7溶解，要攝氏4〇°度左右的加熱才可使 在剝離Si基板1與支樓基板8的其他形能中，尚有· η ^啄之衣虱樹脂，以使晶圓縱向回轉，並只 將外圍部分浸泡於酿~丨 包於& (例如硫酸）等藥品中予以剝離之方 法0 二卜’在直接剝離Si基板1與支撑基板8的方法中， =舉使用m子、小刀#銳利物將邊緣外圍 樹脂部分削除的方法，或 $對矽日日®整體進行研磨以削除該 口P刀而將兩者剝離等方法。 接著，如第9圖中所+ , ,.H 斤不，本發明第2實施形態，係藉 由孟屬密接Cu柱6以及導恭唑工 /WBL、 子14使CSP晶片彼此密接 (豐層)，而得以使前述單體csp晶片(第8圖中之切開後的 +導體装置）完成三次元安裳（無論幾層皆可），只要是 晶片大小相同（如記憶體等）即可達到大容量化。 以下，參照附圖說明本發明之半導體裝置之製造方法 之第3實施形態。 首先’如第10圖（a)所示，在膜厚約6〇〇//111之矽晶圓 (以下稱作Sl基板）1〇1上形成氧化膜，於該氧化膜上形成 玉屬（例如A1或疋A1合金）銲塾1〇2，並形成藉由電聚cvd 法所形成Si〇2膜或是PSG膜以覆蓋該録墊1()2，將此膜與 314700R0] 14 1229435 丽述氧化膜合併以形成預定膜厚之 前述銲墊102係與Si基板1〇1 乳M 103°另外， 接。此外，特別需要平坦性時，例/成之半導體元件連 ⑻進行物理研磨或是化學㈣等處理。H第〗氧化膜 之光阻劑膜為遮罩，對銲墊1〇 /以未圖式 Μ办丨放—》日批 弟1氧化膜1 03進杆 蝕刻使，亥鋅墊102之一部份 汐彬能士 “丄 1 )路出。另外，在本實 她形您中，珂述第i氧化膜 不只 左右。 ，全體約為5//m 接著’如第1〇圖(b)所示，在前述鲜塾ι〇2及第】氧 化膜1 03上形成聚醯亞胺膜，以 而對該聚醯^ 1 I 圖式之光阻劑膜為遮罩 門二丁❹於前述銲墊102上形成具有 L二:膜104,之後，在前述開口部内形成錄 二（AU)1G6後’在其上鍍銅（Cu)而埋人柱⑽。 另外’在該Cu才主1 〇7 食*-r m /v 蚀。另外，在太〜， (AU)以防止〜柱107腐 貫她形怨中，前述開口部内所埋設之導電 材料（錄、金、铜、令彳夕胳陪 刃金）之膜厗，全體約為25# m左右。 在此，如本製程係使用於CCD影像感測器時，前述聚 酷亞胺膜1〇4必須使用網版印刷法形成具透明性之聚醯亞 月*膜或透明玻璃環氧樹脂等。 亦可採用以環氧樹脂貼合玻璃板材者。 =進步而言，本製程非運用於三次元製程而運用於 CSP衣辁蚪，無須形成開口部，而可全面塗布聚醯亞胺膜 104 〇 、 在’又有聚亞胺膜1 〇 4的狀態，利用黏著薄膜在 15 314700R01 1229435
Si基板101上貼合後述之支撐基板lu亦可。 另：，如第17圖⑷所示，本發明第4實施形態，係 於包含前述銲墊102上之第1氧化膜103上形成Tiw⑵， 並進行圖案化使之形成預定圖案。之後，形成聚醯亞胺膜 104A，並於形成於該聚醯亞胺膜1〇4八之開口部上形成α 柱107Α(以及Au)，亦即可採用所謂的再配線構造。 接著，如第11圖⑷所示，於包含前述Cu柱ι〇7(以及 上之聚醯亞胺膜104上貼合黏著薄臈11〇，藉由該黏 者薄膜110將支撐基板lu與前述Si基板1〇1側貼合。 在此，前述支撐基板U1係在後述Si基板101之背面 研磨（BG)時防止Si基板1〇1龜裂之支撐材，可使用例如y 基板、氧化膜（玻璃基板）、陶瓷等。另外，在本實施形態 中，支撐材所必要之膜厚，約為4〇〇// m左右。 另外’ W述黏著薄膜11〇，為提高後述之Si基板1〇1 與支撐基板1 1 1之分離步驟的作業效率，而採用可溶解於 丙酮之有機膜。另外，在本實施形態中，黏著薄膜11 〇之 膜厚約為100# m左右。該黏著薄膜110，係配置於作為充 填後述之環氧樹脂11 2之晶圓邊緣内側2 m m左右處。 在此’亦可使用無接合力之薄膜以代替黏著薄膜，而 於該薄膜兩面塗上黏著劑，以貼合前述支撐基板u 2、前 述薄膜以及前述Si基板1 0 1。在此情況下，只需使用可溶 解黏著劑之溶劑。 第11圖（b)為第11圖（a)之概略圖與平面圖（為求說明 之方便’係除去支撑基板111時之平面圖）。 16 314700R0] 1229435 在該黏著薄膜110之外圍部，如第11圖（]3)所示藉由 充真環氧樹脂1 1 2，岔封该黏著薄膜1 1 〇，將其固定。並藉 此防止在各種作業中產生有機溶劑等藥液之侵入。 接著’如第1 2圖（a)所示對si基板1 ο 1側進行BG處 理’使該Si基板1 0 1薄膜化至大約1 〇至1 〇〇 #历左右的 膜厚。此時，前述支撐基板111係用以在BG工程中支撲 Si基板ι〇1。之後，在經過BG處理之si基板1〇1的背面 側形成約0·01 μ m左右之第2氧化膜U3。另外，亦可形 成由氮化矽膜或聚醯亞胺所構成之有機系絕緣物以取代前 述第2氧化膜113。更進一步而言，在前述BGi程中， 因不受銅上之平坦性影響，可直接進行背面研磨bg，故 作業性良好。 另外，如第1 2圖（b)所示，以未圖式之光阻劑膜為遮 罩對前述第2氧化膜113以及Si基板1〇1進行蝕刻以形成 開口邛11 4。接著，如第1 3圖（a)所示對自前述開口部工i 4 露出之第1氧化膜103進行蝕刻，使前述銲墊1〇2露出。 之後，形成經由CVD法所形成之第3氧化膜以覆蓋在包含 開口部114a内之前述銲墊102上之第二氧化膜ιΐ3上，對 該第3氧化膜進行異向性蝕刻，使第3氧化膜於開口部 114a之側壁部殘膜化而形成側壁間隔膜115。另外，第3 氧化膜之CVD成膜處理溫度，以攝氏2〇〇度左右之低溫為 佳。此外，亦可使用氮化矽膜來形成側壁間隔膜丨丨5。 接著，如第1 3圖（b)所示，隔著側壁間隔膜i丨5於前 述開口部11 4a内濺鍍形成氮化鈦（TiN)或是氮化鈕（TaN)等 314700R01 17 1229435 阻障膜m，藉由該阻障膜116於前述開口部"4a内埋設 Cu以形成Cu埋入層117。另外，在本步驟中，首先需在又 阻障膜116上進行種銅、㈣處理，並對該銅進行退1處 理。之後’將該銅埋設於開口部U4a内。在此，如需特： 要求平坦性’可對該Cu進行CMP研磨。 另外，如第14圖（a)所示於前述Cu埋入層ιΐ7上形 成其開口大小較埋設有該銅埋入層117之開口部之開 口稍大的銲錫遮罩118 ’藉由該遮罩118於該開口上進行 銲錫膏之網版㈣，再藉由冑該銲錫膏進行迴流焊接處 理，而於Cu埋入層117上形成銲錫球119。另外，在本實 施形態中’係使用在攝氏度下會產生醯亞胺化之敷層 所形成之聚醯亞胺膜作為銲錫遮罩丨丨8。 曰 另外，亦可採用如第丨7圖（b)中所示本發明之第$實 施形態’於包含前述Cu埋入層117上之第2氧化膜η: 上形成Α1膜131以及Ni膜（以及Au膜）132，將其圖案化 使其形成預定圖案，然後’藉由銲錫遮罩118八形成銲錫 球119A之構造。 接著’如第14圖（b)所示，切割前述Si基板1〇丨側直 至到達前述黏著薄膜之位置。 之後，藉由將該Si基板1〇1浸泡於未圖式之丙酮溶液 槽内’如帛15圖（b)所示丙酮會自前述切割線β侵入，而 溶解前述黏著薄膜11G。因此，前述Si基板igi(各晶片） 與支撐基板111會自動分離，而形成如第15圖⑷所示之 早體CSP晶片120。 314700R01 】8 1229435 如上所述，在本實施形態中，由於係使用可溶解於丙 _之有機系黏著薄膜11 〇則合Si基板1 0 1與支擇基板 ，因此切割後，只需將Si基板ιοί浸泡於丙酮中便可 簡單地將兩者分離，而具有良好之作業性。 另外，亦可使用黏著力較弱之薄膜代替前述黏著薄膜 11 〇，而於切割後，以物理性方法將晶片剝離。更進一步而 5 ’使用透明玻璃作為支撑基板111時，亦可貼上UV膠 ▼做為有機系黏著薄膜丨丨〇，並在切割後進行照射， 使晶片剝離。 又，在取代黏著薄膜110而在無接合力之薄膜塗上uv 系黏著劑以黏接前Si基板101與支撐基板lu時，亦可在 某一步驟之後，對前述UV系黏著劑進行UV照射使之硬 化而將該Si基板101與支撐基板u i相剝離後，再切割Si 基板1 0 1。 另外，亦可在完成切割後，例如，自晶圓背面以加熱 片加熱，將晶圓與支撐基板ln之間的有機膜（黏著薄膜 11 0)溶解軟化，再將兩者剝離。此時，當黏著薄膜i丨〇為 可溶解於丙酮之有機系薄膜時，只需加熱至攝氏200度左 右，若使用聚醯亞胺膜則加熱至攝氏400度左右，即可使 該黏著薄膜11 〇溶解。 在剝離Si基板101與支撐基板U1之其他形態中，亦 有在切割丽，將邊緣的環氧樹脂，以使晶圓縱向回轉，並 只將外圍部分浸泡於酸等藥品中予以剝離之方法。另外， 尚有：將銳利物插入晶圓與晶片間之邊緣的環氧樹脂中而 19 314700R01 1229435 使之分離的方法。然後，在該兩種方法之後，貼上B(J膠 帶進行切割。 之後，如第16圖所示，藉由金屬密接cu柱107(以及 Au)與銲錫球119使CSP晶片120彼此密接（疊層），可使前 述單體CSP晶片120完成三次元安裝（無論幾層皆可），只 要晶片大小相同（如記憶體等）即可達到大容量化之目的。 【發明之效果】 在本發明中，由於係使用一般在安裝領域所採用之賤 鑛裝置與電鍍裝置形成配線，故可實現成本低且製程簡單 之半導體裝置。 另外，並不像現行之三次元安裝技術一般，自表面進 行S i貝通荨加工，再以c u充填貫通孔，故在本實施形態 中’然須進行過去所必要之表面側的CMP處理，而得以減 少步驟數。 另外，由於積層構造中，在形成銅介層（Cu via)後即無 須進行用以連接該銅介層與銲墊之再配線，故不會增加製 造工數。 另外，支撐基板與Si基板，係在接合後均進行BG(背 面研磨）及其後之處理，故可使晶片膜厚達到最薄的程度。 【圖式簡單說明】 第1圖係顯示本發明之第1實施形態之半導體裝置之 製造方法之剖面圖。 第2圖係顯示本發明之第1實施形態之半導體裝置之 20 314700R0] 1229435 製造方法之剖面圖。 第3圖(a)及(b)係顯示本發明之第丄實施形態之半導體 裝置之製造方法之剖面圖。 第4圖⑷及(b)係顯示本發明之第1實施形態之半導體 裝置之製造方法之剖面圖。 第5圖係顯示本發明之第1實施形態之半導體裝置之 製造方法之剖面圖。 第6圖係—不本發明之第1實施形態之半導體裝置之 製造方法之剖面圖。 第7圖⑷及（b)係顯示本發明之第1實施形態之半導體 裝置之製造方法之剖面圖。 第8圖係顯示本發明之第1實施形態之半導體裝置之 製造方法之剖面圖。 第9圖係顯示本發明之第2實施形態之半導體裝置之 製造方法之剖面圖。 第10圖(a)及(b)係顯示本發明之第3實施形態之半導 體裂置之製造方法之剖面圖。 第11圖⑷及（b)係顯示本發明之第3實施形態之半導 體裳置之製造方法之剖面圖。 第12圖（a)及（b)係顯示本發明之第3實施形態之半導 體裳置之製造方法之剖面圖。 第13圖（a)及（b)係顯示本發明之第3實施形態之半導 體裝置之製造方法之剖面圖。 第14圖（a)及（b)係顯示本發明之第3實施形態之半導 21 314700R01 1229435 體裝置之製造方法之剖面圖。 第15圖（a)及（b)係顯示本發明之第3實施形態之半導 體裝置之製造方法之剖面圖。 第1 6圖係顯示本發明之第3實施形態之半導體裝置 之製造方法之剖面圖。 第17圖（a)及（b)係顯示本發明之第4及第5實施形態 之半導體裝置之製造方法之剖面圖。 1 Si基板 2a 銲墊 2b 銲墊 3 第1氧化膜 3a 第1氧化膜 4 第1配線 5 聚醯亞胺膜 6 Cu柱 7 黏著薄膜 8 支禮基板 9 環氧樹脂 10 第2氧化膜 11 緩衝構件 12 第2配線 13 保護膜 14 導電端子 ΚΙ 開口部 K2 開口部 D 切割線 101 Si基板 102 銲墊 103 第1氧化膜 104 聚醯亞胺膜 104A 聚醯亞胺膜 105 鎳（Ni) 106 金（Au) 107 銅（Cu) 110 黏著薄膜 111 支樓基板 112 環氧樹脂 1 13 第2氧化膜 114 開口部 22 314700R01 1229435 114a 開口部 115 側壁間隔膜 116 阻擋膜 117 Cu埋入層 118 銲錫遮罩 118A 銲錫遮罩 119 鲜錫球 119A 鲜錫球 120 CSP晶片 121 鈦鎢（TiW) 131 A1膜 132 Ni膜及Au膜 23 314700R01

Claims (1)

1229435 拾、申請專利範圍： 1. 一種半導體裝置之製造方法，包括： 隔著第1絕緣膜在半導體晶圓上形成金屬銲墊之 步驟； 隔著薄膜將前述半導體晶圓與支撐該半導體晶圓 之支撐基板貼合之步驟； 膜之步驟； 姓d 4)述半導體晶圓之背面而形成開口部後，在肯 述半‘肢日日圓之背面以及前述開口部内形成第2絕緣 將則述第2絕緣膜姓刻後，形成連接至前述金屬 墊之配線之步驟； 在前述配線上形成保護膜之步驟； 在未為别述保護膜覆蓋之前述配線上形成電極 銲 步驟； 之 及 自前述半導體晶圓背面切 割至前述薄膜之步驟，·以 將前述半導體㈣與前述支撐基板分離之步驟。 2.t 利範圍第1項之半導體裝置之製造方法，其 圓之=㈣？前述半導體晶圓與支撑該半導心 端部使=-反貼°之步驟’係僅在前述半導體晶圓的眉 3 邛使用衣乳树脂使兩者貼合之步驟。 I申：3圍第1項之半導體裝置之製造方法，其 4·如申二圍為I溶解於丙酮溶液之有機系薄膜。 巳圍弟1項之半導體裝置之製造方法，其 314700R01 24 435 435 中 前述薄膜具有黏著性。 :申請專利範圍第！項之半導體裳置之製造方法，呈 使用uv膠帶作為前述薄膜時，係使用透明玻璃 為則述支撐基板，並在前述切割步驟後進行uv照 如申請專利範圍第2項之半導體裝置之製造方法，其 中，將前述環氧樹脂以使用刀片、鋸子、小刀等銳利物 之物理方式剝離’使前述半導體晶圓與前述支樓基板分 如申請專利範圍第2項之半導體裝置之製造方法，其 :/系將刖述半導體晶圓浸泡至酸中，以將前述環氧樹 月曰冷解之化學#式剥離，使前述半導體晶圓與前述支樓 基板分離。 如申請專利範圍第2項之半導體裝置之製造方法，其 =，係對前述半導體晶圓整體之周邊部進行研磨，削去 I述環氧樹脂部分，使前述半導體晶圓與前述支撐基板 刀離。 如申請專利範圍第1項之半導體裝置之製造方法，其 中’則述配線係在形成鋁後經由鍍鎳及鍍金而形成。 如申請專利範圍第1項之半導體裝置之製造方法，其 中’則述配線係在形成鈦鎢後經由鍍銅而形成。 如申請專利範圍第1項之半導體裝置之製造方法，其 中係在前述半導體晶圓背面形成開口部前，先對該背 面進行研磨。 25 314700R01 1229435 12·如申請專利範圍第1項之半導體裝置之製造方法，其 中’曰具有形成在前述金屬銲墊上形成配線，以及在該金 屬銲墊上之配線上形成電極連接用之金屬柱之步驟。 1 3.如申凊專利範圍第！項之半導體裝置之製造方法，其 中係在岫述薄膜上塗抹UV系黏著劑以黏合前述半導 體日日圓及支撐基板，然後進行UV照射。 I4· 一種半導體裝置之製造方法，包括·· 隔者第1絕緣膜於半導體晶圓上形成金屬銲墊之 步驟； 隔著薄膜將前述半導體晶圓與支撐前述半導體晶 圓之支撐基板貼合之步驟； 形成從前述半導體晶圓背面貫通至前述金屬銲塾 之開口之步驟； 在前述開口之側壁部形成帛2絕緣膜後，在該開口 内形成金屬膜之步驟； 在前述金屬膜上形成電極之步驟； 自則述半導體晶圓背面切割至前述薄膜之步驟；以 及 將前述半導體晶圓與前述支撐基板分離之步驟。 15.如申請專利範圍第14項之半導體裝置之製造方法，其 中’隔著薄膜將前述半導體晶圓與支撑該半導體晶圓之 支撐基板貼合的步驟，係在前述半導體晶圓與前述支撐 基板中間夹置外徑小於前述半導體晶圓與前述支撐基 板之外徑㈣膜的狀態下，僅在周端部利用環氧樹脂使 314700R01 26 1229435 兩者貼合。 16.=申料利範圍第14項之半導體裝置之製造方法，其 中由河述薄膜為可溶解於丙酮溶液之有機系薄膜。 .。申凊專利範圍第14項之半導體裝置之製造方法，其 中，丽述薄膜為有黏著性之薄膜。 士申1專利圍第14項之半導體裝置之製造方法，其 中二使用UV膠帶作為前述薄膜時，係使用透明玻螭作 為則述支樓基板’並在前述切割步驟後進行UV照射。 19.如申請：利範圍第14項之半導體裝置之製造方法，其 中，在前述金屬膜上形成電極之步驟，具有於該金屬祺 上形成金屬配線’並在該金屬配線上形成電極之步驟。 20·如申請專利範圍第14項之半導體裝置之製造方法，其 中，係在前述半導體晶圓背面内形成開口前，先對該背 面進行研磨。 21·如申請專利範圍第14項之半導體裝置之製造方法，其 中，具有於前述金屬銲墊上形成電極連接用之金屬柱之 步驟。 22.如申請專利範圍第14項之半導體裝置之製造方法，其 中’係在前述薄膜上塗抹UV系黏著劑以黏合前述半導 體晶圓及支撑基板，然後進行UV照射。 27 314700R01
TW092115930A 2002-06-18 2003-06-12 Manufacture of semiconductor device TWI229435B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002176775 2002-06-18

Publications (2)

Publication Number Publication Date
TW200405534A TW200405534A (en) 2004-04-01
TWI229435B true TWI229435B (en) 2005-03-11

Family

ID=29717459

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092115930A TWI229435B (en) 2002-06-18 2003-06-12 Manufacture of semiconductor device

Country Status (5)

Country Link
US (2) US6864172B2 (zh)
EP (2) EP2207198A3 (zh)
KR (1) KR100552356B1 (zh)
CN (2) CN100474573C (zh)
TW (1) TWI229435B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI479622B (zh) * 2011-11-15 2015-04-01 Xintec Inc 晶片封裝體及其形成方法

Families Citing this family (150)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI232560B (en) * 2002-04-23 2005-05-11 Sanyo Electric Co Semiconductor device and its manufacture
TWI229435B (en) 2002-06-18 2005-03-11 Sanyo Electric Co Manufacture of semiconductor device
US7399683B2 (en) * 2002-06-18 2008-07-15 Sanyo Electric Co., Ltd. Manufacturing method of semiconductor device
JP2004095849A (ja) * 2002-08-30 2004-03-25 Fujikura Ltd 貫通電極付き半導体基板の製造方法、貫通電極付き半導体デバイスの製造方法
TWI227550B (en) * 2002-10-30 2005-02-01 Sanyo Electric Co Semiconductor device manufacturing method
JP4071615B2 (ja) * 2002-12-20 2008-04-02 株式会社フジクラ 貫通電極の形成方法及び貫通電極付き基板
JP4401181B2 (ja) * 2003-08-06 2010-01-20 三洋電機株式会社 半導体装置及びその製造方法
US7180149B2 (en) * 2003-08-28 2007-02-20 Fujikura Ltd. Semiconductor package with through-hole
DE10340409B4 (de) * 2003-09-02 2007-05-24 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Trägerwafer und Verfahren zum Bearbeiten eines Halbleiterwafers unter Verwendung eines Trägerwafers
EP1517166B1 (en) * 2003-09-15 2015-10-21 Nuvotronics, LLC Device package and methods for the fabrication and testing thereof
US6934065B2 (en) * 2003-09-18 2005-08-23 Micron Technology, Inc. Microelectronic devices and methods for packaging microelectronic devices
TWI226090B (en) * 2003-09-26 2005-01-01 Advanced Semiconductor Eng Transparent packaging in wafer level
KR100529672B1 (ko) * 2003-10-02 2005-11-17 동부아남반도체 주식회사 이미지 센서의 백 그라인딩 방법
US7081411B2 (en) * 2003-10-18 2006-07-25 Northrop Grumman Corporation Wafer etching techniques
US8084866B2 (en) 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
US7091124B2 (en) 2003-11-13 2006-08-15 Micron Technology, Inc. Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
US7583862B2 (en) * 2003-11-26 2009-09-01 Aptina Imaging Corporation Packaged microelectronic imagers and methods of packaging microelectronic imagers
US20050147489A1 (en) * 2003-12-24 2005-07-07 Tian-An Chen Wafer supporting system for semiconductor wafers
JP4850392B2 (ja) * 2004-02-17 2012-01-11 三洋電機株式会社 半導体装置の製造方法
JP2005235860A (ja) 2004-02-17 2005-09-02 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP4307284B2 (ja) * 2004-02-17 2009-08-05 三洋電機株式会社 半導体装置の製造方法
TWI249767B (en) 2004-02-17 2006-02-21 Sanyo Electric Co Method for making a semiconductor device
US7253397B2 (en) 2004-02-23 2007-08-07 Micron Technology, Inc. Packaged microelectronic imagers and methods of packaging microelectronic imagers
JP2005303258A (ja) * 2004-03-16 2005-10-27 Fujikura Ltd デバイス及びその製造方法
US20050247894A1 (en) 2004-05-05 2005-11-10 Watkins Charles M Systems and methods for forming apertures in microfeature workpieces
US8092734B2 (en) * 2004-05-13 2012-01-10 Aptina Imaging Corporation Covers for microelectronic imagers and methods for wafer-level packaging of microelectronics imagers
US7253957B2 (en) * 2004-05-13 2007-08-07 Micron Technology, Inc. Integrated optics units and methods of manufacturing integrated optics units for use with microelectronic imagers
US20050275750A1 (en) 2004-06-09 2005-12-15 Salman Akram Wafer-level packaged microelectronic imagers and processes for wafer-level packaging
US7498647B2 (en) 2004-06-10 2009-03-03 Micron Technology, Inc. Packaged microelectronic imagers and methods of packaging microelectronic imagers
US7262405B2 (en) * 2004-06-14 2007-08-28 Micron Technology, Inc. Prefabricated housings for microelectronic imagers
US7199439B2 (en) * 2004-06-14 2007-04-03 Micron Technology, Inc. Microelectronic imagers and methods of packaging microelectronic imagers
KR100618543B1 (ko) * 2004-06-15 2006-08-31 삼성전자주식회사 웨이퍼 레벨 적층 패키지용 칩 스케일 패키지 제조 방법
US7294897B2 (en) * 2004-06-29 2007-11-13 Micron Technology, Inc. Packaged microelectronic imagers and methods of packaging microelectronic imagers
US7232754B2 (en) * 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US7416913B2 (en) * 2004-07-16 2008-08-26 Micron Technology, Inc. Methods of manufacturing microelectronic imaging units with discrete standoffs
JP4376715B2 (ja) * 2004-07-16 2009-12-02 三洋電機株式会社 半導体装置の製造方法
US7189954B2 (en) * 2004-07-19 2007-03-13 Micron Technology, Inc. Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers
US7402453B2 (en) * 2004-07-28 2008-07-22 Micron Technology, Inc. Microelectronic imaging units and methods of manufacturing microelectronic imaging units
JP4322181B2 (ja) * 2004-07-29 2009-08-26 三洋電機株式会社 半導体装置の製造方法
US20060023107A1 (en) * 2004-08-02 2006-02-02 Bolken Todd O Microelectronic imagers with optics supports having threadless interfaces and methods for manufacturing such microelectronic imagers
US7364934B2 (en) 2004-08-10 2008-04-29 Micron Technology, Inc. Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US7397066B2 (en) * 2004-08-19 2008-07-08 Micron Technology, Inc. Microelectronic imagers with curved image sensors and methods for manufacturing microelectronic imagers
US7223626B2 (en) * 2004-08-19 2007-05-29 Micron Technology, Inc. Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-level packaging of imagers
DE602005019581D1 (de) * 2004-08-20 2010-04-08 Nxp Bv Verfahren zum ablösen einer dünnen halbleiterschaltung von ihrer basis
US7429494B2 (en) * 2004-08-24 2008-09-30 Micron Technology, Inc. Microelectronic imagers with optical devices having integral reference features and methods for manufacturing such microelectronic imagers
US7425499B2 (en) * 2004-08-24 2008-09-16 Micron Technology, Inc. Methods for forming interconnects in vias and microelectronic workpieces including such interconnects
US7115961B2 (en) * 2004-08-24 2006-10-03 Micron Technology, Inc. Packaged microelectronic imaging devices and methods of packaging microelectronic imaging devices
US7276393B2 (en) * 2004-08-26 2007-10-02 Micron Technology, Inc. Microelectronic imaging units and methods of manufacturing microelectronic imaging units
SG120200A1 (en) * 2004-08-27 2006-03-28 Micron Technology Inc Slanted vias for electrical circuits on circuit boards and other substrates
US7419852B2 (en) * 2004-08-27 2008-09-02 Micron Technology, Inc. Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies
US20070148807A1 (en) 2005-08-22 2007-06-28 Salman Akram Microelectronic imagers with integrated optical devices and methods for manufacturing such microelectronic imagers
US7511262B2 (en) * 2004-08-30 2009-03-31 Micron Technology, Inc. Optical device and assembly for use with imaging dies, and wafer-label imager assembly
US7646075B2 (en) * 2004-08-31 2010-01-12 Micron Technology, Inc. Microelectronic imagers having front side contacts
US7491582B2 (en) * 2004-08-31 2009-02-17 Seiko Epson Corporation Method for manufacturing semiconductor device and semiconductor device
JP2006071486A (ja) * 2004-09-02 2006-03-16 Renesas Technology Corp 接続装置、半導体チップ検査装置および半導体装置の製造方法
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
TWI267183B (en) 2004-09-29 2006-11-21 Sanyo Electric Co Semiconductor device and manufacturing method of the same
JP4966487B2 (ja) * 2004-09-29 2012-07-04 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
JP4246132B2 (ja) * 2004-10-04 2009-04-02 シャープ株式会社 半導体装置およびその製造方法
TWI303864B (en) 2004-10-26 2008-12-01 Sanyo Electric Co Semiconductor device and method for making the same
JP4443379B2 (ja) 2004-10-26 2010-03-31 三洋電機株式会社 半導体装置の製造方法
JP4873517B2 (ja) 2004-10-28 2012-02-08 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
US7271482B2 (en) * 2004-12-30 2007-09-18 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US20060162850A1 (en) * 2005-01-24 2006-07-27 Micron Technology, Inc. Methods and apparatus for releasably attaching microfeature workpieces to support members
US7214919B2 (en) * 2005-02-08 2007-05-08 Micron Technology, Inc. Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US20060177999A1 (en) * 2005-02-10 2006-08-10 Micron Technology, Inc. Microelectronic workpieces and methods for forming interconnects in microelectronic workpieces
US7303931B2 (en) * 2005-02-10 2007-12-04 Micron Technology, Inc. Microfeature workpieces having microlenses and methods of forming microlenses on microfeature workpieces
US7190039B2 (en) * 2005-02-18 2007-03-13 Micron Technology, Inc. Microelectronic imagers with shaped image sensors and methods for manufacturing microelectronic imagers
US7485967B2 (en) 2005-03-10 2009-02-03 Sanyo Electric Co., Ltd. Semiconductor device with via hole for electric connection
JP4097660B2 (ja) * 2005-04-06 2008-06-11 シャープ株式会社 半導体装置
DE102005022017B3 (de) * 2005-05-12 2006-10-26 Infineon Technologies Ag Verfahren zur Herstellung von Chip-Stapeln sowie zugehörige Chip-Stapel
JP4311376B2 (ja) 2005-06-08 2009-08-12 セイコーエプソン株式会社 半導体装置、半導体装置の製造方法、電子部品、回路基板及び電子機器
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US20060290001A1 (en) * 2005-06-28 2006-12-28 Micron Technology, Inc. Interconnect vias and associated methods of formation
US7169248B1 (en) * 2005-07-19 2007-01-30 Micron Technology, Inc. Methods for releasably attaching support members to microfeature workpieces and microfeature assemblies formed using such methods
US7485968B2 (en) * 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
US7288757B2 (en) * 2005-09-01 2007-10-30 Micron Technology, Inc. Microelectronic imaging devices and associated methods for attaching transmissive elements
US7863187B2 (en) * 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7772116B2 (en) * 2005-09-01 2010-08-10 Micron Technology, Inc. Methods of forming blind wafer interconnects
US7262134B2 (en) 2005-09-01 2007-08-28 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
JP4745007B2 (ja) * 2005-09-29 2011-08-10 三洋電機株式会社 半導体装置及びその製造方法
US20080217715A1 (en) * 2005-10-11 2008-09-11 Park Tae-Seok Wafer Level Package Using Silicon Via Contacts for Cmos Image Sensor and Method of Fabricating the Same
DE102005053494A1 (de) * 2005-11-09 2007-05-16 Fraunhofer Ges Forschung Verfahren zum Herstellen elektrisch leitender Durchführungen durch nicht- oder halbleitende Substrate
TWI324800B (en) * 2005-12-28 2010-05-11 Sanyo Electric Co Method for manufacturing semiconductor device
TW200737506A (en) * 2006-03-07 2007-10-01 Sanyo Electric Co Semiconductor device and manufacturing method of the same
US7749349B2 (en) * 2006-03-14 2010-07-06 Micron Technology, Inc. Methods and systems for releasably attaching support members to microfeature workpieces
JP4812512B2 (ja) * 2006-05-19 2011-11-09 オンセミコンダクター・トレーディング・リミテッド 半導体装置の製造方法
US7749899B2 (en) 2006-06-01 2010-07-06 Micron Technology, Inc. Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces
TWI367557B (en) * 2006-08-11 2012-07-01 Sanyo Electric Co Semiconductor device and manufaturing method thereof
US7629249B2 (en) 2006-08-28 2009-12-08 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
US7829438B2 (en) 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
US7901989B2 (en) * 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
JP5010247B2 (ja) * 2006-11-20 2012-08-29 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US7791199B2 (en) * 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
US7952195B2 (en) * 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
US7679187B2 (en) * 2007-01-11 2010-03-16 Visera Technologies Company Limited Bonding pad structure for back illuminated optoelectronic device and fabricating method thereof
DK1962344T3 (da) * 2007-02-25 2012-07-02 Samsung Electronics Co Ltd Emballager til elektroniske indretninger og fremgangsmåder til fremstilling
JP5584474B2 (ja) 2007-03-05 2014-09-03 インヴェンサス・コーポレイション 貫通ビアによって前面接点に接続された後面接点を有するチップ
US8232183B2 (en) * 2007-05-04 2012-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Process and apparatus for wafer-level flip-chip assembly
JP5101157B2 (ja) * 2007-05-07 2012-12-19 オンセミコンダクター・トレーディング・リミテッド 半導体装置の製造方法
JP2009021462A (ja) * 2007-07-13 2009-01-29 Disco Abrasive Syst Ltd ウェーハの加工方法
US8461672B2 (en) 2007-07-27 2013-06-11 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
JP2010535427A (ja) * 2007-07-31 2010-11-18 テッセラ，インコーポレイテッド 貫通シリコンビアを使用する半導体実装プロセス
KR101533663B1 (ko) 2007-08-03 2015-07-03 테세라, 인코포레이티드 재구성된 웨이퍼를 이용한 스택 패키지
US8043895B2 (en) 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
SG150410A1 (en) 2007-08-31 2009-03-30 Micron Technology Inc Partitioned through-layer via and associated systems and methods
US7884015B2 (en) 2007-12-06 2011-02-08 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
JP5271562B2 (ja) * 2008-02-15 2013-08-21 本田技研工業株式会社 半導体装置および半導体装置の製造方法
US20100053407A1 (en) * 2008-02-26 2010-03-04 Tessera, Inc. Wafer level compliant packages for rear-face illuminated solid state image sensors
US20090212381A1 (en) * 2008-02-26 2009-08-27 Tessera, Inc. Wafer level packages for rear-face illuminated solid state image sensors
EP2308087B1 (en) 2008-06-16 2020-08-12 Tessera, Inc. Stacking of wafer-level chip scale packages having edge contacts
DE102009005458B4 (de) * 2009-01-21 2010-09-30 Austriamicrosystems Ag Halbleiterbauelement mit Durchkontaktierung und Verfahren zu dessen Herstellung
US20100194465A1 (en) * 2009-02-02 2010-08-05 Ali Salih Temperature compensated current source and method therefor
KR20120068985A (ko) 2009-03-13 2012-06-27 테세라, 인코포레이티드 본드 패드를 통과하여 연장된 비아를 갖는 마이크로전자 소자를 포함하는 적층형 마이크로전자 어셈블리
EP2306506B1 (en) * 2009-10-01 2013-07-31 ams AG Method of producing a semiconductor device having a through-wafer interconnect
TWI497658B (zh) * 2009-10-07 2015-08-21 Xintec Inc 晶片封裝體及其製造方法
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
JP2012039005A (ja) * 2010-08-10 2012-02-23 Toshiba Corp 半導体装置およびその製造方法
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
KR101059490B1 (ko) 2010-11-15 2011-08-25 테세라 리써치 엘엘씨 임베드된 트레이스에 의해 구성된 전도성 패드
US8455984B2 (en) * 2010-11-15 2013-06-04 Nanya Technology Corp. Integrated circuit structure and method of forming the same
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
KR20120077876A (ko) * 2010-12-31 2012-07-10 삼성전자주식회사 이종 기판 접합 구조 및 방법
KR20120135626A (ko) * 2011-06-07 2012-12-17 삼성전자주식회사 반도체 칩 패키지의 제조 방법
DE102011112659B4 (de) * 2011-09-06 2022-01-27 Vishay Semiconductor Gmbh Oberflächenmontierbares elektronisches Bauelement
KR101906860B1 (ko) * 2011-11-24 2018-10-12 삼성전자주식회사 반도체 소자 및 이를 제조하는 방법
CN102795593A (zh) * 2012-08-29 2012-11-28 深迪半导体(上海)有限公司 超薄真空密封mems晶圆的加工方法
CN104112673B (zh) * 2013-04-19 2017-06-23 碁鼎科技秦皇岛有限公司 芯片封装基板及其制作方法
TWI525673B (zh) * 2013-10-08 2016-03-11 精材科技股份有限公司 晶圓級晶片封裝體的製造方法
KR20150078008A (ko) * 2013-12-30 2015-07-08 에스케이하이닉스 주식회사 반도체 장치, 이의 제조 방법 및 이의 테스트 방법
CN104752239B (zh) * 2013-12-31 2019-07-23 中芯国际集成电路制造(上海)有限公司 一种半导体器件、制备方法及封装方法
DE102014100237B4 (de) * 2014-01-10 2016-06-02 Stiftung Caesar Center Of Advanced European Studies And Research Verfahren zum Erzeugen einer freistehenden, abgeschirmten Metallelektrode durch einen Einzelmaskenprozess und ein Verfahren zum Freilegen einer Elektrodenspitze
TWI628723B (zh) * 2015-03-10 2018-07-01 精材科技股份有限公司 一種晶片尺寸等級的感測晶片封裝體及其製造方法
TWI778938B (zh) 2015-03-16 2022-10-01 美商艾馬克科技公司 半導體裝置和製造其之方法
KR101678418B1 (ko) * 2015-03-16 2016-11-23 한국생산기술연구원 3차원 레이저 스캐닝 시스템
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US20170256432A1 (en) * 2016-03-03 2017-09-07 Nexperia B.V. Overmolded chip scale package
US20170330980A1 (en) * 2016-05-16 2017-11-16 General Electric Company Die repatterning transmission lines on silicon photomultipliers
US10319654B1 (en) 2017-12-01 2019-06-11 Cubic Corporation Integrated chip scale packages
US11114402B2 (en) 2018-02-23 2021-09-07 Semiconductor Components Industries, Llc Semiconductor device with backmetal and related methods
CN110444480A (zh) * 2019-07-24 2019-11-12 浙江荷清柔性电子技术有限公司 制作柔性芯片的方法、柔性芯片

Family Cites Families (116)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2013735A1 (zh) 1968-07-05 1970-04-10 Gen Electric Inf Ita
GB1285708A (en) * 1968-10-28 1972-08-16 Lucas Industries Ltd Semi-conductor devices
US3648131A (en) 1969-11-07 1972-03-07 Ibm Hourglass-shaped conductive connection through semiconductor structures
US4954875A (en) 1986-07-17 1990-09-04 Laser Dynamics, Inc. Semiconductor wafer array with electrically conductive compliant material
US4978639A (en) * 1989-01-10 1990-12-18 Avantek, Inc. Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips
JPH0482215A (ja) 1990-07-25 1992-03-16 Sumitomo Electric Ind Ltd ランプアニール装置
US5229647A (en) 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
US5927993A (en) 1992-02-03 1999-07-27 Motorola, Inc. Backside processing method
US5350662A (en) * 1992-03-26 1994-09-27 Hughes Aircraft Company Maskless process for forming refractory metal layer in via holes of GaAs chips
US5476819A (en) 1993-07-26 1995-12-19 Litton Systems, Inc. Substrate anchor for undercut silicon on insulator microstructures
TW270213B (zh) 1993-12-08 1996-02-11 Matsushita Electric Ind Co Ltd
JPH08186151A (ja) 1994-12-29 1996-07-16 Sony Corp 半導体装置及びその製造方法
US5682062A (en) 1995-06-05 1997-10-28 Harris Corporation System for interconnecting stacked integrated circuits
US5648684A (en) 1995-07-26 1997-07-15 International Business Machines Corporation Endcap chip with conductive, monolithic L-connect for multichip stack
JPH0946566A (ja) 1995-08-01 1997-02-14 Olympus Optical Co Ltd 電子内視鏡用固体撮像装置
US5904546A (en) * 1996-02-12 1999-05-18 Micron Technology, Inc. Method and apparatus for dicing semiconductor wafers
KR100410812B1 (ko) 1996-06-25 2004-04-01 주식회사 하이닉스반도체 반도체장치의제조방법
US6027958A (en) * 1996-07-11 2000-02-22 Kopin Corporation Transferred flexible integrated circuit
DE19636744C2 (de) 1996-09-10 1998-09-17 Siemens Ag Verfahren zum Übertragen von Daten in einem hybriden Telekommunikationssystem, insbesondere einem "ISDN - DECT-spezifischen RLL/WLL"-System
WO1998013862A1 (fr) 1996-09-24 1998-04-02 Mitsubishi Denki Kabushiki Kaisha Dispositif a semi-conducteur et son procede de fabrication
US5691245A (en) * 1996-10-28 1997-11-25 He Holdings, Inc. Methods of forming two-sided HDMI interconnect structures
EP2270845A3 (en) 1996-10-29 2013-04-03 Invensas Corporation Integrated circuits and methods for their fabrication
US6054760A (en) 1996-12-23 2000-04-25 Scb Technologies Inc. Surface-connectable semiconductor bridge elements and devices including the same
US5910687A (en) 1997-01-24 1999-06-08 Chipscale, Inc. Wafer fabrication of die-bottom contacts for electronic devices
JPH10242084A (ja) 1997-02-24 1998-09-11 Lintec Corp ウェハ貼着用粘着シートおよび電子部品の製造方法
JP3286553B2 (ja) 1997-03-17 2002-05-27 株式会社村上開明堂 防眩インナーミラー
JP3011233B2 (ja) 1997-05-02 2000-02-21 日本電気株式会社 半導体パッケージ及びその半導体実装構造
US6051489A (en) * 1997-05-13 2000-04-18 Chipscale, Inc. Electronic component package with posts on the active side of the substrate
JP3335575B2 (ja) 1997-06-06 2002-10-21 松下電器産業株式会社 半導体装置およびその製造方法
FR2767223B1 (fr) 1997-08-06 1999-09-17 Commissariat Energie Atomique Procede d'interconnexion a travers un materiau semi-conducteur, et dispositif obtenu
US6432744B1 (en) * 1997-11-20 2002-08-13 Texas Instruments Incorporated Wafer-scale assembly of chip-size packages
EP0926723B1 (en) 1997-11-26 2007-01-17 STMicroelectronics S.r.l. Process for forming front-back through contacts in micro-integrated electronic devices
US5888884A (en) 1998-01-02 1999-03-30 General Electric Company Electronic device pad relocation, precision placement, and packaging in arrays
EP1041617A4 (en) 1998-01-20 2001-07-18 Citizen Watch Co Ltd SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME, AND STRUCTURE AND METHOD FOR FIXING SEMICONDUCTOR
US6624505B2 (en) 1998-02-06 2003-09-23 Shellcase, Ltd. Packaged integrated circuits and methods of producing thereof
IL123207A0 (en) 1998-02-06 1998-09-24 Shellcase Ltd Integrated circuit device
JP3497722B2 (ja) * 1998-02-27 2004-02-16 富士通株式会社 半導体装置及びその製造方法及びその搬送トレイ
JP3842444B2 (ja) 1998-07-24 2006-11-08 富士通株式会社 半導体装置の製造方法
US6153929A (en) 1998-08-21 2000-11-28 Micron Technology, Inc. Low profile multi-IC package connector
DE19846232A1 (de) 1998-09-03 2000-03-09 Fraunhofer Ges Forschung Verfahren zur Herstellung eines Halbleiterbauelements mit Rückseitenkontaktierung
US6066513A (en) * 1998-10-02 2000-05-23 International Business Machines Corporation Process for precise multichip integration and product thereof
US6339251B2 (en) * 1998-11-10 2002-01-15 Samsung Electronics Co., Ltd Wafer grooves for reducing semiconductor wafer warping
US6310328B1 (en) * 1998-12-10 2001-10-30 Mattson Technologies, Inc. Rapid thermal processing chamber for processing multiple wafers
JP3687379B2 (ja) 1998-12-18 2005-08-24 株式会社日立製作所 半導体装置の製造方法
US6259039B1 (en) * 1998-12-29 2001-07-10 Intel Corporation Surface mount connector with pins in vias
KR100315030B1 (ko) * 1998-12-29 2002-04-24 박종섭 반도체패키지의제조방법
FR2788375B1 (fr) * 1999-01-11 2003-07-18 Gemplus Card Int Procede de protection de puce de circuit integre
JP2000286283A (ja) 1999-03-30 2000-10-13 Seiko Epson Corp 半導体装置の製造方法
JP2000294677A (ja) * 1999-04-05 2000-10-20 Fujitsu Ltd 高密度薄膜配線基板及びその製造方法
US6617681B1 (en) * 1999-06-28 2003-09-09 Intel Corporation Interposer and method of making same
US6326689B1 (en) * 1999-07-26 2001-12-04 Stmicroelectronics, Inc. Backside contact for touchchip
CN1322574C (zh) * 1999-07-30 2007-06-20 日本板硝子株式会社 在切割区中设置的槽的结构及其应用
JP3687435B2 (ja) * 1999-08-27 2005-08-24 セイコーエプソン株式会社 半導体チップおよびその製造方法、半導体装置、コンピュータ、回路基板ならびに電子機器
JP2001077229A (ja) 1999-09-02 2001-03-23 Matsushita Electronics Industry Corp 半導体装置およびその製造方法
US6316287B1 (en) * 1999-09-13 2001-11-13 Vishay Intertechnology, Inc. Chip scale surface mount packages for semiconductor device and process of fabricating the same
KR100462980B1 (ko) 1999-09-13 2004-12-23 비쉐이 메저먼츠 그룹, 인코포레이티드 반도체장치용 칩 스케일 표면 장착 패키지 및 그 제조공정
JP2001127243A (ja) 1999-10-26 2001-05-11 Sharp Corp 積層半導体装置
JP2001185519A (ja) 1999-12-24 2001-07-06 Hitachi Ltd 半導体装置及びその製造方法
JP3858545B2 (ja) 1999-12-27 2006-12-13 セイコーエプソン株式会社 半導体モジュール及び電子機器
JP2001210667A (ja) 2000-01-28 2001-08-03 New Japan Radio Co Ltd 半導体装置の製造方法
US6534751B2 (en) * 2000-02-28 2003-03-18 Kyocera Corporation Wafer heating apparatus and ceramic heater, and method for producing the same
US6424031B1 (en) 2000-05-08 2002-07-23 Amkor Technology, Inc. Stackable package with heat sink
JP3701542B2 (ja) 2000-05-10 2005-09-28 シャープ株式会社 半導体装置およびその製造方法
JP3879816B2 (ja) 2000-06-02 2007-02-14 セイコーエプソン株式会社 半導体装置及びその製造方法、積層型半導体装置、回路基板並びに電子機器
JP4329235B2 (ja) 2000-06-27 2009-09-09 セイコーエプソン株式会社 半導体装置及びその製造方法
JP2002026270A (ja) * 2000-07-10 2002-01-25 Nec Corp 半導体装置の製造方法
JP2002094082A (ja) 2000-07-11 2002-03-29 Seiko Epson Corp 光素子及びその製造方法並びに電子機器
JP2002057128A (ja) * 2000-08-15 2002-02-22 Fujitsu Quantum Devices Ltd 半導体装置及びその製造方法
US6379982B1 (en) 2000-08-17 2002-04-30 Micron Technology, Inc. Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing
US6406934B1 (en) 2000-09-05 2002-06-18 Amkor Technology, Inc. Wafer level production of chip size semiconductor packages
JP2002083785A (ja) 2000-09-07 2002-03-22 Nec Kansai Ltd 半導体素子の製造方法
JP2002093942A (ja) 2000-09-14 2002-03-29 Nec Corp 半導体装置およびその製造方法
JP4183375B2 (ja) * 2000-10-04 2008-11-19 沖電気工業株式会社 半導体装置及びその製造方法
US6693358B2 (en) 2000-10-23 2004-02-17 Matsushita Electric Industrial Co., Ltd. Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device
JP2002163900A (ja) * 2000-11-22 2002-06-07 Hitachi Ltd 半導体ウエハ、半導体チップ、半導体装置および半導体装置の製造方法
US6506681B2 (en) * 2000-12-06 2003-01-14 Micron Technology, Inc. Thin flip—chip method
US6524885B2 (en) * 2000-12-15 2003-02-25 Eaglestone Partners I, Llc Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniques
JP2002231918A (ja) 2001-02-06 2002-08-16 Olympus Optical Co Ltd 固体撮像装置及びその製造方法
US6399463B1 (en) * 2001-03-01 2002-06-04 Amkor Technology, Inc. Method of singulation using laser cutting
JP4497737B2 (ja) 2001-03-12 2010-07-07 株式会社ルネサステクノロジ 半導体装置の製造方法
US6910268B2 (en) 2001-03-27 2005-06-28 Formfactor, Inc. Method for fabricating an IC interconnect system including an in-street integrated circuit wafer via
US6597059B1 (en) * 2001-04-04 2003-07-22 Amkor Technology, Inc. Thermally enhanced chip scale lead on chip semiconductor package
JP4698877B2 (ja) 2001-04-27 2011-06-08 オリンパス株式会社 撮像装置
US6753936B2 (en) * 2001-05-17 2004-06-22 Dai Nippon Pringing Co., Ltd. Field sequential color liquid crystal display device
JP2003031647A (ja) * 2001-07-19 2003-01-31 Hitachi Kokusai Electric Inc 基板処理装置および半導体装置の製造方法
JP4000507B2 (ja) 2001-10-04 2007-10-31 ソニー株式会社 固体撮像装置の製造方法
SG102639A1 (en) 2001-10-08 2004-03-26 Micron Technology Inc Apparatus and method for packing circuits
US6642127B2 (en) 2001-10-19 2003-11-04 Applied Materials, Inc. Method for dicing a semiconductor wafer
US6611052B2 (en) * 2001-11-16 2003-08-26 Micron Technology, Inc. Wafer level stackable semiconductor package
US6955989B2 (en) * 2001-11-30 2005-10-18 Xerox Corporation Use of a U-groove as an alternative to using a V-groove for protection against dicing induced damage in silicon
US6607941B2 (en) * 2002-01-11 2003-08-19 National Semiconductor Corporation Process and structure improvements to shellcase style packaging technology
US6908784B1 (en) 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
US6848177B2 (en) 2002-03-28 2005-02-01 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
TWI232560B (en) * 2002-04-23 2005-05-11 Sanyo Electric Co Semiconductor device and its manufacture
US7340181B1 (en) 2002-05-13 2008-03-04 National Semiconductor Corporation Electrical die contact structure and fabrication method
JP2003332270A (ja) * 2002-05-15 2003-11-21 Renesas Technology Corp 半導体装置およびその製造方法
US7399683B2 (en) * 2002-06-18 2008-07-15 Sanyo Electric Co., Ltd. Manufacturing method of semiconductor device
TWI229435B (en) 2002-06-18 2005-03-11 Sanyo Electric Co Manufacture of semiconductor device
US6805279B2 (en) * 2002-06-27 2004-10-19 Taiwan Semiconductor Manufacturing Co., Ltd. Fluxless bumping process using ions
DE10238444B4 (de) 2002-08-22 2011-05-12 United Monolithic Semiconductors Gmbh Verfahren zur Herstellung von vereinzelten monolithisch integrierten Halbleiterschaltungen
US6903442B2 (en) 2002-08-29 2005-06-07 Micron Technology, Inc. Semiconductor component having backside pin contacts
JP4081666B2 (ja) * 2002-09-24 2008-04-30 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
TWI227050B (en) * 2002-10-11 2005-01-21 Sanyo Electric Co Semiconductor device and method for manufacturing the same
TWI227550B (en) 2002-10-30 2005-02-01 Sanyo Electric Co Semiconductor device manufacturing method
TWI239607B (en) 2002-12-13 2005-09-11 Sanyo Electric Co Method for making a semiconductor device
TWI229890B (en) 2003-04-24 2005-03-21 Sanyo Electric Co Semiconductor device and method of manufacturing same
JP2007528120A (ja) 2003-07-03 2007-10-04 テッセラ テクノロジーズ ハンガリー コルラートルト フェレロェセーギュー タールシャシャーグ 集積回路装置をパッケージングする方法及び装置
JP4401181B2 (ja) * 2003-08-06 2010-01-20 三洋電機株式会社 半導体装置及びその製造方法
TWI226090B (en) * 2003-09-26 2005-01-01 Advanced Semiconductor Eng Transparent packaging in wafer level
US7183137B2 (en) * 2003-12-01 2007-02-27 Taiwan Semiconductor Manufacturing Company Method for dicing semiconductor wafers
JP2005191550A (ja) 2003-12-01 2005-07-14 Tokyo Ohka Kogyo Co Ltd 基板の貼り付け方法
JP4753170B2 (ja) * 2004-03-05 2011-08-24 三洋電機株式会社 半導体装置及びその製造方法
JP2006093367A (ja) * 2004-09-24 2006-04-06 Sanyo Electric Co Ltd 半導体装置の製造方法
TWI273682B (en) 2004-10-08 2007-02-11 Epworks Co Ltd Method for manufacturing wafer level chip scale package using redistribution substrate
US7449779B2 (en) * 2005-03-22 2008-11-11 Tessera, Inc. Wire bonded wafer level cavity package
TWI324800B (en) * 2005-12-28 2010-05-11 Sanyo Electric Co Method for manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI479622B (zh) * 2011-11-15 2015-04-01 Xintec Inc 晶片封裝體及其形成方法

Also Published As

Publication number Publication date
KR100552356B1 (ko) 2006-02-20
EP1376678A3 (en) 2004-02-04
EP1376678A2 (en) 2004-01-02
CN1855463A (zh) 2006-11-01
US6864172B2 (en) 2005-03-08
EP2207198A2 (en) 2010-07-14
TW200405534A (en) 2004-04-01
CN100474573C (zh) 2009-04-01
CN1469447A (zh) 2004-01-21
EP2207198A3 (en) 2011-06-29
CN1276492C (zh) 2006-09-20
US20040063268A1 (en) 2004-04-01
KR20040002599A (ko) 2004-01-07
US20080265424A1 (en) 2008-10-30
US7719102B2 (en) 2010-05-18

Similar Documents

Publication Publication Date Title
TWI229435B (en) Manufacture of semiconductor device
JP4212293B2 (ja) 半導体装置の製造方法
US11727714B2 (en) Fingerprint sensor device and method
TWI293206B (en) Semiconductor device, method for manufacturing semiconductor device, circuit board, and electronic instrument
TWI622144B (zh) 指紋感測器裝置及其製造方法
US7399683B2 (en) Manufacturing method of semiconductor device
TWI251314B (en) Manufacturing method of semiconductor device, semiconductor device, circuit substrate and electronic equipment
JP4635209B2 (ja) 半導体パッケージの製造方法
CN100395886C (zh) 半导体器件的制造方法
TW201018347A (en) Wiring board capable of having built-in functional element and method for manufacturing the same
TW201444006A (zh) 金屬凸塊結構
JP2007311385A (ja) 半導体装置の製造方法および半導体装置
TW200913216A (en) Semiconductor device and manufacturing method thereof
US11670593B2 (en) Package-on-package (POP) electronic device and manufacturing method thereof
JP2002231854A (ja) 半導体装置およびその製造方法
JP4215571B2 (ja) 半導体装置の製造方法
JP4425235B2 (ja) 半導体装置及びその製造方法
JP2003037344A (ja) 回路装置およびその製造方法
JP4286264B2 (ja) 半導体装置及びその製造方法
JP2005109427A (ja) 半導体装置及びその製造方法
JP4443549B2 (ja) 半導体装置の製造方法
JP4698080B2 (ja) 回路装置の製造方法
JP4938346B2 (ja) 半導体装置およびその製造方法
TW200950036A (en) Semiconductor device and manufacture method thereof

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees