CN1855463A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN1855463A
CN1855463A CNA2006100752719A CN200610075271A CN1855463A CN 1855463 A CN1855463 A CN 1855463A CN A2006100752719 A CNA2006100752719 A CN A2006100752719A CN 200610075271 A CN200610075271 A CN 200610075271A CN 1855463 A CN1855463 A CN 1855463A
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semiconductor device
semiconductor substrate
substrate
manufacture method
film
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CN100474573C (zh
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野间崇
篠木裕之
高尾幸弘
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Abstract

一种削减制造工序数量，实现低成本化的半导体装置及其制造方法。本发明的半导体装置，包括：形成于半导体衬底的上表面侧的金属焊盘；与所述金属焊盘电连接，并且形成于所述半导体衬底的上表面侧的电极连接部；形成于所述半导体衬底的侧面部及下表面部的第一绝缘膜；与所述金属焊盘连接，并且沿所述半导体衬底的侧面部及下表面部延伸的金属配线。

Description

半导体装置及其制造方法
本发明专利申请是中国发明专利申请第03143065.1号、申请日为2003年6月18日、发明名称为“半导体装置的制造方法”的分案申请。
技术领域
本发明涉及一种半导体装置及其制造方法，具体而言，涉及具有球状导电端子的BGA(Ball Grid Array焊球阵列)型半导体装置及其制造方法。
背景技术
作为现有的表面安装型半导体装置的一种有BGA型的半导体装置。其是将由焊锡等金属材料构成的球状导电端子在封装衬底一主面上格子状配列多个，并和搭载在衬底的其它主面上的半导体芯片焊接，然后封装得到的装置。并且，在组装到电子仪器时，将各导电端子热熔接在印刷衬底上的配线图案上，并将半导体芯片和印刷衬底上搭载的外部电路电连接。
这样的BGA型半导体装置和半导体装置的侧面具有突出的导线插头的SOP(Small Outline Package小外形封装)或QFP(Quad Flat Package四边引线扁平封装)等其它表面安装型的半导体装置相比，可以设置多个连接端子，有利于小型化，这是众所周知的。
近年来，这种BGA型半导体装置在CCD图像传感器的领域也采用，作为在小型化要求强烈的手机上搭载的数字相机的图像传感器芯片使用。
另外，使用晶片电平的CSP(Chip Size Package芯片尺寸封装)或硅(Si)贯通技术的三维安装技术正在受到关注。这些技术研究在粘合多层芯片后，贯通Si或从表面贯通Si晶片，然后进行堆积的方法。
然而，现有的三维安装技术由表面进行Si贯通等加工，由铜(Cu)填充夹层孔而形成，故表面侧必须进行CMP(Chemical Mechanical Pocishing化学机械抛光)处理，Cu夹层形成后必须进行将该Cu夹层和焊盘连接的再配线，因而具有制造工序增多的缺点。另外，使用Cu的技术虽然适于细微化，但Cu自身的成本高或必须另外购入其它特别的装置，故也有不能避免成本高的现状。
发明内容
于是，本发明提供一种半导体装置，其特征在于，包括：形成于半导体衬底的上表面侧的金属焊盘；与所述金属焊盘电连接，并且形成于所述半导体衬底的上表面侧的电极连接部；形成于所述半导体衬底的侧面部及下表面部的第一绝缘膜；与所述金属焊盘连接，并且沿所述半导体衬底的侧面部及下表面部延伸的金属配线。
另外，本发明的一种半导体装置，其特征在于，包括：形成于半导体衬底的上表面侧的金属焊盘；与所述金属焊盘的一个的主面电连接，并且形成于所述半导体衬底的上表面侧的电极连接部；从所述半导体衬底的下表面开设至所述金属焊盘的另一个的主面的开口部；形成于所述开口部内的侧壁上的第一绝缘膜；形成于所述开口部内的金属膜。
另外，本发明提供一种半导体装置的制造方法，其特征在于，包括：
准备半导体衬底，其在上表面侧形成有金属焊盘，经由粘接物质粘合所述半导体衬底的上表面侧和支承体的工序；去除所述半导体衬底的下表面而形成开口部的工序；在所述开口部内经由绝缘膜而形成与所述金属焊盘连接的金属配线的工序；从所述半导体衬底的下表面侧切割的工序；分离所述半导体衬底和所述支承体的工序。
附图说明
图1是显示本发明的第一实施形态的半导体装置制造方法的剖面图；
图2是显示本发明的第一实施形态的半导体装置制造方法的剖面图；
图3(a)、(b)是显示本发明的第一实施形态的半导体装置制造方法的剖面图；
图4(a)、(b)是显示本发明的第一实施形态的半导体装置制造方法的剖面图；
图5是显示本发明的第一实施形态的半导体装置制造方法的剖面图；
图6是显示本发明的第一实施形态的半导体装置制造方法的剖面图；
图7(a)、(b)是显示本发明的第一实施形态的半导体装置制造方法的剖面图；
图8是显示本发明的第一实施形态的半导体装置制造方法的剖面图；
图9是显示本发明的第二实施形态的半导体装置制造方法的剖面图；
图10(a)、(b)是显示本发明的第三实施形态的半导体装置制造方法的剖面图；
图11(a)、(b)是显示本发明的第三实施形态的半导体装置制造方法的剖面图；
图12(a)、(b)是显示本发明的第三实施形态的半导体装置制造方法的剖面图；
图13(a)、(b)是显示本发明的第三实施形态的半导体装置制造方法的剖面图；
图14(a)、(b)是显示本发明的第三实施形态的半导体装置制造方法的剖面图；
图15(a)、(b)是显示本发明的第三实施形态的半导体装置制造方法的剖面图；
图16是显示本发明的第三实施形态的半导体装置制造方法的剖面图；
图17(a)、(b)是显示本发明的第四及第五实施形态的半导体装置制造方法的剖面图。
具体实施方式
以下，对本发明的半导体装置的制造方法的第一实施形态，参照附图进行说明。
首先，如图1所示，在大约600μm膜厚的硅片(以下称为Si衬底1)上形成氧化膜，在该氧化膜上形成多个金属(如Al或Al合金)焊盘2a、2b，覆盖该焊盘2a、2b采用等离子CVD法形成SiO2膜或PSG膜，将其和所述氧化膜合起来形成规定膜厚的第一氧化膜3。并且，所述焊盘2a、2b和Si衬底1上构成的各半导体元件连接。另外，在特别需要平坦性时，例如可物理研磨第一氧化膜3，或对其进行化学腐蚀处理等。然后，以未图示的光致抗蚀剂膜为掩模腐蚀焊盘2a、2b上的第一氧化膜3，露出该焊盘2a、2b的一部分(表面部)。其后，在焊盘2a、2b的上表面上实施铝(Al或Al合金)的第一配线4。另外，在本实施形态中，所述第一氧化膜3的膜厚全部大约为5μm左右。另外，焊盘2a、2b的一部分被第一氧化膜3覆盖。
其次，如图2所示，在第一配线4的上表面上形成聚酰亚胺膜5，以未图示的光致抗蚀剂膜为掩模腐蚀该聚酰胺膜5，在所述焊盘2a、2b连接的第一配线4上形成开口部。在图2中，表示聚酰亚胺膜5的两端形成该开口部的情况。
而后，在所述开口部内形成未图示的镍(Ni)、金(Au)后，在其上采用半导体后工序使用的普通镀敷装置镀铜(Cu)，装入Cu端子6。另外，该Cu端子6上，为防止该Cu端子6的腐蚀也可电镀形成Au。另外，在本实施形态中，所述开口部内装设的导电材料(Ni、Au、Cu、Au)的膜厚整体约为25μm左右。
在此，在将本工艺用在不用于三维工艺的CSP工艺时，不必形成开口部，可整面涂敷聚酰亚胺膜5。
在没有聚酰亚胺膜5的状态下，也可以将后述的支承衬底8用粘接薄膜粘合在Si衬底1上方。
另外，在CCD图像传感器采用本工艺时，所述聚酰亚胺膜5必须使用网印法形成透明性聚酰亚胺膜或透明玻璃环氧树脂等。
也可以是用环氧树脂粘合玻璃板件。
接着，如图3所示，在包含所述Cu端子6(Au)上的聚酰亚胺膜5上粘贴粘接薄膜7，介由该粘接薄膜7粘合支承衬底8和所述Si衬底1侧。
在此，所述支承衬底8是为了防止后述的Si衬底1的BG(基底研磨)时、Si衬底1的破裂等的支承件，利用例如Si衬底或氧化膜(玻璃衬底)或陶瓷等。另外，在本实施形态中，作为支承件必需的膜厚为大约400μm左右。
另外，所述粘接薄膜7为了提高后述的Si衬底1和支承衬底8的分离工序的作业效率，采用溶于丙酮的有机膜。并且，在本实施形态中，粘接薄膜7的膜厚定为大约100μm左右。该粘接薄膜7作为后述树脂9填充用配置在距晶片边缘2mm左右的内侧。
在此，也可替换粘接薄膜，使用无粘接力的薄膜，在该薄膜的两侧涂敷粘接剂，将所述支承衬底8和所述薄膜及所述Si衬底1侧粘合。此时，只要使用溶解粘接剂的溶剂即可。
图3(b)是图3(a)的概略图和平面图(为说明方便，是除去支承衬底8后的平面图)。
在该粘接薄膜7的外周部通过如图3(b)所示填充环氧树脂9，密封该粘接薄膜7并固定，由此，防止在各种作业中有机溶剂等药液的侵入。在此，环氧树脂9也可是聚酰亚胺类树脂。
其次，如图4(a)所示，BG处理Si衬底一侧，将该Si衬底1的膜厚减薄至大约10～100μm左右。此时，所述支承衬底8在BG工序时支承Si衬底1。而后，腐蚀BG处理过的Si衬底1的下表面侧及第一氧化膜3，形成第一开口部k1，使所述焊盘2a、2b露出。
然后，如图4(b)所示，在Si衬底1的下表面侧堆积第二氧化膜10后，以未图示的光致抗蚀剂膜为掩膜腐蚀该第二氧化膜10，形成第二开口部k2。在此，第一氧化膜3a是焊盘2a和焊盘2b间的第一氧化膜3的腐蚀剩余部。另外，也可取代所述第二氧化膜10，使用硅氮化膜或聚酰亚胺膜等。
另外，在本实施形态中，如图4(a)所示，在Si衬底1的腐蚀工序后，具有腐蚀第一氧化膜3的工序，在包含开口部k1的Si衬底1上形成氧化膜10，腐蚀该第二氧化膜10，形成开口部k2，但也可以例如，在相当于图4(a)的工序中，在仅腐蚀Si衬底1并于焊盘2a、2b之下残留第一氧化膜3的情况下，形成第二氧化膜10，腐蚀该第二氧化膜及第一氧化膜3形成开口部2。
其次，如图5所示，在第二氧化膜10的表面所需位置形成缓冲部件11，将该缓冲部件11的表面、第二氧化膜10的表面及所述第二开口部k2覆盖，通过喷射形成铝(Al或Al合金)，形成第二配线12，另外，第二配线12也可是Cu配线。
然后，如图6所示，以未图示的光致抗蚀剂膜为掩膜，腐蚀所述第二配线12，露出第一氧化膜3a，。即，通过该腐蚀，焊盘2a、2b的下表面的露出面由第二配线12覆盖，与焊盘2a、2b的端部和第二配线12的腐蚀剖面大致一致。其结果，形成焊盘2a、2b各自和第二配线12具有10～数百μm左右的面接触。该配线形成后，施行镍(Ni)及金(Au)的无电解电镀。
另外，也可以取代Al喷射，喷射钛钨合金(TiW)，保护膜形成后进行铜(Cu)的电解电镀，除去该保护膜后，通过腐蚀钛钨合金(TiW)形成第二配线12。
而后，在第二配线12的表面形成焊接掩膜(以下称保护膜13)，并在该保护膜13上网印焊料糊，通过反射处理该焊料糊，在所述第二配线12上形成焊料球(以下称导电端子14)。在本实施形态中，作为保护膜13使用由可在200℃亚胺化的流体敷层(リカコ-ト)(新日本理化社制品)构成的聚酰亚胺。
然后，进行切割，如图7所示，在第一氧化膜3a上形成切割线D。该切割线D是为了分离每个晶片上的半导体芯片而设置的。图7(b)是图7(a)的概略图和平面图(为了说明方便，是除去支承衬底8后的平面图)。在图7(b)的概略图中，切割线D形成至到达粘接薄膜7的位置，在平面图中，该切割线D格子状形成。
而后，通过在未图示的丙酮溶液槽内浸泡该Si衬底1，由如图7(b)所示的所述切割线(D)侵入丙酮，溶解所述粘接薄膜7。其结果将所述Si衬底1(各芯片)和支承衬底8自动分离，完成如图8所示的单体CSP芯片。
这样，在本实施形态中，由于使用溶解于丙酮的有机类类粘接薄膜7粘合Si衬底1和支承衬底8，故切割后，仅使Si衬底1浸泡在丙酮中，即可简单地分离二者，作业性好。
另外，也可取代所述粘接薄膜7，使用粘接力弱的薄膜，在切割后，物理剥离芯片。另外，在作为支承衬底8使用透明玻璃时，只要作为有机类薄膜7粘贴UV带，切割后做UV照射，剥离芯片即可。
也可取代粘接薄膜7，在没有粘接力的薄膜上设置UV粘接剂，粘接所述Si衬底1和支承衬底8，在某个工序结束后，对所述UV系粘接剂照射UV，使其硬化，从而剥离该Si衬底1和支承衬底8，然后切割Si衬底1。
并且，也可在切割后，例如自晶片下表面由加热板加热，溶解由晶片和支承衬底8挟持的有机膜(粘接薄膜7)使其软化，从而剥离两者。此时，在粘接薄膜7是溶于丙酮的有机膜时，加热200℃左右，而在利用聚酰亚胺膜时，加热400℃左右，该粘接薄膜7就会溶解。
作为剥离Si衬底1和支承衬底8的另一形式，也有在切割前竖起晶片使其旋转，仅将外周浸在酸(如硫酸)等药品中，将边缘的环氧树脂，外周剥离的方法。
另外，作为直接剥离Si衬底1和支承衬底8的方法，列举由切剥器或锯、裁剪刀等刀具切削边缘外周的环氧树脂部分的方法或研磨每个硅晶片，切削同一部分，从而剥离两者的方法等。
作为本发明的第二实施形态，如图9所示，通过金属粘合Cu端子6和导电端子14，粘合(层叠)CSP芯片相互之间，所述单体CSP芯片(图8切离后的半导体装置的一个)可实现三维安装(无论几层)，只要是相同芯片尺寸的东西(存储器等)，就可实现大容量化。
以下，参照附图说明本发明的半导体装置的制造方法的第三实施形态。
首先，如图10(a)所示，在大约600μm膜厚的硅晶片(以下称Si衬底)101上形成氧化膜，在该氧化膜上形成金属(例如Al或Al合金)焊盘102，覆盖该焊盘102，通过等离子CVD法形成SiO2膜或PSG膜，并将其和所述氧化膜合起来，形成规定膜厚的第一氧化膜103。且，所述焊盘102和Si衬底101上构成的半导体元件连接。另外，在特别需要平坦性时，也可将第一氧化膜103进行例如物理研磨或化学腐蚀处理等。而后，以未图示的光致抗蚀剂膜为掩膜，腐蚀焊盘102上的第一氧化膜103，露出该焊盘102的一部分(表面部)。另外，在本实施形态中，所述第一氧化膜103的膜厚整体大约为5μm左右。另外，焊盘102的一部分被第一氧化膜103覆盖。
然后，如图10(b)所示，在所述焊盘102及第一氧化膜103上形成聚酰亚胺膜，并以未图示的光致抗蚀剂膜为掩膜腐蚀该聚酰亚胺膜，在所述焊盘102上形成具有开口部的聚酰亚胺膜104。而后，在所述开口部内形成镍(Ni)105、金(Au)106，然后，在其上镀铜(Cu)，装入铜端子107。也可以在该Cu端子107上，为防止该Cu端子107的腐蚀，电镀形成Au。另外，在本实施形态中，所述开口部内埋设的导电部材(Ni、Au、Cu、Au)的膜厚整体约为25μm左右。
在此，本工艺在用于CCD图像传感器时，所述聚酰亚胺膜104必须使用网印法形成透明性聚酰亚胺膜或透明玻璃环氧树脂等。
也可以是用环氧树脂粘合玻璃板件。
另外，在将本工艺适用于不使用于三维工艺的CSP工艺流程时，没有形成开口部的必要，可对聚酰亚胺膜104的整个面进行涂敷。
在没有聚酰亚胺膜5的状态下，也可以将后述的支承衬底8用粘接薄膜粘合在Si衬底1上方。
作为本发明的第四实施形态，如图17(a)所示，在包含所述焊盘102上部的第一氧化膜103上形成TiW121，进行图案制作，构成规定图案。而后，也可以形成聚酰亚胺膜104A，并在该聚酰亚胺膜104A上形成的开口部上形成Cu端子107A(及Cu)，采用所谓再配线结构。
然后，如图11(a)所示，在包含所述Cu端子107(及Cu)上的聚酰亚胺膜104上粘贴粘接薄膜110，介由该粘接薄膜110粘合支承衬底111和所述Si衬底101侧。
在此，所述支承衬底111是为了在后述的Si衬底101的BG(基底研磨)时，防止Si衬底101的破裂等的支承件，其利用了例如Si衬底或氧化膜(玻璃衬底)或陶瓷等。另外，在本实施形态中，作为支承件必要的膜厚大约为400μm左右。
另外，所述粘接薄膜110为了提高后述的Si衬底101和支承衬底111的分离工序中的作业效率，采用了溶于丙酮的有机膜。另外，在本实施形态中，粘接薄膜110的膜厚为大约100μm左右。该粘接薄膜110作为后述的环氧树脂112的填充用配置在距晶片边缘2mm左右的内侧。
在此，也可取代粘接薄膜，使用无粘接力的薄膜，在该薄膜的两面设置粘接剂，将所述支承衬底111和该薄膜和所述Si衬底101侧粘合。这种情况下，只要使用溶解粘接剂的溶剂即可。
图11(b)是图11(a)的简化图和平面图(为说明方便，是除去支承衬底111后的平面图)。
在该粘接薄膜110的外周部，如图11(b)所示，通过填充环氧树脂112密封并固定该粘接薄膜110。由此，防止了在各种作业中有机溶剂等药液的侵入。
其次，如图12(a)所示，可BG处理Si衬底101侧，薄膜化该Si衬底101的膜厚至大约10～100μm左右。此时，所述支承衬底111在BG工序时支承Si衬底101。而后，在BG处理后的Si衬底101的下表面侧形成大约0.01μm左右的第二氧化膜113。另外，也可取代所述第二氧化膜113形成由硅氮化膜或聚酰亚胺构成的有机类绝缘物。并且，在所述BG工序中，由于不受Cu上的平坦性左右，故可直接进行基底研磨，作业性能好。
然后，如图12(b)所示，以未图示的光致抗蚀剂膜为掩膜，腐蚀所述第二氧化膜113及Si衬底101，形成开口部114。然后，如图13(a)所示，腐蚀由所述开口部114露出的第一氧化膜103，露出所述焊盘102。其后，覆盖包含开口部114a内的所述焊盘102上的第二氧化膜113上，利用CVD法形成第三氧化膜，并各向异性腐蚀该第三氧化膜，在开口部114a的侧壁部残留第三氧化膜，形成侧壁衬垫膜115。另外，第三氧化膜的CVD成膜处理温度最好为200℃左右的低温。另外，也可使用硅氮化膜形成侧壁衬垫膜115。
其次，如图13(b)所示，在所述开口部114a内介由侧壁衬垫膜115喷射形成氮化钛(TiN)或氮化钽(TaN)等阻挡膜116，并介由该阻挡膜116在所述开口部114a内埋设Cu，形成Cu埋入层117。另外，在本工序中，首先在阻挡膜116上施以Cu籽晶、进行镀Cu处理，并退火处理该Cu。而后，将该Cu埋设在开口部114a内。在此，在特别需要平坦性时，要CMP研磨该Cu。
然后，如图14(a)所示，在所述Cu埋入层117上形成具有比埋设该Cu埋入层117的开口部114a的开口尺寸更大开口的焊接掩膜118，并介由该掩膜118在该开口上网印焊锡糊，通过反射处理该焊锡糊，在Cu埋入层117上形成焊锡球119。另外，在本实施形态中，作为焊接掩膜118，使用由可在200℃亚胺化的流体涂层构成的聚酰亚胺膜。
如图17所示，作为本发明的第五实施形态在包含所述Cu埋入层117上的第二氧化膜113上形成Al膜131及Ni膜(及Au膜)132，并进行图案制作，形成规定图案。也可采用介由焊接掩膜118A形成焊锡球119的结构。
然后，如图14(b)所示，切割所述Si衬底101侧至到达所述粘接薄膜110的位置。
而后，通过在未图示的丙酮溶液槽内浸泡该Si衬底101，如图15(b)所示，从所述切割线(D)侵入丙酮并溶解所述粘接薄膜110。因此，所述Si衬底101(各芯片)和支承衬底111自动分离，完成图15(a)所示的单体CSP芯片120。
这样，在本实施形态中，由于使用溶于丙酮的有机类粘接薄膜110粘合Si衬底101和支承衬底111，故切割后仅通过将Si衬底101浸泡在丙酮中，就可简单地分离两者，作业性好。
另外，也可取代所述粘接薄膜110，使用弱粘接力的薄膜，在切割后，物理剥离芯片。并且，在作为支承衬底111使用透明玻璃时，只要作为有机类粘接薄膜110粘贴UV带，切割后进行UV照射并剥离芯片即可。
也可取代粘接薄膜110，在没有粘接力的薄膜上设置UV粘接剂，粘接所述Si衬底101和支承衬底111，在某个工序结束后，对所述UV系粘接剂照射UV，使其硬化，从而剥离该Si衬底101和支承衬底111，然后切割Si衬底101。
并且，切割后，例如由晶片下表面利用加热板加热，通过溶解晶片和支承衬底111挟持的有机膜(粘接薄膜110)并使其软化来剥离两者也可。此时，在粘接薄膜110是溶于丙酮的有机膜时，通过200℃左右的加热，在利用聚酰亚胺膜时进行400℃左右的加热，使该粘接薄膜110溶解。
作为剥离Si衬底101和支承衬底111的另一形态，也有在切割前，竖起晶片旋转，并仅将外周浸于酸等药品中，将边缘的环氧树脂剥离的方法。另外，也有将刀具插入晶片和芯片之间的边缘的环氧树脂中进行切离的方法。两方法后，粘贴BG带进行切割。
而后，如图16所示，由金属粘合Cu端子107(及Cu)和焊锡球119将CSP芯片120相互之间密切粘合(层积)，可以实现所述单体CSP芯片120的三维安装(无论几层)，实现相同芯片尺寸的东西(存储器等)的大容量化。
在本发明中，由于使用一般安装领域使用的喷射装置和电镀装置形成配线，故可实现低成本且工序非常简单的半导体装置。
另外，由于不象现有的三维安装技术那样自表面进行Si贯通等加工，不用铜(Cu)填充形成夹层孔，故在现有例中当然需要的表面侧CMP(Chemical Mechanical Polishing)处理，在本实施形态中，不必再进行，可以削减工序数量。
另外，在积层结构中，在Cu夹层形成后，为了连接该Cu夹层和焊盘，不需要再配线，不增加制造工时。
另外，支承衬底和Si衬底由于在粘合后进行了BG(基底研磨)及其后处理，故芯片的膜厚可以尽可能薄。

Claims (40)

1.一种半导体装置，其特征在于，包括：
形成于半导体衬底的上表面侧的金属焊盘；
与所述金属焊盘电连接，并且形成于所述半导体衬底的上表面侧的电极连接部；
形成于所述半导体衬底的侧面部及下表面部的第一绝缘膜；
与所述金属焊盘连接，并且沿所述半导体衬底的侧面部及下表面部延伸的金属配线。
2.如权利要求1所述的半导体装置，其特征在于，具有覆盖所述金属配线的保护膜。
3.如权利要求1或2中任一项所述的半导体装置，其特征在于，所述电极连接部是由Ni、Au、Cu构成的层积体或由Ni、Au、Cu、Au构成的层积体。
4.如权利要求1或2中任一项所述的半导体装置，其特征在于，在所述半导体衬底的上表面上形成有第一配线，在该第一配线中存在中所述电极连接部与所述金属焊盘的电连接。
5.如权利要求4所述的半导体装置，其特征在于，在所述第一配线上形成有第二绝缘膜，其在所述电极连接部上设有开口部。
6.如权利要求5所述的半导体装置，其特征在于，所述第二绝缘膜包含聚酰亚胺或环氧树脂。
7.如权利要求1或2中任一项所述的半导体装置，其特征在于，具有与所述金属配线电连接的导电端子。
8.如权利要求7所述的半导体装置，其特征在于，在与所述导电端子重叠的区域中，在所述金属配线和所述半导体衬底之间形成有缓冲部件。
9.如权利要求1所述的半导体装置，其特征在于，所述第一绝缘膜由单一的膜构成。
10.一种层积型的半导体装置，其将权利要求1～9中任一项所述的半导体装置与其他的半导体装置层积，其特征在于，相互间电连接是经由所述电极连接部而进行的。
11.一种层积型的半导体装置，其将权利要求7～9中任一项所述的半导体装置至少层积两个，其特征在于，所述至少层积了两个的半导体装置中的一个半导体装置的所述电极连接部与另一个半导体装置的所述导电端子连接。
12.一种半导体装置，其特征在于，包括：
形成于半导体衬底的上表面侧的金属焊盘；
与所述金属焊盘的一个的主面电连接，并且形成于所述半导体衬底的上表面侧的电极连接部；
从所述半导体衬底的下表面开设至所述金属焊盘的另一个的主面的开口部；
形成于所述开口部内的侧壁上的第一绝缘膜；
形成于所述开口部内的金属膜。
13.如权利要求12所述的半导体装置，其特征在于，在所述半导体衬底的下表面侧形成有与所述金属膜电连接的导电端子。
14.如权利要求13所述的半导体装置，其特征在于，与所述金属膜连接的配线图案形成在所述半导体衬底的下表面侧，在所述配线图案上形成有所述导电端子。
15.如权利要求12～14中任一项所述的半导体装置，其特征在于，所述电极连接部是由Ni、Au、Cu构成的层积体或由Ni、Au、Cu、Au构成的层积体。
16.如权利要求12～14中任一项所述的半导体装置，其特征在于，在所述半导体衬底的上表面侧形成有第二绝缘膜，其在所述电极连接部上设有开口部。
17.如权利要求16所述的半导体装置，其特征在于，所述第二绝缘膜包含聚酰亚胺或环氧树脂。
18.如权利要求12～14中任一项所述的半导体装置，其特征在于，在所述半导体衬底的上表面侧形成有配线，该配线中存在有所述电极连接部与所述金属焊盘的电连接。
19.一种层积型的半导体装置，其将权利要求12～18中任一项所述的半导体装置与其他的半导体装置层积，其特征在于，相互间的电连接是经由所述电极连接部而进行的。
20.一种层积型的半导体装置，其将权利要求13～18中任一项所述的半导体装置至少层积两个，其特征在于，所述至少层积了两个的半导体装置中的一个半导体装置的所述电极连接部与另一个半导体装置的所述导电端子连接。
21.一种半导体装置的制造方法，其特征在于，包括：
准备半导体衬底，其在上表面侧形成有金属焊盘，经由粘接物质粘合所述半导体衬底的上表面侧和支承体的工序；
去除所述半导体衬底的下表面而形成开口部的工序；
在所述开口部内经由绝缘膜而形成与所述金属焊盘连接的金属配线的工序；
从所述半导体衬底的下表面侧切割的工序；
分离所述半导体衬底和所述支承体的工序。
22.如权利要求21所述的半导体装置的制造方法，其特征在于，具有形成覆盖所述金属配线的保护膜的工序。
23.如权利要求21所述的半导体装置的制造方法，其特征在于，所述切割是沿在所述开口部区域设定的切割线而进行的。
24.如权利要求21所述的半导体装置的制造方法，其特征在于，所述切割是沿在除所述开口部的区域之外的区域设定的切割线而进行的。
25.如权利要求21～24中任一项所述的半导体装置的制造方法，其特征在于，在粘合所述支承体的工序中，仅在所述半导体衬底的上表面侧的周边部使用树脂。
26.如权利要求21～24中任一项所述的半导体装置的制造方法，其特征在于，在分离所述半导体衬底和所述支承体的工序中，供给使所述粘接物质溶解的溶解剂。
27.如权利要求26所述的半导体装置的制造方法，其特征在于，所述溶解剂是丙酮溶液。
28.如权利要求21～24中任一项所述的半导体装置的制造方法，其特征在于，所述粘接物质使用紫外线带或紫外线系的粘接剂，在分离所述半导体衬底和所述支承体的工序中，通过向所述紫外线带或紫外线系的粘接剂照射紫外线而将所述半导体衬底和所述支承体分离。
29.如权利要求21～24中任一项所述的半导体装置的制造方法，其特征在于，在分离所述半导体衬底和所述支承体的工序中使用刀具。
30.如权利要求21～24中任一项所述的半导体装置的制造方法，其特征在于，在分离所述半导体衬底和所述支承体的工序中，在将所述支承体粘合于所述半导体衬底上的状态下，通过浸于酸中而使所述粘接物质溶解，将所述半导体衬底和所述支承体分离。
31.如权利要求25所述的半导体装置的制造方法，其特征在于，在分离所述半导体衬底和所述支承体的工序中，通过在切削所述半导体衬底的周边部的同时切削所述树脂，从而将所述半导体衬底和所述支承体分离。
32.如权利要求21～24中任一项所述的半导体装置的制造方法，其特征在于，在分离所述半导体衬底和所述支承体的工序中，通过利用热使所述粘接物质软化而将所述半导体衬底和支承体分离。
33.如权利要求21～24中任一项所述的半导体装置的制造方法，其特征在于，所述支承体使用硅衬底、氧化膜、玻璃衬底、陶瓷衬底中的任一种。
34.如权利要求21～24中任一项所述的半导体装置的制造方法，其特征在于，在形成所述开口部的工序之前，具有研磨所述半导体衬底的下表面侧的工序。
35.如权利要求21～24中任一项所述的半导体装置的制造方法，其特征在于，在粘合所述支承体的工序之前，具有在所述半导体衬底的上表面侧形成与所述金属焊盘电连接的电极连接部的工序。
36.如权利要求35所述的半导体装置的制造方法，其特征在于，在形成所述电极连接部的工序之前，在所述半导体衬底的上表面侧形成与所述金属焊盘电连接的第一配线，接着在所述第一配线上形成所述电极连接部。
37.如权利要求35所述的半导体装置的制造方法，其特征在于，所述电极连接部包含Ni、Au、Cu中的至少一种材料。
38.如权利要求21～24中任一项所述的半导体装置的制造方法，其特征在于，具有在所述金属配线上形成导电端子的工序。
39.一种层积型的半导体装置的制造方法，其将权利要求35～37中任一项所述的半导体装置与其他的半导体装置层积，其特征在于，相互的电连接是经由所述电极连接部而进行的。
40.一种层积型的半导体装置的制造方法，其将权利要求37所述的半导体装置至少层积两个，其特征在于，所述至少层积了两个的半导体装置中的一个半导体装置的电极连接部与另一个半导体装置的所述导电端子连接。
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