TW309633B - - Google Patents
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- Publication number
- TW309633B TW309633B TW085115445A TW85115445A TW309633B TW 309633 B TW309633 B TW 309633B TW 085115445 A TW085115445 A TW 085115445A TW 85115445 A TW85115445 A TW 85115445A TW 309633 B TW309633 B TW 309633B
- Authority
- TW
- Taiwan
- Prior art keywords
- film
- insulating film
- interlayer insulating
- electrode
- silicon
- Prior art date
Links
- 239000010408 film Substances 0.000 claims description 265
- 239000011229 interlayer Substances 0.000 claims description 59
- 239000000463 material Substances 0.000 claims description 46
- 239000011347 resin Substances 0.000 claims description 45
- 229920005989 resin Polymers 0.000 claims description 45
- 239000004065 semiconductor Substances 0.000 claims description 42
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 40
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 40
- 239000010410 layer Substances 0.000 claims description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 34
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 32
- 239000011159 matrix material Substances 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 11
- 229920001721 polyimide Polymers 0.000 claims description 6
- 229920000178 Acrylic resin Polymers 0.000 claims description 5
- 239000004925 Acrylic resin Substances 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 239000002253 acid Substances 0.000 claims description 4
- 239000009719 polyimide resin Substances 0.000 claims description 4
- 239000012528 membrane Substances 0.000 claims description 3
- 239000004642 Polyimide Substances 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000004576 sand Substances 0.000 claims description 2
- 210000003625 skull Anatomy 0.000 claims description 2
- 150000001412 amines Chemical class 0.000 claims 2
- 229920000642 polymer Polymers 0.000 claims 2
- QQONPFPTGQHPMA-UHFFFAOYSA-N propylene Natural products CC=C QQONPFPTGQHPMA-UHFFFAOYSA-N 0.000 claims 2
- 125000004805 propylene group Chemical group [H]C([H])([H])C([H])([*:1])C([H])([H])[*:2] 0.000 claims 2
- 239000004020 conductor Substances 0.000 claims 1
- 239000004519 grease Substances 0.000 claims 1
- 239000002210 silicon-based material Substances 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 229910052715 tantalum Inorganic materials 0.000 claims 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims 1
- 239000010409 thin film Substances 0.000 description 47
- 239000012535 impurity Substances 0.000 description 22
- 238000004519 manufacturing process Methods 0.000 description 18
- 229910052782 aluminium Inorganic materials 0.000 description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 17
- 150000002500 ions Chemical class 0.000 description 16
- 239000010407 anodic oxide Substances 0.000 description 13
- 229910021417 amorphous silicon Inorganic materials 0.000 description 10
- 238000002048 anodisation reaction Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 9
- 239000007789 gas Substances 0.000 description 8
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 7
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 6
- 229910021419 crystalline silicon Inorganic materials 0.000 description 6
- 239000003792 electrolyte Substances 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 230000001678 irradiating effect Effects 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 3
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 3
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 239000011651 chromium Substances 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- FEWJPZIEWOKRBE-UHFFFAOYSA-N Tartaric acid Natural products [H+].[H+].[O-]C(=O)C(O)C(O)C([O-])=O FEWJPZIEWOKRBE-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 235000011114 ammonium hydroxide Nutrition 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000008595 infiltration Effects 0.000 description 2
- 238000001764 infiltration Methods 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 235000002906 tartaric acid Nutrition 0.000 description 2
- 239000011975 tartaric acid Substances 0.000 description 2
- RFSDQDHHBKYQOD-UHFFFAOYSA-N 6-cyclohexylmethyloxy-2-(4'-hydroxyanilino)purine Chemical compound C1=CC(O)=CC=C1NC1=NC(OCC2CCCCC2)=C(N=CN2)C2=N1 RFSDQDHHBKYQOD-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000007743 anodising Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 150000002009 diols Chemical class 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- GQPLMRYTRLFLPF-UHFFFAOYSA-N nitrous oxide Inorganic materials [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 1
- 235000006408 oxalic acid Nutrition 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 229910052706 scandium Inorganic materials 0.000 description 1
- SIXSYDAISGFNSX-UHFFFAOYSA-N scandium atom Chemical compound [Sc] SIXSYDAISGFNSX-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
- -1 sodium ions) Chemical class 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000010025 steaming Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 150000003608 titanium Chemical class 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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Description
A7 B7 經濟部中央橾準局員工消費合作社印製 309633 五、發明説明(1 ) 發明背景 發明領域 本發明係關於一種半導體裝置之構造,其可使用於典 型的爲活性矩陣型液晶顯示器和E L型顯示單元之平板顯 示器,且特別是關於典型爲薄膜電晶體之半導體裝置之中 間層絕緣膜構造。 相關技藝之說明 迄今,活性矩陣型液晶顯示裝置已知爲典型的平板顯 示器。其具有之結構爲開關薄膜電晶體提供在位在矩陣中 之多數圖素中之每一圓素中,且充電输入/輸出由1至每 個圓素電極由薄膜電晶體控制》 在此種構造中,必需以絕緣膜塗覆半導體裝置以防止 涇氣,雜質和移動離子(例如鈉離子),其會嚴重的影響 半導體裝置之滲入。再者,其必需適當的構造以使介於圖 素電極,接線和薄膜電晶體間產生之電容可降低。 再者,所需的是具有低生產成本和良好的生產率。但 是,現有的情況是以一般使用當成中間層絕緣膜之氧化矽 膜或氮化矽膜並無法滿足上述之需求。 發明概要 因此,在本發明之說明書中所揭示之目的乃在於提供 一種前述中間層絕緣膜之新穎構造。 本紙張尺度適用中國國家標準(CNS ) A4规格(210X 297公釐) (請先閲讀背面之注意事項再填寫本頁)
A 7 __^_ B7_ 五、發明説明(2 ) 亦即,本發明之目的乃在提供一種半導髏裝置之構造 ,其具有中間層絕緣膜以防止涇氣和雜質之滲入,且可抑 制產生在薄膜電晶體,圖素《極,和接線間之電容,生產 成本低,且具有高的生產率。 依照本發明之一觀點,一種半導體裝置,包含:一中 介層絕緣膜,其由設置在一半導髗元件之上部份上之樹脂 材料形成;和一氧化矽膜或氮化矽膜形成當成一下層,而 中間層絕緣膜形成在該下層之叠層膜之整個表面上。 依照本發明之另一結構,一種半導體裝置,包含:一 中介層絕緣膜,其由設置在一半導體元件之上部份上之樹 脂材料形成;和一氧化矽膜或氮化矽膜之叠層膜形成當成 一下層,而中間層絕緣膜形成在該下層之整個表面上。 在上述之構造中,氧化矽膜或氮化矽膜可首先放置在 曼層之順序中。但是,當.半導體元件欲覆蓋時,由黏著性 和良好的介面特性而言,最好使氮化矽膜當成下層。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 依照本發明之另一結構,一種半導體裝置_,包含:一 中介層絕緣膜,其由設置在一半導體元件之上部份上之樹 脂材料形成:和一氮氧化矽膜形成當成一下層,而中間層 絕緣膜形成在該下層之整個表面上。 依照本發明之另一結構,一種半導體裝置,包含:一 中介層絕緣膜,其由設置在一半導體元件之上部份上之樹 脂材料形成:和一氧化矽膜或氮化矽膜形成在該半導體元 件和該中間層絕緣膜間。 依照本發明之另一觀點,一種半導體裝置,包含:一 本紙張尺度適用中國國家標準(CNS ) A4规格(2IOX 297公釐) A7 B7 經濟部中央標準局負工消費合作社印製 309633 五、發明説明(3 ) 中介餍絕緣膜’其·由設置在—半導體元件之上部份上之樹 /脂材料形成:和一^氧化矽膜形成在該半導體元件和該中間 層絕緣膜間。 依照本發明之又一觀點,一種半導體裝置,包含:一 中介層絕緣膜’其由設置在一半導體元件之上部份上之樹 脂材料形成;和一氧化矽膜或一氮化矽膜之叠層膜乃形成 在該半導體元件和該中間層絕緣膜間。 藉由使用氮化矽膜和樹脂膜之叠層膜當成中間層絕緣 膜以覆蓋薄膜電晶體之上部份,則可降低產生在介於圖素 電極,接線和薄膜電晶體間之電容。 再者,由於可使樹脂材料之表面平坦化,則不會形成 跨過在接線位準中之差異之部份,藉此可避免接線電阻之 局部改變和接線之斷裂。 再者,藉由提供氮化矽膜於樹脂膜和薄膜電晶體之間 ,以使樹脂膜不會與薄膜電晶體直接接觸’如此可抑制在 樹脂膜中之涇氣免於對薄膜電晶體之操作有不良的效果。 由下述之說明書之說明及圖式之解說可明顯的了解上 述及其它相關之目的和特點’以及在申請專利範圍中指出 之新穎性。 圖式簡單說明 圖1 A至1 D爲製造活性矩陣電路之圖素部份之步驟 之圖; 圖2 A和2 B爲製造活性矩陣電路之圖素部份之步驟 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁)
A7 B7 五、發明説明(4 ) 之圖: 圖3 A和3 B爲製造活性矩陣電路之圖素部份之步驟 之圖; 圖4爲製造活性矩陣電路之圖素部份之步驟之圖; 圚5 A至5 F爲製造構成當成一互補型電晶體之薄膜 電晶體之步驟圖;和 圖6 A至6 E爲製造薄膜電晶體之步驟圖。 較佳資施例之說明 〔第一實施例〕 圖1和2爲製造依照本發明之活性矩陣型液晶顯示器 之圖素部份之步驟圖。 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 首先,如圖1A所示,藉由電漿CVD,在玻璃基底 1 0 1上形成3000A厚之氧化矽膜1 02當成下曆。 •此下層具有抑制雜質由玻璃基底擴散至隨後形成之半導體 層之功能。其亦可釋除作用在介於玻璃基底和半導體層間 之應力之功能。 亦可使用氮氧化矽膜當成下層。由於氮氧化矽膜膜較 密且與玻璃基底間具有較高的黏著性,其更可作用當成下 層。 氮氧化矽膜亦可藉由電漿CVD使用矽烷,氧氣和 N20之混合氣體而形成。其亦可利用電漿C VD以 T E 0 S氣體和N2〇之混合氣體形成》 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公廢) 經濟部中央標準局員工消費合作社印製 A7 _B7_ 五、發明説明(5 ) '其次,形成未顯示之非晶矽膜。此非晶矽膜變成薄膜 半導體之啓始膜,而該薄膜半導體構成薄膜電晶體之活性 層》藉由使用低壓熱CVD,可形成5 Ο 0A厚之非晶矽 膜》值得注意的是電漿C VD可使用當成形成非晶矽膜之 方法。 而後,非晶矽膜以熱處理,雷射光之照射,或熱處理 和雷射光之照射之組合而結晶。因此,可得到結晶矽膜。 而後,結晶矽膜定圖樣以獲得薄膜電晶镫之活性層( 圖 1 A )。 其次,覆蓋活性層1 〇 3 (如圖1 A所示)且作用當 成閘絕緣膜之氧化矽膜1 0 4藉由電漿CVD形成 1 Ο Ο 0A之厚度。因此,可獲得圖1 A所示之狀態。 最好使用氮氧化矽膜當成作用成閘極絕緣膜之絕緣膜 〇 其次,以濺鍍法形成4000A厚之含有0. 1重量 百分比之銃之鋁膜。此鋁膜而後構成閘電極。 在形成鋁膜後,未顯示之密陽極氧化膜形成1 〇 〇 〇 A之厚度在表面上。使用電解質進行陽極化,其中含3% 酒石酸之乙二醇溶液以氨水中和,且在電解質中設定鋁膜 當成陽極。 在此陽極化中’欲形成之陽極氧化膜之厚度由所得之 電壓控制。 再者,設置阻止掩模以執行定圖樣以形成一閘電極 10 5。 本紙张尺度適用中關家料(CNS ) A4規格(21GX297公釐)~ 一 (請先閲讀背面之注意事項再填寫本頁)
經濟部中央標準局員工消費合作社印製 A7 B7五、發明説明(6 ) 在形成閘電極1 0 5後,再度執行陽極化,並留下未 顯示之阻止掩模。使用3 %草酸溶液當成電解質而進行陽 極化。 在此陽極化中,由於仍保留有阻止掩模,因此只有閘 電極1 0 5之側邊選擇性的陽極化。因此在此步驟中,可 獲得具有多孔構造之陽極氧化膜。 因此,具有多孔特性之陽極氧化膜1 0 6形成在閘電 極105之側面上。 · 多孔陽極氧化膜可成長至厚度約爲數微米。此成長距 離可由陽極化時間控制。此處之陽極氧化膜1 0 6之厚度 爲 3 0 0 0 A。 其次,使用電解質再度執行陽極化,其中含有3%酒 石酸之2二醇溶液可利用氨水中和。由於在此陽極化步驟 中,電解質滲入多孔陽極氧化膜1 0 6之內側’因此’密 陽極氧化膜1 0 7環繞閘電極1 0 5形成。 密陽極氧化膜1 0 7之厚度爲5 0 0A。密陽極氧化 膜1 0 7之主要角色爲覆蓋閘電極1 〇 5之表面,以使在 後績步驟中,不會成長小丘或鑀。其另一角色爲保護閘電 極1 0 5以使在後績移去多孔陽極氧化膜時,閘電極 1 0 5不會受到蝕刻。此外’其亦有助於在後縯之射出雜 質離子之步驟中,形成偏置閘區域。因此,可獲得圖1 B 所示之狀態。 在此狀態中注入雜質離子。此處,注入P (磷)離子 以獲得N通道型薄膜電晶體。 本紙乐尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁)
309633 經濟部中央橾準局員工消費合作社印製 五、發明説明(7 ) 當雜質離子在圖1 B所示的狀態注入時,雜質離子選 擇性的注入區域1 0 8和1 1 1中。在此步驟中’區域 1 0 8和1 1 1變成高濃度雜質區域。 由於閘電極1 0 5變成一掩模,則不會有雜質離子注 入剛好在閘電極1 0 5下方之區域1 0 9。此區域1 0 9 變成通道形成區域。 再者,由於多孔陽極氧化膜1 0 6和密陽極氧化膜 1 0 7變成掩模,則亦無雜質離子注入區域1 1 〇中。此 區域1 1 0爲一偏置閘區域,其非但未作用當成一源/汲 極區域,亦米作用當成一通道形成區域。偏置閘區域之尺 寸可依照密陽極氧化膜1 0 7之厚度和多孔陽極氧化膜 106之厚度而決定* 偏置閘區域可釋除形成在通道形成區域和汲極區域間 之電場之應力。偏置閘區域之存在可使薄膜電晶體之截斷 霉流值降低並抑制損壞。 因此,源區域108·,通道形成區域109 ,偏置閘 區域1 1 0,和汲極區域1 1 1以自我對準方式形成》 值得注意的是,此處揭示一方法以在雜質離子注入後 移去多孔陽極氧化膜,且在輕摻粗狀況下再度注入粗質。 在此例中,輕摻雜區域可形成在多孔陽極氧化膜1 0 6之 正下方。輕摻雜區域之汲極側一般稱爲L D D (輕摻雜汲 極)區域。 在注入雜質離子後,選擇性的移除多孔陽極氧化膜 106。此處,多孔陽極氧化膜106使用磷酸,醋酸, (請先閱讀背面之注意事項再填寫本頁) 訂 泉 本紙張尺度適用中國國家標準(CNS ) Λ4規格(210X 297公釐) 10 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明(8 ). 和硝酸之混合酸選擇性的移除。 而後,以照射雷射光執行退火處理。由於雷射光在此 時可照射至介於高濃度雜質區域和偏置閘區域間之介面附 近,因此由雜質離子之注入而破壤之接面部份可完全的退 火。 除了雷射光外,上述之退火亦可藉由照射紫外線或紅 外線而執行。配合雷射光或強光之照射之加熱定相當有效 的。 ‘ 在獲得如圖1 B所示之狀態之後,形成2 0 0 0左厚 之氧化矽膜1 1 2當成第一中間層絕緣膜。對於第一中間 厝絕緣膜而言,可使用氮化矽膜或氧化矽膜和氮化矽膜之 叠層膜。 其次,經由第一中間層絕緣膜1 1 2形成一接觸孔, 以形成一源電極1 1 3和薄膜電晶體之源區域接觸。源電 極1 1 3具有鈦膜,鋁膜和鉅膜之叠餍構造。此源電極亦 當成由源極線延伸之部份。亦即,其和位在活性矩陣區域 之矩陣中之源極線同時形成。因此,可獲得如圓1 C所示 之狀態。 其次,形成具有1000A厚之氮化矽膜1 14,氮 化矽膜藉由使用其密膜品質(通常氮化矽膜之膜品質較密 )而具有一功能以抑制固定電荷存在於薄膜電晶體之介面 中。其另具有之功能爲利用密膜品質而防止涇氣和移動雜 子由外界滲入。 使用電漿CVD利用矽烷和氨而形成氮化矽膜1 1 4 本紙張尺度適用中國國家標準(CNS ) Μ規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁)
11 - 經濟部中央標準局員工消费合作社印製 Α7 Β7 五、發明説明(9 ) 。除了氮化矽膜外,亦可使用氮氧化矽膜。 其次,藉由電漿CVD可形成2 Ο Ο 0A厚之氧化矽 膜1 1 5。雖然形成氧化矽膜1 1 5以加強其可靠度,但 是亦可不特別的使用。 再者,藉由使用透明聚醯亞胺樹脂或丙烯酸樹脂可形 成中間層絕緣膜1 1 6。由樹脂材料製成之中間層絕緣膜 116之厚度爲2#m。因此,可得画1D之狀態。 藉由使用樹脂材料產生中間層絕緣膜,可降低介於元 件和形成在中間層絕緣膜上之電極和接線間之電容。再者 ,亦可顯著的降低生產成本* 由於氧化矽膜115形成當成下層在以樹脂材料製成 之中間層絕緣膜下方,可增加與下層間之黏著性。再者, 其亦可提供一結構以抑制涇氣滲入氧化矽膜115和欲形 成之下層間。 即使當由樹脂材料形成之中間層絕緣膜形成在氮化矽 膜1 1 4上時,亦可獲得此效果一-#無需形成氧化—矽膜 115。 其次’作用當成光遮蔽膜和當成異矩陣之鉻膜形成和 定圇樣以形成一作用當成如圚2 A所示之光遮蔽膜之蒸矩 陣 1 1 7。 可選擇介電常數小於3之樹脂材料以用於構成中間層 絕緣膜1 1 6之樹脂材料。其厚度可增加至數μιη。即使 樹脂材料之厚度變厚,由於製造步驟之時間不會延長,因 此其結果亦是相當良好的。 本紙張尺度適用中國國家標準(CNS ) Α4規格(21〇χ 297公釐) (請先閲讀背面之注意事項再填寫本頁)
-12 - A7 B7 經濟部中央標準局員工消費合作社印製 五、 發明説明 10 ) 1 I 藉 由 上 述 之 構 造 可 抑 制 電 容 免 於 產 生 在 由 鉻 所 製 成 1 1 之 光 遮 蔽 膜 和 下 層 薄 膜 電 晶 體 之 間 9 1 1 再 者 當 以 樹 脂 材 料 製 成 時 可 輕 易 的 使 薄 膜 電 晶 體 1 | 請 1 I 1 1 6 之 表 面 平 坦 且 可 抑 制 由 其 不 規 則 性 所 引 起 之 光 之 先 閱 1 | 讀 1 洩 漏 0 背 1 I 之 1 在 獲 得 如 圖 2 A 所 示 之 狀 態 之 後 進 — 步 形 成 氮 化 矽 意 1 I 膜 當 成 中 間 層 絕 緣 膜 1 1 8 〇 而 後 進 —. 步 形 成 氧 化 矽 膜 事 項 再 1 1 1 1 9 〇 填 窝 本 •K· Η 1 雖 然 此 處 採 用 Jmr m 化 矽 膜 和 氧 化 矽 膜 之 兩 層 搶 m 造 以 增 加 Ά 1 1 可 靠 度 亦 可 採 用 它 們 任 一 之 單 層 結 構 0 1 1 再 者 形 成 由 樹 脂 材 料 製 成 之 中 間 層 絕 緣 膜 1 2 0 0 1 | 此 材 料 可 以 和 中 間 層 絕 緣 膜 1 1 6 相 同 〇 訂 藉 由 以 樹 脂 材 料 形 成 中 間 層 絕 緣 膜 1 2 0 可 抑 制 產 1 1 | 生 在 稍 後 形 成 之 90 素 電 極 和 薄 膜 電 晶 體 間 之 不 必 要 之 電 容 \ 1 1 〇 再 者 由 於 表 面 可 平 坦 化 亦 可 抑 制 稍 後 產 生 來 白 困 素 1 1 1 電 極 之 電 場 負 於 受 到 干 擾 0 ,成’ 而 後 形 成 — 接 觸 孔 藉 由 測 鍍 形 成 用 以 形 成 圖 素 電 1 1 極 之 I T 〇 電 極 且 其 定 圖 樣 以 產 生 圃 素 電 極 1 2 1 〇 1 | 因 此 可 完 成 圖 2 B 所 示 之 構 造 〇 由 於 位 在 薄 膜 電 晶 1 I 體 ( 特 別 是 源 電 極 1 1 3 ) 和 光 遮 蔽 膜 ( 和 / 或 異 矩 陣 ) 1 1 1 1 1 7 之 中 間 層 絕 緣 膜 之 公 電 常 數 可 降 低 且 其 厚 度 可 增 厚 1 » 如 圚 2 B 所 示 之 構 造 可 防 止 不 必 要 之 電 容 產 生 〇 1 1 由 於 可 輕 易 的 使 樹 脂 膜 增 厚 且 不 會 增 加 處 理 時 間 » 1 1 因 此 可 迅 速 的 完 成 上 述 之 構 造 〇 1 1 準 標 家 國 國 中 用 適 尺 張 紙 本 釐 公 經濟部中央橾準局員工消費合作杜印製 309633 a? B7 五、發明説明(11 ) 〔第二實施例〕 本實施例之特徼在於進一步的改善第一實施例所示之 構造,以增加可靠度。 » 如上所述,例如鉻之金屬材料乃使用於光遮蔽膜和黑 矩陣。但是,當相關於長期可靠度時,會有由金屬材料擴 散雜質之問題和由介於金屬材料和其它電極和接線間所引 起之短路之問題。 · 而後,在本實施例所示之構造中,一可陽極化材料Ψ 用當成光遮蔽jP以遮蔽薄膜電晶體’且除了第一資施例所 示之構造外,一陽極氧化極可形成在表面上。 可使用鋁或鉅當成可陽極化材料。當使用鋁時,由於 陽極氧化膜可著色成黑色或接近使用在例如鋁帶之工業產 品之陽極技術之彩色,因此可形成適當的光遮蔽膜。 圖3 Α和3 Β爲本實施例之示意製造步驟。值得注意 的是和圖2相同的零件並未特別顯示在圖3 A和3 B中。 首先,如圖1 D所示之狀態由下述圖1 A至1 D所示 之步驟而得。其次,形成如圖3 A所示之光遮蔽膜3 0 1 。此處*光遮蔽膜3 0 1使用鋁當成材料而形成。 而後,藉由在電解質中執行陽極化,陽極氧化膜 3 0 2形成在光遮蔽膜3 0 1之表面上,如圖3A所示。 雖然光遮蔽膜3 0 1如同在圖中用以遮蔽薄膜電晶體 之光遮蔽膜,其仍可正常延伸以形成黑矩陣。 在獲得如圖3 A所示之狀態後,由氮化矽膜和氧化矽 本紙張尺度適用中國國家樣準(CNS ) A4規格(210X 297公釐) (請先鬩讀背面之注意事項再填寫本頁)
-14 - 經濟部中央標準局員工消費合作社印製 A7 ____B7 五、發明説明(l2 ) 膜構成之中間層絕緣膜和由樹脂材料構成之中間層絕緣膜 形成在多層中。
再者,以I TO形成圓素電極,藉此可獲得如圖3 B 所示之狀態。 由於陽極氧化膜3 0 2化學穩定,在本實施例中所示 之構造在相關於長時間之可靠度時,亦可抑制雜質免於由 光遮蔽膜3 0 1進入週圍。再者,光遮蔽膜亦可免於短路 〔第三實施例〕 本實施例係關於一種構造,其中圖索之孔徑比進一步 增加。一般而言,需儘可能的增加圖素之孔徑比。此外, ———.—- - 必需設置圈素電極在儘可能宽的區域中,以增加圈素之孔 徑比。 但是,當圖素電極和薄膜電晶體以及接線互相重置, 由於其間會產生電容,在此觀點中會形成顯著的限制·。 本實施例可提供用以降低產生電容問題之構造。 圖4爲本實施例之構造。在圖4所示之構造中*位在 矩陣中之源極線和閘極線會作用當成黑矩陣,且圖素電極 4 0 2之區域會儘可能的增加。 在圖4所示之構造中,用以覆蓋薄膜電晶體之主要部 份之光遮蔽膜4 0 1以形成源電極(和源極線)之金屬材 料形成。 藉由設置圖素電極即可使用部份的源極線和閘極線當 本紙^尺度適用中國國家標準(CNS ) A4规格(210X 297公釐) (請先閲讀背面之注意事項再填寫本瓦) 訂 經濟部中央標準局員工消費合作社印製 A7 ____B7__ 五、發明説明(l3 ) 成黑矩陣,以使部份的源極線和閘極線重叠圖素電極。 當採用如圖4所示之構造時*由於圖素電極可設置跨 過寬度區域,因此可增加圖素之孔徑比。 再者,即使採用此種構造,由於存在有由樹脂材料製 成之中間層絕緣膜1 1 6,因此可降低介於圓素電極 4 0 2和薄膜電晶體間產生之電容。 再者,藉由使用樹脂材料當成中間層絕緣膜|亦可減 輕不必要的壓力在形成圖素電極4 0 2之後之磨擦步驟和 板組裝步驟中施加至薄膜電晶體。 氧化矽膜115形成穿過在形成中間層絕緣膜之樹脂 材料1 1 6下方之整個表面上,且氮化矽膜1 1 4形成在 其下方。由於中間層絕緣膜覆蓋有氮化矽膜1 1 4,如此 可確保薄膜電晶體之電穩定性。 由於氮化矽膜114可使涇氣免於由以樹脂材料製成 之中間層絕緣膜116擴散至薄膜電晶體部份·則可增^ 薄膜電晶體之電穩定性。 •. — ...» 〔第四實施例〕 本實施例顯示N通道型薄膜電晶體和P通道型薄膜電 晶體互補形成之例。 本實施例之構造可使用於整合絕緣表面上之各種薄膜 積體電路。其亦可使用於活性矩陣型液晶顯示器之週邊驅 動電路。 首先,氧化矽膜或氮化矽膜當成一底層膜5 0 2而形 本紙伕尺度適用中國國家標準(CNS ) Λ4規格(210X 297公釐) ~ 一 16 - (請先閱讀背面之注意事項再填寫本頁)
309633 五、發明説明(l4) (請先閲讀背面之注意事項再填寫本頁) 成在玻璃基底5 0 1上,如圖5A所示。再者,藉由電娥 C V D或低壓熱C VD而進一步形成未顯示之非晶矽膜。 此非晶矽膜以照射雷射光或應用熱至非晶矽膜而轉換成結 晶矽膜。 如此所得之結晶矽膜定圖樣以獲得活性層5 0 3和 504。因此,可得^5A所示之狀態。 再者,形成由閘絕緣膜構成之氧化矽膜5 0 5。而後 ,形成4 0 0 0A厚之鋁膜以隨後形成一閘電極。除了鋁 膜外,亦可使用可陽極化金屬(例如鉅)。 在形成鋁膜後,以上述之方法在表面上形成非常薄且 密之陽極氧化膜。 其次,阻止掩模設置在鋁膜上以定圖樣鋁膜。而後, 使用所獲得的鋁圖樣當成陽極而執行陽極化以形成多孔陽 極氧化膜5 0 8和5 0 9。多孔陽極氧化膜之厚度爲 5 0 0 0 A。 經濟部中央橾準局員工消費合作社印製 在形成密陽極氧化膜之條件下再度執行陽極化以形成 密陽極氧化膜510和511。密陽極氧化膜510和 51 1之厚度爲800A。因此,可得圖5B之狀態。 而後,藉由乾蝕刻而移去曝露之氧化矽膜,因此可獲 得如圖5 C所示之狀態* 在獲得圖5 C所示之狀態後,使用醋酸,硝酸和磷酸 之混合酸移除多孔陽極氧化膜5 0 8和5 0 9 »因此,可 獲得如圖5 D之狀態。 阻止掩模交替的設置以使P離子注入在薄膜電晶體和 本紙張尺度適用中國國家揉準(CNS ) A4規格(210X 297公釐) -17 - 經濟部中央樣準局貝工消費合作社印製 A7 B7 五、發明説明(15 ) B離子注入右薄膜電晶體。 藉由注入雜質離子,高濃度N型源極區域5 1 4和汲 極區域5 1 7以自我自準方式形成* 再者,摻雜以低澳度之P離子之弱1^型區域乃同時形 成》再者,通道形成區域516亦可時形成。 由於存在有閘絕緣膜5 1 2 ’可形成弱N型區域 5 1 5。亦即,經由閘極絕緣膜5 1 2轉送之P離子乃由 閘絕緣膜512部份的阻擋。 ’ 強P型源區域5 2 1和汲極區域5 1 8以相同原理用 自我對準方式形成。低澳度雜質區域5 2 0以及通道形成 區域519亦同時形成。 當密陽極氧化膜5 1 0和5 1 1之厚度爲2 Ο Ο 0A 時,藉由此厚度和通道形成區域接觸’可形成一偏置閘區 域。 但是由於密陽極氧化膜510和511之厚度薄至小 於1 0 0 0A,因此在此資施例中可忽略偏置閘區域之存 在。 而後,以雷射光或強光照射退火已注入雜質離子之區 域。 而後,氮化矽膜5 2 2和氧化矽膜5 2 3形成中間層 絕緣膜,如圖5 E所示它們的厚度爲1 〇 〇 〇A。值得注 意的是可以不形成氧化砂膜5 2 3。 於此,薄膜電晶體以氮化矽膜覆蓋。由於氮化矽膜較 密且具有良好的介面特性’藉由採用此種構造可增力卩薄膜 本紙張尺度適用中國國家標率(cNS) A4規格(210x297公釐) (請先閲讀背面之注意Ϋ項再填寫本頁) 丁, 、-'° Γ -18 - 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明(l6 ) 電晶體之可靠度。 再者,藉由使用旋轉塗覆可形成以樹脂材料製成之中 間層絕緣膜5 2 4。此處,中間曆絕緣膜5 2 4之厚度爲 1 β m (圚 5 E )。 而後,形成接觸孔和形成左N通道型薄膜電晶體之源 電極5 2 3和汲極鬣極5 2 6 »同時,形成右薄膜電晶體 之源電極5 2 7和汲極電極5 2 6。此處,汲極電極 5 2 6共同設置。 . 因此,可形成具有互補構造CMO S構造之薄膜電晶 體。. 在本資施例之構造中,薄膜電晶體以氮膜和樹脂材料 --------------------—-—-------^ 覆蓋。此種構造可形成移動離子和涇氣雖以滲入且具有髙 '1 — ™" V........—------------- 1 ___ _ — , — II I .f ^^ ---------~' 度< 耐用性之裝置。 再者,當形成多厝接線時,可防止在薄膜電晶體和接 ' '— ------ 鶴_間產生電_容。 〔第五實施例〕 本實施例顯示用以製造所謂的底閘厚薄膜電晶體之薄 膜電晶體之製造步驟,其中閘電極位在基底之側邊而非位 在活性層上。 圖6 A至6 E爲本實施例之製造步驟。首先,如圖6 A所示,藉由濺鍍成氧化矽膜6 0 2在玻璃基底6 0 1上 當成一底層。其次,以鋁形成閘電極6 0 3。 此時,0 . 1 8重量百分比之钪包含在鋁中。再者, 本紙張尺度適用中國國家標準(CNS ) A4规格(21〇Χ29"7公釐) (請先閲讀背面之注$項再填寫本頁)
,1T 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明(l7 ) 儘可能的降低其它雜質以降低它們的澳度•執行這些步驟 以抑制在後績步驟中由於鋁之異常成長而形成所謂的小丘 或纘之突起。 因此,可得圈6 A所示之狀態。其次,以電漿CVD 形成5 Ο 0A厚之氧化矽膜6 0 4作用當成閘絕緣膜》 再者,未顯示之非晶矽膜(其隨後樊成結晶矽膜 605),且其爲用以形成薄膜電晶體之活性層之啓始膜 )乃由電漿CVD法形成。除了電漿CVD法外,亦可使 用低壓熱CVD法。 其次,以雷射光照射而使非晶矽膜結晶。因此,可得 結晶矽膜6 0 5。 因此,可得圖6 B所示之狀態。在獲得圖6 B所示之 狀態後,執行定圖樣以獲得活性層6 0 6。 其次,形成氮化矽膜,且藉由使用閘電極以由基底 6 0 1之背面執行曝光,以形成由氮化矽膜所製成之掩模 圖樣6 0 7。 此掩模圖樣6 0 7之形成如下所述。首先,使用閘電 極6 0 3之圖樣,藉由從基底6 0 1之背面曝光以形成阻 止掩模圖樣。再者,執行除灰以退卻阻止掩模圖樣。而後 ,使用退卻之阻止掩模圖樣(未顯示)定圖樣氮化矽膜以 獲得圖樣6 0 7。 因此,可得圖6 C之狀態。其次,藉由使用掩模圚樣 607摻雜雜質。此處,使用P(磷)當成摻雜劑且使用 電漿摻雜當成摻雜之機構。 本紙張尺度適用中國國家標準(〔阳)八4規格(210/297公釐)_ (請先閱讀背面之注意事項再填寫本頁)
經濟部中央標準局員工消費合作社印製 Α7 Β7 五、發明説明(18 ) 在此步驟中,p摻雜至區域6 〇 8和6 1 0中。P並 未摻雜至區域609中。 在完成此摻雜後’藉由從頂部照射雷射光而執行由接 雜離子之衝擊而引起之破壤之退火和摻雜區域之活化。 因此,區域608當成源極區域。再者,區域610 當成汲極區域。而後區域6 0 9界定當成通道區域。 因此,可得園6 D之狀態。其次,由氮化矽膜製成之 中間層絕緣膜6 1 1以電漿CVD形成2 0Ό 0A之厚度 〇 此處最好使用氮化矽膜當成中間層絕緣膜,此乃因爲 氮化矽膜在避免涇氣存在於於後形成之樹脂中間層(作用 於活性層6 0 6 )具有最佳之效果。 除了氮化矽膜外,亦可使用氧化矽膜,氮氧化矽膜, 或氧化矽膜和氮化矽膜之叠層膜(它們兩者之任一個皆可 位在叠餍之首先次序上)。 其次,以聚醯亞胺製成之樹脂膜6 1 2形成當成中間 層絕緣膜。其藉由旋轉塗覆形成。 再者,形成接觸孔以當成源極電極6 1 3和汲極電極 6 14。 於此有一問題爲當使用樹脂材料當成中間層絕緣膜時 ’裝置之特性會由存在於樹脂材料中之涇氣(特別是〇 Η 根)所影響。但是,當使用樹脂材料當成中間層絕緣膜時 所引起之問題可藉由如本實施例所述提供可使涇氣免於移 動之氮化矽膜而加以抑制》 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X 297公釐) (請先閱讀背面之注意事項再填寫本頁)
A7 B7 五、發明説明(l9 ) 在本發明之說明書中所揭示之使用可獲得—種半導體. 裝置之構造,餘半導體可提供高可靠度’抑制產生在薄膜 電晶體和圓素電極以及接線間產生之電容之問題’並可提 供低成本和高製造率之半導體裝置。本發明之說明書中所 揭示者不僅可用於活性矩陣型液晶顯示裝置’且亦可應用 於EL型顯示器和IC電路。 雖然本發明已藉由較佳實施例而說明,對於熟悉此項 技藝之人士而言仍可能有許多的變化,而這些變化仍靨於 本發明下述申請專利範圍之範疇。 (請先閲讀背面之注意事項再填寫本頁)
、1T 經濟部中央標準局員工消費合作社印裝 本紐尺度適财國) M規格(2ι〇χ297公慶) -22 -
Claims (1)
- A8 B8 C8 D8 3^9633 々、申請專利範圍 1. —種半導體裝置,包含: 一中介層絕緣膜,其由設置在一半導«元件之上部份 上之樹脂材料形成;和 -g化矽膜或氣化矽膜形成當成一下層’而中間層絕 緣膜形成在該下層之整個表面上。 2. 如申請專利範園第1項之半導髏裝置,其中該樹 脂材料包含聚醯亞胺樹脂或丙烯酸樹脂。 3. —種半導髓裝置,包含: . 一中介層絕緣膜,其由設置在一半導髏元件之上部份 (請先閣讀背面之注意Ϋ項再填寫本頁) 層 下 一 成 當 成 形 膜 屠 叠 之 膜 矽 和化 •’氮 成和 形膜 料矽材化一 脂氧一 樹一 之. 上 樹 該 中 其 置 。 裝 上體 面導 表半 個之 整項 之 3 層第 下園 該範 在利 成專 形請 膜申 緣如 絕 層 4 間 中 份 部 上 之 件 元 體 。 導 脂 半 樹 一 酸:在 烯含置 丙包設 或,由 脂置其 樹裝, 胺體膜 亞導緣 醯半絕 聚種層 含 一 介 包 中 料 5 | 材 脂 J*s t- 經濟部中央揉準局負工消费合作社印製 成 形 膜 緣 絕 層 間 中 而 層 下1 成 當 和成 ;形 成 j 形I 料化 材氧 脂氮 樹 之 上 樹 該 中 其 , 置 裝 髏 導 半 之 項 5 第 。 圍 上範 面利 表專 個請 整申 之如 層 下 6 該 在 脂 樹 酸 . 烯含 丙包 或, 脂置 樹裝 胺體 亞導 醯半 聚種 含 一 包 料 7 材 脂 份 部 上 之 件 元 體 導 半1 在 置 設 由 其 , 和 膜 : 緣成 絕形 層料 介材 中脂 1 樹 之 上 本紙張尺度適用中國國家揉準(CNS > A4規格(210X297公釐) 經濟部中央標準局貝工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 一也矽膜和氮化矽膜之叠層膜形成在該半導體元件 和該中間層絕緣膜間。 8. 如申請專利範圔第7項之半導髏裝置,其中該樹 脂材料包含聚醣亞胺樹脂或丙烯酸樹脂。 9. —種半導體裝置,包含: 一中介層絕緣膜,其由設置在一半導體元件之上部份 上之樹脂材料形成;和 —氮氧化砂膜形成在該半導體元件和該中間靥絕緣膜 間。 10. 如申請專利範園第1項之半導體裝置,其中該 樹脂材料包含聚醣亞胺樹脂或丙烯酸樹脂0 11. 一種半導體裝置,包含: 一中介層絕緣膜,其由設置在一半導體元件之上部份 上之樹脂材料形成;和 —氧化—食ui矽膜之*層膜乃形成在該半導體 - .- 一·.〆 --------一_〆-------- 元件和該中間層絕緣膜間。 12. —種半導體裝置,包含: 一·電晶體I 一電極連接該電晶體之源和汲極之一: 第一中間層絕緣膜,其由形成在該電極上之氧化矽或 氮化矽形成; 第二中間層絕緣膜,其由形成在該第一中間層絕緣膜 上之樹脂材料所形成’·和 一光屏蔽或黑矩陣膜提供在該電極上。 本紙浪尺度逋用中譎國家楳準(CNS > A4现格(210X297公釐) (請先W讀背面之注意事項再填寫本頁) ,νβ A8 B8 C8 ___________D8 六、申請專利範園 1 3 .如申請專利範園第1 2項之半導《裝置,其中 該樹脂材料包含聚醯亞胺樹脂或丙烯酸樹脂。 光屏蔽或黑仂陣膜提供在該電極上。 1 4 ·如申請專利範圈第1 2項之裝置,其中該電晶 體包含一半導體層提供在一基底上且包含該源極,該汲極 ’和介於該源極和汲極間之通道;一閘絕緣膜形成在該半 導體靥上;和一閘電極形成在該閘絕緣膜上。 15. —種半導體裝置,包含: 一電晶體; ——電極連接該電晶體之源和汲極之一: 第一中間層絕緣膜,其由形成在該電極上之氧化矽或 氮化矽形成; 第二中間層絕緣膜,其由形成在該第一中間層絕緣膜 上之樹脂材料所形成; 一光屏蔽或黑色矩陣膜提供在該電極上; 第三中間層絕緣膜包含形成在該第二中間餍絕緣膜上 之氮化矽或氧化矽,在該光屏蔽或黑矩陣膜上; 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 第四中間餍絕緣膜形成在該第三中間層絕緣膜上;和 一圖素電極形成在該第四中間層絕緣膜上。 16. —種半導體裝置,包含: 一閘電極形成在一基底上: 一閘絕緣膜形成在該閘電極上: -半導體膜形成在該閘絕緣膜上且包含一源極,一汲 極和提供在源極和汲極間之通道; 本紙張尺度逋用中国國家橾率(CNS ) A4規格(210X297公釐) -25 - 經濟部中央標準局貝工消费合作社印製 A8 B8 C8 D8 六、申請專利範圍 一氧化矽或氣化矽中間厝絕緣膜形成在該半導體膜上 :和 一樹脂中間層絕緣膜形成在該氧化矽或氮化矽中間層 絕緣膜上。 本紙張尺度逋用中國國家梯準(CNS ) A4规格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁)-26 -
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US6441468B1 (en) | 2002-08-27 |
US20050023526A1 (en) | 2005-02-03 |
US20020175345A1 (en) | 2002-11-28 |
KR100386204B1 (ko) | 2003-06-09 |
US7202551B2 (en) | 2007-04-10 |
KR100458656B1 (ko) | 2004-12-03 |
US7034381B2 (en) | 2006-04-25 |
KR100351777B1 (ko) | 2003-01-06 |
US6787887B2 (en) | 2004-09-07 |
US5990542A (en) | 1999-11-23 |
US6445059B1 (en) | 2002-09-03 |
KR100446272B1 (ko) | 2004-09-03 |
US7413937B2 (en) | 2008-08-19 |
US20060163576A1 (en) | 2006-07-27 |
US20070173058A1 (en) | 2007-07-26 |
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