KR930024548A - 회로형성용기판의 제조방법 및 회로형성용기판 및 이것을 사용한 다층회로기판 - Google Patents

회로형성용기판의 제조방법 및 회로형성용기판 및 이것을 사용한 다층회로기판 Download PDF

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KR930024548A
KR930024548A KR1019930007634A KR930007634A KR930024548A KR 930024548 A KR930024548 A KR 930024548A KR 1019930007634 A KR1019930007634 A KR 1019930007634A KR 930007634 A KR930007634 A KR 930007634A KR 930024548 A KR930024548 A KR 930024548A
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circuit
porous
conductive paste
metal foil
hole
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KR970005002B1 (ko
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아키히토 하타케야마
히로시 소고
타마오 코지마
야스히코 호리오
마사하데 쯔카모토
야스시 후쿠무라
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모리시타 요이찌
마쯔시다덴기산교 가부시기가이샤
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0116—Porous, e.g. foam
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0263—Details about a collection of particles
    • H05K2201/0269—Non-uniform distribution or concentration of particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0191—Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S428/00—Stock material or miscellaneous articles
    • Y10S428/901—Printed circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/249921—Web or sheet containing structurally defined element or component
    • Y10T428/249953—Composite having voids in a component [e.g., porous, cellular, etc.]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/249921—Web or sheet containing structurally defined element or component
    • Y10T428/249994—Composite having a component wherein a constituent is liquid or is contained within preformed walls [e.g., impregnant-filled, previously void containing component, etc.]
    • Y10T428/249995—Constituent is in liquid form
    • Y10T428/249996—Ink in pores

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

본 발명은, 출발기재에 피압축성의 다공질기재를 사용하고, 임의의 전극층간의 이너비어홀접속을 안정적으로 행하는 것이 가능한 회로 형성용기판의 제조방법 및 그것을 사용한 회로기판 및 다층 회로기판을 제공하는 것을 목적으로한 것으로서, 그 구성에 있어서, 이형성필름(1)을 구비한 피압축성의 다공질기재(2)에 관통구멍(3)을 형성하고, 상기 관통구멍(3)에 도전성페이스트(4)를 충전해서 페이스트속의 바인더 성분을 기재(2)속에 침투기켜서 페이스트속의 바인더에 대한 도전물질의 구성비를 증대시키는 공정과, 이형성필름(1)을 박리한 기재면에 금속박(5)을 붙여서 가열가압하여, 적층기재를 압축하는 공정에 의해서 도전 물질을 치밀화시켜서 금속박간의 전기적 접속을 도모하게한 것을 특징으로한 것이다.

Description

회로형성용기판의 제조방법 및 회로형성용기판 및 이것을 사용한 다층회로기판
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 있어서의 회로형성용 기판의 제조방법을 표시한 공정단면도, 제3도는 본 발명의 제2실시예에 있어서의 회로형성용 기판의 제조방법을 표시한 공정 단면도, 제5도는 다공질기재를 압축하는 프레스압력과 압출률 및 두께의 관계를 표시한 도면, 제8도는 본 발명의 제5실시예에 있어서의 다층회로기판의 제조방법을 표시한 공정단면도.

Claims (22)

  1. 이형성필를을 구비한 피압축성을 가진 다공질기재에 관통구멍을 형성하는 공정과, 상기 관통구멍에 도전성페이스를 충전하는 공정과, 상기 관통구멍에 상기 도전성 페이스트를 충전한 상기 다공질기재로부터 상기 이형성필름을 박리하는 공정과, 상기 다공질기재의 상기 이형성필름을 박리한 면에 금속박을 붙이는 공정과, 상기 금속박을 붙인 상기 다공질기재를 가열가압해서 압축하는 공정을 가진 회로 형성용기판의 제조방법.
  2. 이형성필름을 구비한 피압축성을 가진 다공질기재에 관통구멍을 형성하는 공정과, 상기 관통구멍에 도전성 페이스트를 충전하고, 또한 상기 도전성페이스트속의 바인더에 대한 도전물질의 구성비를 증대시키는 공정과, 상기 관통구멍에 상기 도전성페이스를 충전한 상기 다공기질기재로부터 상기 이형성필름을 박리하는 공정과 상기 다공질기재의 상기 이형성필름을 박리한 면에 금속박을 붙이는 공정과, 상기 금속박을 붙인 상기 다공질기재를 가열가압해서 압축하여, 상기 도전성페이스트속의 도전물질을 치밀화하는 공정을 가진 회로 형성용 기판의 제조방법.
  3. 제1항 또는 제2항에 있어서, 다공질기재를 가열가압해서 압축하는 공정에 있어서, 그 압축율이 10~60%인 것을 특징으로 하는 회로형성용기판의 제조방법.
  4. 제1항 또는 제2항에 있어서, 관통구멍에 도전성페이스트를 충전하는 공정이전에, 이형성필름을 구비한 피압축성을 가진 다공질기재를 예비압축하는 공정을 부가한 것을 특징으로하는 회로 형성용 기판의 제조방법.
  5. 제1항 또는 제2항에 있어서, 이형성필름을 구비한 피압축성을 가진 다공질기재가 유기재로를 주재로로 하고, 상기 다공질기재의 빈구멍율이 10~60%인 것을 특
    징으로 하는 회로 형성용 기판의 제조방법.
  6. 제1항 또는 제2항에 있어서, 이형성필름을 구비한 피압축성을 가진 다공질기재가 방향족 폴리아미드부직포와 열경화성수지와의 복합재인 것을 특징으로 하는 회로형성용기판의 제조방법.
  7. 제1항 또는 제2항에 있어서, 도전성페이스트속의 도전물질이, 은, 금,은팔라듐,구리 및 이들의 합금중의 1종이상으로 이루어진 것을 특징으로 하는 회로형성용기판의 제조방법.
  8. 제1항 또는 제2항에 있어서, 양면에 금속박을 붙인 다공질기재를 가열가압해서 압축하는 공정이, 도전성페이스트의 점도를 상승시키는 제1공정과, 상기 금속박과 상기 다공질기재를 접착하는 제2공정으로 이루어진 것을 특징으로 하는 회로형성용 기판의 제조방법.
  9. 제1항 또는 제2항에 있어서, 도전성페이스트의 겔화온도가 다공질기재를 구성하는 수지의 연화온도보다 낮은 것을 특징으로 하는 회로형성용 기판의 제조방법.
  10. 이형성필름을 구비한 피압축성을 가진 다공질기재에 관통구멍을 형성하는 공정과, 상기 관통구멍에 도전성 페이스트를 충전하는 공정과, 상기 관통구멍에 상기 도전성페이스트를 충전한 상기 다공질기재로부터 상기 이형설필름을 박리하는 공정과, 상기 다공질기재의 상기 이형성필름을 박리한 면에 금속박을 붙이는 공정과, 상기 금속박을 붙인 상기 다공질기재를 가열가압해서 압축하는 이상의 공정에 의해 얻어진 회로 형성용기판의 양면에 회로패턴을 형성하는 회로기판의 제조공정과, 다공질기재에 관통구멍을 형성하고, 상기 관통구멍에 도전성페이스트를 충전하는 중간접속체의 제조공정과, 적어도 1쌍의 상기 회로기판의 사이에 각각 상기 중간접속체를 끼워 유지하여, 가열가압하는 공정을 가진 것을 특징으로 하는 다층회로기판의 제조방법.
  11. 이형성필름을 구비한 피압축성을 가진 다공질기재에 관통구멍을 형성하는 공정과, 상기 관통구멍에 도전성 페이스트를 충전하고, 또한 상기 도전성페이스트속의 바인더에 대한 도전물질의 구성비를 증대시키는 공정과, 상기 관통구멍에 상기 도전성페이스틀 충전한 상기 다공질기재로부터 상기 이형성필름을 박리하는 공정과,상기 다공질기재의 상기 이형성필름을 박리한 면에 금속박을 붙이는 공정과, 상기 금속박을 붙인 상기 다공질기재를 가열가압해서 압축하여, 상기 도전성페이스트속의 도전물질을 치밀화하는 이상의 공정에 의해 얻어진 회로형성용기판의 양면에 회로패턴을 형성하는 회로기판의 제조공정과, 다공질기재에 관통구멍을 형성하고, 상기 관통구멍에 도전성페이스를 충전하는 중간 접속체의 제조공정과, 상기 회로기판의 위에 상기 중간접속체를 붙이고, 그위에 다른 금속박을 붙인 후, 가열가압하는 공정과, 상기 다른 금속박을 가공해서 회로패턴을 형성하는 공정을 가진 것을 특징으로 하는 다층회로기판의 제조방법.
  12. 다공질기재와 상기 다공질개재에 형성된 관통구멍에 충전된 도전성페이스트와, 상기 다공질기재의 양면에 붙인 금속박을 구비하고, 상기 다공질기재의 양면에 붙인 상기 금속박은, 상기 금속박을 붙인 상기 다공질기재를 가열가압해서 압축하므로서 도전성페이스틀 개재해서 전기적으로 접속되어 있는 것을 특징으로하는 회로형 성용기판.
  13. 다공질기재와, 상기 다공질기재에 형성된 관통구멍에 충전되고, 또한 그 페이스트속의 바인더에 대한 도전물질의 구성비가 증대되어서 이루어진 도전성페이스트와, 상기 다공질기재의 양면에 붙인 금속박을 구비하고, 상기 다공질기재의 양면에 붙인 상기 금속박은, 상기 금속박을 붙인 상기 다공질기재를 가열가압해서 압축하므로서 도전성페이스트를 개재해서 전기적으로 접속되어 있는 것을 특징으로하는 회로 형성용기판.
  14. 제12항또는 제13항에 있어서, 다공질기재가, 가열가압에 의해압축율이 10~60%의 범위에서 압축된 것임을 특징으로 하는 회로형성용기판.
  15. 제12항 또는 제13항에 있어서, 다공질기재가, 관통구멍에 도전성페이스트를 충전하는 이전에 예비압축된 것임을 특징으로 하는 회로형성용기판.
  16. 제12항 또는 제13항에 있어서, 다공질기재가 유기재로를 주재로로하고, 상기 다공질기재의 빈구멍율이 10~60%인 것을 특징으로 하는 회로형성용기판.
  17. 제12항 또는 제13항에 있어서, 다공질기재가 방향족 폴리아미드부직포와 열경화성수지와의 복합재인 것을 특징으로하는 회로형성용기판.
  18. 제12항 또는 제13항에 있어서, 도전성페이스트속의 도전물질이 , 은, 금, 은팔라듐, 구리 및 이들의 합금증의 1종이상으로 이루어진 것을 특징으로 하는 회로형성용기판.
  19. 제12항 또는 제13항에 있어서, 다공질기재가, 도전성페이스트의 점도를 상승시키는 제1공정과 금속박과 다공질기재를 접착하는 제2공정에 있어서 가열가압된 것을 특징으로 하는 회로형성용기판.
  20. 제12항 또는 제13항에 있어서, 도전성페이스트이 겔화온도가 다공질기재를 구성하는 수지의 열화온도보다 낮은 것을 특징으로 하는 회로형성용기판.
  21. 청구범위 제12항 또는 제13항 기재의 회로형성용 기판의 양ㅇ면에 회로패턴을 형성해서 이루어진 적어도 1쌍의 회로기판과, 다공질기재에 형성된 관통구멍에 도전성펭스트가 충전되어 있는 중간접속체를 구비하고, 상기회로기판의 사이에 상기 중간접속체을 끼워유지하며, 가열가압하므로서 상기 회로기판의 회로패턴과 대항하는 상기 회로기판의 회로패턴이 중간접속체의 도전성페이스트를 개재해서 전기적으로 접속되어 있는것을 특징으로 하는 다층회로기판.
  22. 청구범위 제12항 또는 제13항 기재의 회로형성용 기판의 양면에 회로패턴을
    형성해서 이루어진 회로기판과, 관통구멍이 형성된 다공질기재에 도전성페이스트가 충전되고, 상기 회로기판의 위에 붙여진 상기 중간접속체와, 중간접속체의 위에 붙여지고, 가열가압해서 압축된 후, 그것에 회로패턴이 형성된 금속박을 구비하고, 상기 회로기판의 회로패턴과 상기 금속박의 회로 패턴이 중간접속체의 도전성 페이스트를 개재해서 전기적으로 접속되어 있는 것을 특징으로 하는 다층회로기판.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930007634A 1992-05-06 1993-05-04 회로형성용기판의 제조방법 및 회로형성용기판 및 이것을 사용한 다층회로기판 KR970005002B1 (ko)

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JP92-113527 1992-05-06
JP11352792 1992-05-06
JP92-127160 1992-05-20
JP12716092 1992-05-20
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JP17801992 1992-07-06
JP326393 1993-01-12
JP93-3263 1993-01-12
JP7784093A JP2601128B2 (ja) 1992-05-06 1993-04-05 回路形成用基板の製造方法および回路形成用基板
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EP0568930B1 (en) 1998-03-04
CN1056490C (zh) 2000-09-13
JPH06268345A (ja) 1994-09-22
JP2601128B2 (ja) 1997-04-16
CN1092240A (zh) 1994-09-14
EP0568930A3 (ko) 1994-04-06
KR970005002B1 (ko) 1997-04-10
CN1203731C (zh) 2005-05-25
US5481795A (en) 1996-01-09

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