FR2296988A1 - Perfectionnement aux procedes de fabrication d'un module de circuits multicouches en ceramique - Google Patents

Perfectionnement aux procedes de fabrication d'un module de circuits multicouches en ceramique

Info

Publication number
FR2296988A1
FR2296988A1 FR7443622A FR7443622A FR2296988A1 FR 2296988 A1 FR2296988 A1 FR 2296988A1 FR 7443622 A FR7443622 A FR 7443622A FR 7443622 A FR7443622 A FR 7443622A FR 2296988 A1 FR2296988 A1 FR 2296988A1
Authority
FR
France
Prior art keywords
improvement
circuit module
manufacturing processes
multilayer circuit
ceramic multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7443622A
Other languages
English (en)
Other versions
FR2296988B1 (fr
Inventor
Jean-Marie Lemoine
Jean-Luc Mathis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compagnie IBM France SAS
Original Assignee
Compagnie IBM France SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compagnie IBM France SAS filed Critical Compagnie IBM France SAS
Priority to FR7443622A priority Critical patent/FR2296988A1/fr
Priority to GB42144/75A priority patent/GB1487800A/en
Priority to IT28856/75A priority patent/IT1049009B/it
Priority to JP13829875A priority patent/JPS5437294B2/ja
Priority to US05/635,567 priority patent/US4024629A/en
Priority to CA240,572A priority patent/CA1043189A/fr
Priority to DE2558361A priority patent/DE2558361C2/de
Publication of FR2296988A1 publication Critical patent/FR2296988A1/fr
Application granted granted Critical
Publication of FR2296988B1 publication Critical patent/FR2296988B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B61—RAILWAYS
    • B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
    • B61L25/00—Recording or indicating positions or identities of vehicles or vehicle trains or setting of track apparatus
    • B61L25/02—Indicating or recording positions or identities of vehicles or vehicle trains
    • B61L25/04—Indicating or recording train identities
    • B61L25/045—Indicating or recording train identities using reradiating tags
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09981—Metallised walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0156—Temporary polymeric carrier or foil, e.g. for processing or transferring
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0191—Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
FR7443622A 1974-12-31 1974-12-31 Perfectionnement aux procedes de fabrication d'un module de circuits multicouches en ceramique Granted FR2296988A1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR7443622A FR2296988A1 (fr) 1974-12-31 1974-12-31 Perfectionnement aux procedes de fabrication d'un module de circuits multicouches en ceramique
GB42144/75A GB1487800A (en) 1974-12-31 1975-10-15 Plated through-holes for printed circuits
IT28856/75A IT1049009B (it) 1974-12-31 1975-10-31 Procedimento perfezionato per la fabbricazione di moduli circuitali ceramici a piu strati
JP13829875A JPS5437294B2 (fr) 1974-12-31 1975-11-19
US05/635,567 US4024629A (en) 1974-12-31 1975-11-26 Fabrication techniques for multilayer ceramic modules
CA240,572A CA1043189A (fr) 1974-12-31 1975-11-26 Techniques de fabrication de modules ceramiques multicouches
DE2558361A DE2558361C2 (de) 1974-12-31 1975-12-23 Verfahren zum Herstellen von durchgehend metallisierten Bohrungen in mehrschichtigen keramischen Moduln

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7443622A FR2296988A1 (fr) 1974-12-31 1974-12-31 Perfectionnement aux procedes de fabrication d'un module de circuits multicouches en ceramique

Publications (2)

Publication Number Publication Date
FR2296988A1 true FR2296988A1 (fr) 1976-07-30
FR2296988B1 FR2296988B1 (fr) 1977-07-08

Family

ID=9146935

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7443622A Granted FR2296988A1 (fr) 1974-12-31 1974-12-31 Perfectionnement aux procedes de fabrication d'un module de circuits multicouches en ceramique

Country Status (7)

Country Link
US (1) US4024629A (fr)
JP (1) JPS5437294B2 (fr)
CA (1) CA1043189A (fr)
DE (1) DE2558361C2 (fr)
FR (1) FR2296988A1 (fr)
GB (1) GB1487800A (fr)
IT (1) IT1049009B (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1983003040A1 (fr) * 1982-02-26 1983-09-01 Serras Paulet Edouard Circuit electrique imprime
EP0374286A1 (fr) * 1987-06-22 1990-06-27 The Furukawa Electric Co., Ltd. Procédé de fabrication d'une plaque à circuit imprimé à deux couches
EP0396806A1 (fr) * 1989-05-12 1990-11-14 Ibm Deutschland Gmbh Structure vitrocéramique et méthode pour la fabriquer
EP0568930A2 (fr) * 1992-05-06 1993-11-10 Matsushita Electric Industrial Co., Ltd. Procédé de fabrication d'un substrat organique pour des circuits imprimés

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JPS5328266A (en) * 1976-08-13 1978-03-16 Fujitsu Ltd Method of producing multilayer ceramic substrate
US4181387A (en) * 1978-06-21 1980-01-01 Western Electric Company, Inc. Interconnect sockets and assemblies
US4327247A (en) * 1978-10-02 1982-04-27 Shin-Kobe Electric Machinery Co., Ltd. Printed wiring board
US4191789A (en) * 1978-11-02 1980-03-04 Bell Telephone Laboratories, Incorporated Fabrication of bi-level circuits
JPS55138294A (en) * 1979-04-11 1980-10-28 Matsushita Electric Ind Co Ltd Method of forming through hole connector
US4247981A (en) * 1979-06-18 1981-02-03 Western Electric Company, Inc. Methods of assembling interconnect members with printed circuit boards
US4383495A (en) * 1980-06-02 1983-05-17 Western Electric Company, Inc. Apparatus for coating surfaces of a substrate
US4301192A (en) * 1980-06-02 1981-11-17 Western Electric Co., Inc. Method for coating thru holes in a printed circuit substrate
US4369557A (en) * 1980-08-06 1983-01-25 Jan Vandebult Process for fabricating resonant tag circuit constructions
US4434134A (en) * 1981-04-10 1984-02-28 International Business Machines Corporation Pinned ceramic substrate
DE3214097A1 (de) * 1982-04-16 1983-10-20 ITALTEL Società Italiana Telecomunicazioni S.p.A., 20149 Milano Verfahren, mit dem durchgehende loecher in elektrischen schaltungstraegern leitfaehig gemacht werden
JPS5923548A (ja) * 1982-07-30 1984-02-07 Fujitsu Ltd 半導体装置
DE3245458A1 (de) * 1982-12-08 1984-06-14 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung von durchkontaktierungen in dickschichttechnik
JPS6047495A (ja) * 1983-08-25 1985-03-14 株式会社日立製作所 セラミツク配線基板
JPS6084711A (ja) * 1983-10-14 1985-05-14 株式会社日立製作所 スル−ホ−ル充填用ペ−スト
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JPH0714105B2 (ja) * 1986-05-19 1995-02-15 日本電装株式会社 混成集積回路基板及びその製造方法
US4919970A (en) * 1986-09-15 1990-04-24 International Business Machines Corporation Solder deposition control
US4802741A (en) * 1987-10-09 1989-02-07 Eastman Kodak Company In-depth electrode light valve array devices and improved fabrication method therefor
US4785989A (en) * 1987-11-16 1988-11-22 Gte Products Corporation Clad system for brazing to alumina
US5089881A (en) * 1988-11-03 1992-02-18 Micro Substrates, Inc. Fine-pitch chip carrier
JPH02152105A (ja) * 1988-12-01 1990-06-12 Fujitsu Ltd 導電材料およびその製造方法
US4954313A (en) * 1989-02-03 1990-09-04 Amdahl Corporation Method and apparatus for filling high density vias
US4985601A (en) * 1989-05-02 1991-01-15 Hagner George R Circuit boards with recessed traces
JPH0480991A (ja) * 1990-07-24 1992-03-13 Cmk Corp プリント配線板の製造方法
US5283104A (en) * 1991-03-20 1994-02-01 International Business Machines Corporation Via paste compositions and use thereof to form conductive vias in circuitized ceramic substrates
AT398876B (de) * 1991-10-31 1995-02-27 Philips Nv Zwei- oder mehrlagige leiterplatte
US5282312A (en) * 1991-12-31 1994-02-01 Tessera, Inc. Multi-layer circuit construction methods with customization features
US5367764A (en) * 1991-12-31 1994-11-29 Tessera, Inc. Method of making a multi-layer circuit assembly
US5766670A (en) * 1993-11-17 1998-06-16 Ibm Via fill compositions for direct attach of devices and methods for applying same
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US5834824A (en) * 1994-02-08 1998-11-10 Prolinx Labs Corporation Use of conductive particles in a nonconductive body as an integrated circuit antifuse
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US5746874A (en) * 1995-09-29 1998-05-05 International Business Machines Corporation Apparatus and method for forming cavity substrates using flexible preform insert
US5906042A (en) * 1995-10-04 1999-05-25 Prolinx Labs Corporation Method and structure to interconnect traces of two conductive layers in a printed circuit board
US5872338A (en) * 1996-04-10 1999-02-16 Prolinx Labs Corporation Multilayer board having insulating isolation rings
US5915756A (en) * 1996-08-22 1999-06-29 Altera Corporation Method to fill via holes between two conductive layers
US6622603B1 (en) * 1997-03-12 2003-09-23 International Business Machines Corporation Linear via punch
US6288344B1 (en) 1999-08-20 2001-09-11 Cardiac Pacemakers, Inc. Integrated EMI shield utilizing a hybrid edge
US6352014B1 (en) * 1999-12-15 2002-03-05 International Business Machines Corporation Method for making punches using multi-layer ceramic technology
US6833615B2 (en) * 2000-12-29 2004-12-21 Intel Corporation Via-in-pad with off-center geometry
US6762380B2 (en) * 2001-06-29 2004-07-13 Icorp Membrane switch circuit layout and method for manufacturing
US7024763B2 (en) 2003-11-26 2006-04-11 Formfactor, Inc. Methods for making plated through holes usable as interconnection wire or probe attachments
US20050108875A1 (en) * 2003-11-26 2005-05-26 Mathieu Gaetan L. Methods for making vertical electric feed through structures usable to form removable substrate tiles in a wafer test system
KR20100071968A (ko) * 2007-08-31 2010-06-29 리엑티브 나노테크놀로지스, 인크. 전자 부품의 저온 접합을 위한 방법
KR20110049247A (ko) * 2009-11-04 2011-05-12 삼성전기주식회사 인쇄회로기판 및 그 제조방법
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DE1188157B (de) * 1961-04-21 1965-03-04 Litton Industries Inc Verfahren zur Herstellung einer geschichteten, gedruckten Schaltungsplatte

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REVUE US: "IBM TECHNICAL DISCLOSURE BULLETIN", VOL. 15, NO. 10, MARS 1973, "MULTILAYER CERAMIC GREEN SHEET CHANNEL FORMATION" A. JURAS ET AL.) *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1983003040A1 (fr) * 1982-02-26 1983-09-01 Serras Paulet Edouard Circuit electrique imprime
EP0374286A1 (fr) * 1987-06-22 1990-06-27 The Furukawa Electric Co., Ltd. Procédé de fabrication d'une plaque à circuit imprimé à deux couches
EP0396806A1 (fr) * 1989-05-12 1990-11-14 Ibm Deutschland Gmbh Structure vitrocéramique et méthode pour la fabriquer
EP0568930A2 (fr) * 1992-05-06 1993-11-10 Matsushita Electric Industrial Co., Ltd. Procédé de fabrication d'un substrat organique pour des circuits imprimés
EP0568930A3 (fr) * 1992-05-06 1994-04-06 Matsushita Electric Ind Co Ltd
US5346750A (en) * 1992-05-06 1994-09-13 Matsushita Electric Industrial Co., Ltd. Porous substrate and conductive ink filled vias for printed circuits

Also Published As

Publication number Publication date
CA1043189A (fr) 1978-11-28
GB1487800A (en) 1977-10-05
JPS5180965A (fr) 1976-07-15
DE2558361C2 (de) 1982-04-08
DE2558361A1 (de) 1976-07-08
FR2296988B1 (fr) 1977-07-08
US4024629A (en) 1977-05-24
IT1049009B (it) 1981-01-20
JPS5437294B2 (fr) 1979-11-14

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