JP7169072B2 - 選択的パッシベーションおよび選択的堆積 - Google Patents

選択的パッシベーションおよび選択的堆積 Download PDF

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JP7169072B2
JP7169072B2 JP2018022563A JP2018022563A JP7169072B2 JP 7169072 B2 JP7169072 B2 JP 7169072B2 JP 2018022563 A JP2018022563 A JP 2018022563A JP 2018022563 A JP2018022563 A JP 2018022563A JP 7169072 B2 JP7169072 B2 JP 7169072B2
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layer
passivation layer
selectively
passivation
deposition
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JP2018137435A (ja
JP2018137435A5 (enExample
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エヴァ イー． トイス
スヴィ ピー． ハウッカ
ライヤ エイチ． マテロ
エリナ ファーム
デルフィン ロングリエ
ヒデミ スエモリ
ヤン ヴィレム マエス
マルコ トゥオミネン
シャオレン デン
イヴォ ヨハネス ラーイマケルス
アンドレア イリベリ
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エーエスエム アイピー ホールディング ビー．ブイ．
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Publication of JP2018137435A publication Critical patent/JP2018137435A/ja
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Priority to JP2022172419A priority Critical patent/JP7373636B2/ja
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Priority to JP2023179722A priority patent/JP2023182796A/ja
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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