JP3619773B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP3619773B2 JP3619773B2 JP2000387825A JP2000387825A JP3619773B2 JP 3619773 B2 JP3619773 B2 JP 3619773B2 JP 2000387825 A JP2000387825 A JP 2000387825A JP 2000387825 A JP2000387825 A JP 2000387825A JP 3619773 B2 JP3619773 B2 JP 3619773B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- mold
- manufacturing
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1433—Application-specific integrated circuit [ASIC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/207—Diameter ranges
- H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Injection Moulding Of Plastics Or The Like (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Priority Applications (9)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000387825A JP3619773B2 (ja) | 2000-12-20 | 2000-12-20 | 半導体装置の製造方法 |
| SG200107100A SG92821A1 (en) | 2000-12-20 | 2001-11-13 | A method of manufacturing a semiconductor device and a semiconductor device |
| US09/987,532 US6596561B2 (en) | 2000-12-20 | 2001-11-15 | Method of manufacturing a semiconductor device using reinforcing patterns for ensuring mechanical strength during manufacture |
| TW090128724A TW526598B (en) | 2000-12-20 | 2001-11-20 | Manufacturing method of semiconductor device and semiconductor device |
| KR1020010081051A KR100551641B1 (ko) | 2000-12-20 | 2001-12-19 | 반도체 장치의 제조 방법 및 반도체 장치 |
| CNB011338032A CN1230882C (zh) | 2000-12-20 | 2001-12-20 | 一种半导体器件的制造方法和一种半导体器件 |
| US10/453,606 US6723583B2 (en) | 2000-12-20 | 2003-06-04 | Method of manufacturing a semiconductor device using a mold |
| US10/784,276 US6872597B2 (en) | 2000-12-20 | 2004-02-24 | Method of manufacturing a semiconductor device and a semiconductor device |
| US11/047,660 US7015069B2 (en) | 2000-12-20 | 2005-02-02 | Method of manufacturing a semiconductor device and a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000387825A JP3619773B2 (ja) | 2000-12-20 | 2000-12-20 | 半導体装置の製造方法 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004069427A Division JP2004172647A (ja) | 2004-03-11 | 2004-03-11 | 半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2002190488A JP2002190488A (ja) | 2002-07-05 |
| JP3619773B2 true JP3619773B2 (ja) | 2005-02-16 |
| JP2002190488A5 JP2002190488A5 (enExample) | 2005-02-17 |
Family
ID=18854673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000387825A Expired - Lifetime JP3619773B2 (ja) | 2000-12-20 | 2000-12-20 | 半導体装置の製造方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (4) | US6596561B2 (enExample) |
| JP (1) | JP3619773B2 (enExample) |
| KR (1) | KR100551641B1 (enExample) |
| CN (1) | CN1230882C (enExample) |
| SG (1) | SG92821A1 (enExample) |
| TW (1) | TW526598B (enExample) |
Families Citing this family (92)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1154658A (ja) * | 1997-07-30 | 1999-02-26 | Hitachi Ltd | 半導体装置及びその製造方法並びにフレーム構造体 |
| KR100556240B1 (ko) * | 1998-07-28 | 2006-03-03 | 세이코 엡슨 가부시키가이샤 | 반도체 장치 제조방법 |
| JP4586316B2 (ja) * | 2001-08-21 | 2010-11-24 | 日本テキサス・インスツルメンツ株式会社 | 半導体チップ搭載用基板及びそれを用いた半導体装置 |
| JP3892703B2 (ja) * | 2001-10-19 | 2007-03-14 | 富士通株式会社 | 半導体基板用治具及びこれを用いた半導体装置の製造方法 |
| AU2003234812A1 (en) | 2002-06-05 | 2003-12-22 | Hitachi Ulsi Systems Co., Ltd. | Semiconductor device |
| JP3812500B2 (ja) * | 2002-06-20 | 2006-08-23 | セイコーエプソン株式会社 | 半導体装置とその製造方法、電気光学装置、電子機器 |
| JP2004055860A (ja) * | 2002-07-22 | 2004-02-19 | Renesas Technology Corp | 半導体装置の製造方法 |
| AU2003255956A1 (en) * | 2002-08-05 | 2004-02-25 | Koninklijke Philips Electronics N.V. | Method and apparatus for manufacturing a packaged semiconductor device, packaged semiconductor device obtained with such a method and metal carrier suitable for use in such a method |
| US7064426B2 (en) * | 2002-09-17 | 2006-06-20 | Chippac, Inc. | Semiconductor multi-package module having wire bond interconnect between stacked packages |
| US20040061213A1 (en) * | 2002-09-17 | 2004-04-01 | Chippac, Inc. | Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages |
| US7049691B2 (en) * | 2002-10-08 | 2006-05-23 | Chippac, Inc. | Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package |
| US7034387B2 (en) * | 2003-04-04 | 2006-04-25 | Chippac, Inc. | Semiconductor multipackage module including processor and memory package assemblies |
| JP4519398B2 (ja) * | 2002-11-26 | 2010-08-04 | Towa株式会社 | 樹脂封止方法及び半導体装置の製造方法 |
| JP4607429B2 (ja) | 2003-03-25 | 2011-01-05 | 東レ・ダウコーニング株式会社 | 半導体装置の製造方法および半導体装置 |
| JP4796271B2 (ja) * | 2003-07-10 | 2011-10-19 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US20050047106A1 (en) * | 2003-08-29 | 2005-03-03 | Martino Peter Miguel | Substrate reinforcing in an LGA package |
| TWI222186B (en) * | 2003-09-04 | 2004-10-11 | Advanced Semiconductor Eng | Method for manufacturing package substrate strip and structure from the same |
| JP2005116762A (ja) * | 2003-10-07 | 2005-04-28 | Fujitsu Ltd | 半導体装置の保護方法及び半導体装置用カバー及び半導体装置ユニット及び半導体装置の梱包構造 |
| JP2005150350A (ja) * | 2003-11-14 | 2005-06-09 | Renesas Technology Corp | 半導体装置の製造方法 |
| JP4488733B2 (ja) * | 2003-12-24 | 2010-06-23 | 三洋電機株式会社 | 回路基板の製造方法および混成集積回路装置の製造方法。 |
| JP2006073586A (ja) * | 2004-08-31 | 2006-03-16 | Renesas Technology Corp | 半導体装置の製造方法 |
| US7791180B2 (en) * | 2004-10-01 | 2010-09-07 | Yamaha Corporation | Physical quantity sensor and lead frame used for same |
| US7595548B2 (en) * | 2004-10-08 | 2009-09-29 | Yamaha Corporation | Physical quantity sensor and manufacturing method therefor |
| CN100416807C (zh) * | 2004-10-20 | 2008-09-03 | 力晶半导体股份有限公司 | 半导体封装结构及其制造方法 |
| JP2006190771A (ja) | 2005-01-05 | 2006-07-20 | Renesas Technology Corp | 半導体装置 |
| DE102005002862A1 (de) * | 2005-01-20 | 2006-07-27 | Infineon Technologies Ag | Vefahren zur Herstellung eines FBGA-Bauelementes und Substrat zur Durchführung des Verfahrens |
| TWI283050B (en) * | 2005-02-04 | 2007-06-21 | Phoenix Prec Technology Corp | Substrate structure embedded method with semiconductor chip and the method for making the same |
| JP2006269486A (ja) * | 2005-03-22 | 2006-10-05 | Renesas Technology Corp | 半導体装置の製造方法 |
| US8461675B2 (en) * | 2005-12-13 | 2013-06-11 | Sandisk Technologies Inc. | Substrate panel with plating bar structured to allow minimum kerf width |
| JP4741383B2 (ja) * | 2006-02-17 | 2011-08-03 | 富士通セミコンダクター株式会社 | 電子部品の樹脂封止方法 |
| US20070269929A1 (en) * | 2006-05-17 | 2007-11-22 | Chih-Chin Liao | Method of reducing stress on a semiconductor die with a distributed plating pattern |
| WO2007136651A2 (en) * | 2006-05-17 | 2007-11-29 | Sandisk Corporation | Semiconductor device with a distributed plating pattern |
| US20070267759A1 (en) * | 2006-05-17 | 2007-11-22 | Chih-Chin Liao | Semiconductor device with a distributed plating pattern |
| JP2007335581A (ja) * | 2006-06-14 | 2007-12-27 | Renesas Technology Corp | 半導体装置の製造方法 |
| JP2008004855A (ja) * | 2006-06-26 | 2008-01-10 | Nitto Denko Corp | Tab用テープキャリア |
| JP2008016630A (ja) * | 2006-07-06 | 2008-01-24 | Matsushita Electric Ind Co Ltd | プリント配線板およびその製造方法 |
| JP5117692B2 (ja) * | 2006-07-14 | 2013-01-16 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP2008047573A (ja) * | 2006-08-11 | 2008-02-28 | Matsushita Electric Ind Co Ltd | 樹脂封止型半導体装置の製造装置、樹脂封止型半導体装置の製造方法、および樹脂封止型半導体装置 |
| US20080036078A1 (en) * | 2006-08-14 | 2008-02-14 | Ciclon Semiconductor Device Corp. | Wirebond-less semiconductor package |
| JP5037071B2 (ja) * | 2006-08-29 | 2012-09-26 | 新光電気工業株式会社 | 樹脂封止型半導体装置の製造方法 |
| US7616451B2 (en) * | 2006-10-13 | 2009-11-10 | Stmicroelectronics S.R.L. | Semiconductor package substrate and method, in particular for MEMS devices |
| DE102006058010B9 (de) * | 2006-12-08 | 2009-06-10 | Infineon Technologies Ag | Halbleiterbauelement mit Hohlraumstruktur und Herstellungsverfahren |
| DE102006062473A1 (de) * | 2006-12-28 | 2008-07-03 | Qimonda Ag | Halbleiterbauelement mit auf einem Substrat montiertem Chip |
| KR100849792B1 (ko) * | 2007-04-23 | 2008-07-31 | 삼성전기주식회사 | 칩 부품의 제조방법 |
| US8637972B2 (en) * | 2007-06-08 | 2014-01-28 | Sandisk Technologies Inc. | Two-sided substrate lead connection for minimizing kerf width on a semiconductor substrate panel |
| KR100878194B1 (ko) * | 2007-07-20 | 2009-01-13 | 세크론 주식회사 | 반도체 몰딩 장치 |
| JP4659802B2 (ja) * | 2007-09-25 | 2011-03-30 | シャープ株式会社 | 絶縁性配線基板、これを用いた半導体パッケージ、および絶縁性配線基板の製造方法 |
| KR100876899B1 (ko) * | 2007-10-10 | 2009-01-07 | 주식회사 하이닉스반도체 | 반도체 패키지 |
| US9117714B2 (en) * | 2007-10-19 | 2015-08-25 | Visera Technologies Company Limited | Wafer level package and mask for fabricating the same |
| KR100931295B1 (ko) * | 2008-01-24 | 2009-12-11 | 세크론 주식회사 | 전자 부품 몰딩 장치 및 전자 부품 몰딩 방법 |
| JP2009206429A (ja) * | 2008-02-29 | 2009-09-10 | Toshiba Corp | 記憶媒体 |
| US20090224412A1 (en) * | 2008-03-04 | 2009-09-10 | Powertech Technology Corporation | Non-planar substrate strip and semiconductor packaging method utilizing the substrate strip |
| US8217514B2 (en) * | 2008-04-07 | 2012-07-10 | Stats Chippac Ltd. | Integrated circuit packaging system with warpage control system and method of manufacture thereof |
| JP5203045B2 (ja) * | 2008-05-28 | 2013-06-05 | 日本特殊陶業株式会社 | 多層配線基板の中間製品、多層配線基板の製造方法 |
| KR100882108B1 (ko) * | 2008-06-02 | 2009-02-06 | 삼성전기주식회사 | 칩 부품의 제조방법 |
| CN101621894B (zh) * | 2008-07-04 | 2011-12-21 | 富葵精密组件(深圳)有限公司 | 电路板组装方法及电路板预制品 |
| JP2010021275A (ja) * | 2008-07-09 | 2010-01-28 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
| JP2010093109A (ja) * | 2008-10-09 | 2010-04-22 | Renesas Technology Corp | 半導体装置、半導体装置の製造方法および半導体モジュールの製造方法 |
| US8568961B2 (en) * | 2008-11-25 | 2013-10-29 | Lord Corporation | Methods for protecting a die surface with photocurable materials |
| US9093448B2 (en) | 2008-11-25 | 2015-07-28 | Lord Corporation | Methods for protecting a die surface with photocurable materials |
| US7851266B2 (en) * | 2008-11-26 | 2010-12-14 | Micron Technologies, Inc. | Microelectronic device wafers including an in-situ molded adhesive, molds for in-situ molding adhesives on microelectronic device wafers, and methods of molding adhesives on microelectronic device wafers |
| JP2010135418A (ja) * | 2008-12-02 | 2010-06-17 | Shinko Electric Ind Co Ltd | 配線基板及び電子部品装置 |
| TWI384603B (zh) | 2009-02-17 | 2013-02-01 | Advanced Semiconductor Eng | 基板結構及應用其之封裝結構 |
| JP5985136B2 (ja) | 2009-03-19 | 2016-09-06 | ソニー株式会社 | 半導体装置とその製造方法、及び電子機器 |
| FR2943849B1 (fr) * | 2009-03-31 | 2011-08-26 | St Microelectronics Grenoble 2 | Procede de realisation de boitiers semi-conducteurs et boitier semi-conducteur |
| JP5119484B2 (ja) * | 2009-06-18 | 2013-01-16 | 三洋電機株式会社 | 実装基板およびそれを用いた半導体装置 |
| KR101037450B1 (ko) * | 2009-09-23 | 2011-05-26 | 삼성전기주식회사 | 패키지 기판 |
| KR101101669B1 (ko) * | 2009-12-01 | 2011-12-30 | 삼성전기주식회사 | 전자부품 제조장치 및 전자부품 제조방법 |
| EP2330618A1 (en) * | 2009-12-04 | 2011-06-08 | STMicroelectronics (Grenoble 2) SAS | Rebuilt wafer assembly |
| JP5503466B2 (ja) * | 2010-08-31 | 2014-05-28 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP5666211B2 (ja) * | 2010-09-01 | 2015-02-12 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 配線基板及び半導体装置の製造方法 |
| US8456021B2 (en) * | 2010-11-24 | 2013-06-04 | Texas Instruments Incorporated | Integrated circuit device having die bonded to the polymer side of a polymer substrate |
| US8759153B2 (en) * | 2011-09-06 | 2014-06-24 | Infineon Technologies Ag | Method for making a sensor device using a graphene layer |
| US8373269B1 (en) * | 2011-09-08 | 2013-02-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Jigs with controlled spacing for bonding dies onto package substrates |
| JP5885332B2 (ja) | 2011-10-20 | 2016-03-15 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| KR20130071792A (ko) * | 2011-12-21 | 2013-07-01 | 삼성전자주식회사 | Muf용 pcb 및 그 pcb 몰딩 구조 |
| KR101922191B1 (ko) * | 2012-03-02 | 2019-02-20 | 엘지이노텍 주식회사 | 인쇄회로기판 및 그의 제조 방법 |
| JP6217101B2 (ja) * | 2013-03-22 | 2017-10-25 | 富士電機株式会社 | 半導体装置の製造方法及び取り付け治具 |
| US10405434B2 (en) | 2013-03-22 | 2019-09-03 | Fuji Electric Co., Ltd. | Mounting jig for semiconductor device |
| US9082885B2 (en) | 2013-05-30 | 2015-07-14 | Samsung Electronics Co., Ltd. | Semiconductor chip bonding apparatus and method of forming semiconductor device using the same |
| JP6044473B2 (ja) * | 2013-06-28 | 2016-12-14 | 株式会社デンソー | 電子装置およびその電子装置の製造方法 |
| US9449943B2 (en) * | 2013-10-29 | 2016-09-20 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of balancing surfaces of an embedded PCB unit with a dummy copper pattern |
| KR20150062556A (ko) * | 2013-11-29 | 2015-06-08 | 삼성전기주식회사 | 휨방지 부재가 구비된 스트립 레벨 기판 및 이의 제조 방법 |
| US9397051B2 (en) | 2013-12-03 | 2016-07-19 | Invensas Corporation | Warpage reduction in structures with electrical circuitry |
| JP6194804B2 (ja) * | 2014-01-23 | 2017-09-13 | 株式会社デンソー | モールドパッケージ |
| KR102214512B1 (ko) * | 2014-07-04 | 2021-02-09 | 삼성전자 주식회사 | 인쇄회로기판 및 이를 이용한 반도체 패키지 |
| US9711552B2 (en) | 2014-08-19 | 2017-07-18 | Heptagon Micro Optics Pte. Ltd. | Optoelectronic modules having a silicon substrate, and fabrication methods for such modules |
| US10043769B2 (en) * | 2015-06-03 | 2018-08-07 | Micron Technology, Inc. | Semiconductor devices including dummy chips |
| US20180166356A1 (en) * | 2016-12-13 | 2018-06-14 | Globalfoundries Inc. | Fan-out circuit packaging with integrated lid |
| CN108738366B (zh) * | 2017-02-20 | 2022-03-15 | 新电元工业株式会社 | 电子装置 |
| KR102696423B1 (ko) * | 2019-08-14 | 2024-08-20 | 삼성전자주식회사 | 반도체 장치 |
| US11469149B2 (en) * | 2019-11-15 | 2022-10-11 | Semtech Corporation | Semiconductor device and method of forming mold degating structure for pre-molded substrate |
Family Cites Families (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW344109B (en) * | 1994-02-10 | 1998-11-01 | Hitachi Ltd | Methods of making semiconductor devices |
| JP2531382B2 (ja) | 1994-05-26 | 1996-09-04 | 日本電気株式会社 | ボ―ルグリッドアレイ半導体装置およびその製造方法 |
| JP3066251B2 (ja) * | 1994-08-05 | 2000-07-17 | シャープ株式会社 | プリント配線基板 |
| JP3214788B2 (ja) * | 1994-11-21 | 2001-10-02 | アピックヤマダ株式会社 | 樹脂モールド装置および樹脂モールド方法 |
| JP2666788B2 (ja) * | 1995-10-19 | 1997-10-22 | 日本電気株式会社 | チップサイズ半導体装置の製造方法 |
| MY118036A (en) * | 1996-01-22 | 2004-08-30 | Lintec Corp | Wafer dicing/bonding sheet and process for producing semiconductor device |
| CN100428449C (zh) * | 1996-07-12 | 2008-10-22 | 富士通株式会社 | 半导体装置 |
| US5776798A (en) | 1996-09-04 | 1998-07-07 | Motorola, Inc. | Semiconductor package and method thereof |
| JPH10244556A (ja) | 1997-03-06 | 1998-09-14 | Sony Corp | 半導体パッケージの製造方法 |
| JPH10256286A (ja) | 1997-03-07 | 1998-09-25 | Nkk Corp | 半導体装置の製造方法 |
| JP2971834B2 (ja) | 1997-06-27 | 1999-11-08 | 松下電子工業株式会社 | 樹脂封止型半導体装置の製造方法 |
| US5904502A (en) * | 1997-09-04 | 1999-05-18 | International Business Machines Corporation | Multiple 3-dimensional semiconductor device processing method and apparatus |
| JP3601985B2 (ja) * | 1998-10-30 | 2004-12-15 | 富士通株式会社 | 半導体パッケージの製造方法 |
| US6448650B1 (en) * | 1998-05-18 | 2002-09-10 | Texas Instruments Incorporated | Fine pitch system and method for reinforcing bond pads in semiconductor devices |
| JP2000156435A (ja) * | 1998-06-22 | 2000-06-06 | Fujitsu Ltd | 半導体装置及びその製造方法 |
| JP3127889B2 (ja) | 1998-06-25 | 2001-01-29 | 日本電気株式会社 | 半導体パッケージの製造方法およびその成形用金型 |
| EP0971401B1 (en) * | 1998-07-10 | 2010-06-09 | Apic Yamada Corporation | Method of manufacturing semiconductor devices and a resin molding machine therefor |
| US6479887B1 (en) * | 1998-08-31 | 2002-11-12 | Amkor Technology, Inc. | Circuit pattern tape for wafer-scale production of chip size semiconductor packages |
| JP4234244B2 (ja) * | 1998-12-28 | 2009-03-04 | 富士通マイクロエレクトロニクス株式会社 | ウエハーレベルパッケージ及びウエハーレベルパッケージを用いた半導体装置の製造方法 |
| JP2000223608A (ja) * | 1999-01-29 | 2000-08-11 | Nec Corp | 半導体パッケージ及びその製造方法 |
| JP2000228566A (ja) * | 1999-02-04 | 2000-08-15 | Matsushita Electric Ind Co Ltd | 集合プリント配線板 |
| SG92685A1 (en) * | 1999-03-10 | 2002-11-19 | Towa Corp | Method of coating semiconductor wafer with resin and mold used therefor |
| JP3494586B2 (ja) * | 1999-03-26 | 2004-02-09 | アピックヤマダ株式会社 | 樹脂封止装置及び樹脂封止方法 |
| US6245595B1 (en) * | 1999-07-22 | 2001-06-12 | National Semiconductor Corporation | Techniques for wafer level molding of underfill encapsulant |
| JP2001135658A (ja) * | 1999-11-08 | 2001-05-18 | Towa Corp | 電子部品の組立方法及び組立装置 |
| US6329220B1 (en) * | 1999-11-23 | 2001-12-11 | Micron Technology, Inc. | Packages for semiconductor die |
| JP3738176B2 (ja) * | 2000-08-03 | 2006-01-25 | 三洋電機株式会社 | 半導体装置の製造方法 |
-
2000
- 2000-12-20 JP JP2000387825A patent/JP3619773B2/ja not_active Expired - Lifetime
-
2001
- 2001-11-13 SG SG200107100A patent/SG92821A1/en unknown
- 2001-11-15 US US09/987,532 patent/US6596561B2/en not_active Expired - Lifetime
- 2001-11-20 TW TW090128724A patent/TW526598B/zh not_active IP Right Cessation
- 2001-12-19 KR KR1020010081051A patent/KR100551641B1/ko not_active Expired - Lifetime
- 2001-12-20 CN CNB011338032A patent/CN1230882C/zh not_active Expired - Lifetime
-
2003
- 2003-06-04 US US10/453,606 patent/US6723583B2/en not_active Expired - Lifetime
-
2004
- 2004-02-24 US US10/784,276 patent/US6872597B2/en not_active Expired - Lifetime
-
2005
- 2005-02-02 US US11/047,660 patent/US7015069B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US20030205797A1 (en) | 2003-11-06 |
| US20020074650A1 (en) | 2002-06-20 |
| US6723583B2 (en) | 2004-04-20 |
| US6596561B2 (en) | 2003-07-22 |
| CN1230882C (zh) | 2005-12-07 |
| TW526598B (en) | 2003-04-01 |
| US20050127535A1 (en) | 2005-06-16 |
| KR100551641B1 (ko) | 2006-02-14 |
| JP2002190488A (ja) | 2002-07-05 |
| CN1360344A (zh) | 2002-07-24 |
| US6872597B2 (en) | 2005-03-29 |
| US20040164428A1 (en) | 2004-08-26 |
| KR20020050148A (ko) | 2002-06-26 |
| SG92821A1 (en) | 2002-11-19 |
| US7015069B2 (en) | 2006-03-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3619773B2 (ja) | 半導体装置の製造方法 | |
| US6537856B2 (en) | Method of attaching a semiconductor chip to a leadframe with a footprint of about the same size as the chip and packages formed thereby | |
| US6638790B2 (en) | Leadframe and method for manufacturing resin-molded semiconductor device | |
| CN101252096B (zh) | 芯片封装结构以及其制作方法 | |
| US20020041019A1 (en) | Semiconductor package having implantable conductive lands and method for manufacturing the same | |
| JP2006516812A (ja) | 部分的にパターン形成されたリードフレームならびに半導体パッケージングにおけるその製造および使用方法 | |
| JP3497744B2 (ja) | 樹脂封止型半導体装置及びその製造方法 | |
| JP3701949B2 (ja) | 半導体チップ搭載用配線基板及びその製造方法 | |
| JP5587464B2 (ja) | 半導体装置の製造方法 | |
| JP4174008B2 (ja) | 半導体装置 | |
| JP4038021B2 (ja) | 半導体装置の製造方法 | |
| JP2004172647A (ja) | 半導体装置 | |
| JP4737995B2 (ja) | 半導体装置 | |
| JP2011044747A (ja) | 半導体装置の製造方法 | |
| JP2012124537A (ja) | 半導体装置 | |
| JP2014207471A (ja) | 半導体装置の製造方法 | |
| JP3398556B2 (ja) | 半導体装置の製造方法 | |
| JPH10189792A (ja) | 半導体パッケージ | |
| JPH11274360A (ja) | 半導体装置及びその製造方法 | |
| JP4175339B2 (ja) | 半導体装置の製造方法 | |
| TWI416698B (zh) | 半導體封裝結構 | |
| JPH0992767A (ja) | 複合リードフレームおよび半導体装置 | |
| KR19990003579U (ko) | 반도체 패키지 | |
| JPH02260445A (ja) | Icパッケージ | |
| JP2002217335A (ja) | 半導体装置およびその製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20040311 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20040311 |
|
| A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20040311 |
|
| A871 | Explanation of circumstances concerning accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A871 Effective date: 20040311 |
|
| A975 | Report on accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A971005 Effective date: 20040415 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20040810 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20041012 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20041102 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20041115 |
|
| R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 Ref document number: 3619773 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071119 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081119 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081119 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091119 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101119 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111119 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111119 Year of fee payment: 7 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313115 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111119 Year of fee payment: 7 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111119 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121119 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121119 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131119 Year of fee payment: 9 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313115 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| EXPY | Cancellation because of completion of term |