JP5037071B2 - 樹脂封止型半導体装置の製造方法 - Google Patents
樹脂封止型半導体装置の製造方法 Download PDFInfo
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- JP5037071B2 JP5037071B2 JP2006232524A JP2006232524A JP5037071B2 JP 5037071 B2 JP5037071 B2 JP 5037071B2 JP 2006232524 A JP2006232524 A JP 2006232524A JP 2006232524 A JP2006232524 A JP 2006232524A JP 5037071 B2 JP5037071 B2 JP 5037071B2
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- resin
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
Claims (7)
- 実装領域に半導体チップが実装され、一端側に樹脂を前記半導体チップの周りに流入させるためのモールドゲート部が設けられた配線基板であって、前記モールドゲート部に、点在する抜きパターンを内部にもつ金属パターン層が露出して設けられた前記配線基板を用意する工程と、
前記配線基板にモールド型を設置することにより、前記半導体チップの周りにキャビティを設けると共に、モールドゲート部の前記金属パターン層の上に前記キャビティに繋がる樹脂流入部を設ける工程と、
前記モールドゲート部上の前記樹脂流入部を通して前記樹脂を前記キャビティ内に充填して前記半導体チップを封止するモールド樹脂を形成する工程と、
前記樹脂流入部に形成されたゲート樹脂部を前記金属パターン層に対して選択的に除去する工程とを有し、
前記金属パターン層の抜きパターンを含む全体の配置面積を100%とするとき、前記抜きパターンのトータル面積は5乃至20%であることを特徴とする樹脂封止型半導体装置の製造方法。 - 前記配線基板を用意する工程において、前記金属パターン層は、最上に金層を備えていることを特徴とする請求項1に記載の樹脂封止型半導体装置の製造方法。
- 前記配線基板を用意する工程において、前記金属パターン層は、複数の島状パターンが連結部によって相互に繋がって構成されることを特徴とする請求項1に記載の樹脂封止型半導体装置の製造方法。
- 前記配線基板を用意する工程において、
前記配線基板には、前記モールドゲート部及び該配線基板の配線層の接続部の上に開口部が設けられたソルダレジストが形成されており、
前記半導体チップは前記ソルダレジストの上に実装され、前記配線層の前記接続部にワイヤで接続されていることを特徴とする請求項1乃至3のいずれか一項に記載の樹脂封止型半導体装置の製造方法。 - 前記配線基板にモールド型を設置する工程において、前記モールド型は、前記配線基板の下に配置される下型と、前記配線基板及び前記半導体チップの上側に配置されて前記キャビティ及び前記樹脂流入部を構成する上型とによって構成され、
前記ゲート樹脂部を除去する工程において、前記ゲート樹脂部を折り取って前記モールド樹脂から分離することを特徴とする請求項1乃至3のいずれか一項に記載の樹脂封止型半導体装置の製造方法。 - 前記配線基板を用意する工程において、前記配線基板には複数の前記実装領域に複数の前記半導体チップがそれぞれ実装されており、
前記ゲート樹脂部を除去する工程の後に、
前記モールドゲート部が分離された状態で個々の半導体装置が得られるように前記配線基板を切断する工程をさらに有することを特徴とする請求項1乃至3のいずれか一項に記載の樹脂封止型半導体装置の製造方法。 - 前記配線基板を用意する工程において、前記配線層は前記配線基板のスルーホールを介して相互接続された状態で前記配線基板の両面側に設けられており、
前記配線基板を切断する工程の前又は後に、前記配線基板の前記半導体チップと反対面側の前記配線層に接続される外部接続端子を設ける工程をさらに有することを特徴とする請求項6に記載の樹脂封止型半導体装置の製造方法。
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EP3823010A1 (en) * | 2019-11-15 | 2021-05-19 | Semtech Corporation | Semiconductor device and method of forming mold degating structure for pre-molded substrate |
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KR101066642B1 (ko) * | 2009-08-31 | 2011-09-22 | 삼성전기주식회사 | 인쇄회로기판 제조방법 |
CN113690148A (zh) * | 2021-08-31 | 2021-11-23 | 青岛歌尔微电子研究院有限公司 | 一种塑封方法和封装模组 |
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JPH0936155A (ja) * | 1995-07-18 | 1997-02-07 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法 |
JPH11297921A (ja) * | 1998-04-14 | 1999-10-29 | Mitsubishi Electric Corp | 半導体装置用フレームおよびその製造方法並びに半導体装置用フレームを用いた半導体装置の製造方法 |
JP3020201B2 (ja) * | 1998-05-27 | 2000-03-15 | 亜南半導体株式会社 | ボールグリッドアレイ半導体パッケージのモールディング方法 |
JP3619773B2 (ja) * | 2000-12-20 | 2005-02-16 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
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EP3823010A1 (en) * | 2019-11-15 | 2021-05-19 | Semtech Corporation | Semiconductor device and method of forming mold degating structure for pre-molded substrate |
KR20210060341A (ko) * | 2019-11-15 | 2021-05-26 | 셈테크 코포레이션 | 프리-몰딩된 기판을 위한 몰드 디게이팅 구조물을 형성하는 반도체 디바이스 및 방법 |
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