JP2016029710A - 半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 239000010410 layer Substances 0.000 claims description 176
- 239000000758 substrate Substances 0.000 claims description 24
- 239000002344 surface layer Substances 0.000 claims description 5
- 210000000746 body region Anatomy 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 238000012216 screening Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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Abstract
【解決手段】トレンチ13をIGBT領域1aおよびダイオード領域1bにそれぞれ形成する。また、ダイオード領域1bに配置された少なくとも一部のゲート電極17bをIGBT領域1aに配置されたゲート電極17aと異なる制御ができるようにする。そして、ダイオード領域1bに配置された少なくとも一部のゲート電極17bに、第1電極19とドリフト層11との間を繋ぐ反転層24が形成されない電圧を印加する。
【選択図】図2
Description
本発明の第1実施形態について説明する。なお、本実施形態の半導体装置は、例えば、インバータ、DC/DCコンバータ等の電源回路に使用されるパワースイッチング素子として利用されると好適である。
本発明の第2実施形態について説明する。本実施形態は、第1実施形態に対して第2ゲート電極17bを第2ゲートパッドと接続するものであり、その他に関しては第1実施形態と同様であるため、ここでは説明を省略する。
本発明の第3実施形態について説明する。本実施形態は、第1実施形態に対して、IGBT領域1aにダミーゲート電極を備えるものであり、その他に関しては第1実施形態と同様であるため、ここでは説明を省略する。
上記第3実施形態では、ダミーゲート電極25bを第3ゲートパッド3cと電気的に接続する例について説明したが、図8に示されるように、ダミーゲート電極25bを第2ゲートパッド3bと電気的に接続するようにしてもよい。すなわち、ダミーゲート電極25bと第2ゲート電極17bとを同じ第2ゲートパッド3bと接続するようにしてもよい。
本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。
11 ドリフト層
12 ベース層
13 トレンチ
14 エミッタ領域
16 ゲート絶縁膜
17a、17b 第1、第2ゲート電極
19 上部電極(第1電極)
21 コレクタ層
22 カソード層
23 下部電極(第2電極)
Claims (5)
- 第1導電型のドリフト層(11)を構成する半導体基板(10)と、
前記ドリフト層上に形成された第2導電型のベース層(12)と、
前記ドリフト層のうちの前記ベース層側と反対側に形成された第2導電型のコレクタ層(21)および第1導電型のカソード層(22)と、
前記ベース層を貫通して前記ドリフトに達する複数のトレンチ(13)と、
前記トレンチの壁面に形成されたゲート絶縁膜(16)と、
前記ゲート絶縁膜上に形成されたゲート電極(17a、17b)と、
前記ベース層の表層部に形成され、前記トレンチと接する第1導電型のエミッタ領域(14)と、
前記ベース層および前記エミッタ領域と電気的に接続される第1電極(19)と、
前記コレクタ層および前記カソード層と電気的に接続される第2電極(23)と、を備え、
前記半導体基板のうちのIGBT素子として動作する領域がIGBT領域(1a)とされていると共にダイオード素子として動作する領域がダイオード領域(1b)とされている半導体装置において、
前記トレンチは、前記IGBT領域および前記ダイオード領域にそれぞれ形成され、
前記ダイオード領域に配置された少なくとも一部の前記ゲート電極(17b)は、前記IGBT領域に配置された少なくとも一部の前記ゲート電極(17a)と異なる制御が可能とされており、前記ベース層に前記第1電極と前記ドリフト層との間を繋ぐ反転層(24)が形成されない電圧が印加されることを特徴とする半導体装置。 - 前記ダイオード領域に配置された少なくとも一部の前記ゲート電極は、前記第1電極と電気的に接続されることにより、前記エミッタ領域と同電位とされていることを特徴とする請求項1に記載の半導体装置。
- 前記ダイオード領域に配置された少なくとも一部の前記ゲート電極は、前記IGBT領域に配置された少なくとも一部の前記ゲート電極が接続されているゲートパッド(3a)と異なるゲートパッド(3b)に接続されていることを特徴とする請求項1に記載の半導体装置。
- 前記IGBT領域に配置された前記ゲート電極は、素子ゲート電極(25a)と、ダミーゲート電極(25b)とを有し、前記素子ゲート電極と前記ダミーゲート電極とは互いに異なる制御が可能とされており、
前記素子ゲート電極には、前記IGBT素子を動作させる電圧が印加され、前記ダミーゲート電極には、前記ベース層に前記第1電極と前記ドリフト層との間を繋ぐ前記反転層が形成されない電圧が印加されることを特徴とする請求項3に記載の半導体装置。 - 前記第2ゲート電極と前記ダミーゲート電極とは、前記素子ゲート電極が接続されているゲートパッド(3a)と異なる共通のゲートパッド(3b)と接続されていることを特徴とする請求項4に記載の半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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JP2015120461A JP6459791B2 (ja) | 2014-07-14 | 2015-06-15 | 半導体装置およびその製造方法 |
PCT/JP2015/003420 WO2016009616A1 (ja) | 2014-07-14 | 2015-07-07 | 半導体装置 |
US15/310,244 US10388773B2 (en) | 2014-07-14 | 2015-07-07 | Semiconductor device and manufacturing method of the same |
CN201580038290.1A CN106537598B (zh) | 2014-07-14 | 2015-07-07 | 半导体装置 |
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JP2014144169 | 2014-07-14 | ||
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JP2015120461A JP6459791B2 (ja) | 2014-07-14 | 2015-06-15 | 半導体装置およびその製造方法 |
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JP2016029710A true JP2016029710A (ja) | 2016-03-03 |
JP2016029710A5 JP2016029710A5 (ja) | 2016-09-01 |
JP6459791B2 JP6459791B2 (ja) | 2019-01-30 |
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US (1) | US10388773B2 (ja) |
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WO (1) | WO2016009616A1 (ja) |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018016282A1 (ja) * | 2016-07-21 | 2018-01-25 | 株式会社デンソー | 半導体装置 |
JP2018021801A (ja) * | 2016-08-02 | 2018-02-08 | 株式会社デンソー | 半導体素子の検査装置 |
CN107924951A (zh) * | 2016-03-10 | 2018-04-17 | 富士电机株式会社 | 半导体装置 |
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US10388773B2 (en) | 2019-08-20 |
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WO2016009616A1 (ja) | 2016-01-21 |
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