JPWO2019078131A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JPWO2019078131A1 JPWO2019078131A1 JP2019549253A JP2019549253A JPWO2019078131A1 JP WO2019078131 A1 JPWO2019078131 A1 JP WO2019078131A1 JP 2019549253 A JP2019549253 A JP 2019549253A JP 2019549253 A JP2019549253 A JP 2019549253A JP WO2019078131 A1 JPWO2019078131 A1 JP WO2019078131A1
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- 150000004767 nitrides Chemical class 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
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- 229910000676 Si alloy Inorganic materials 0.000 description 1
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Abstract
Description
特許文献1 特開2016−131224号公報
Claims (16)
- 第1導電型のドリフト領域を有する半導体基板と、
前記半導体基板に形成され、第2導電型のコレクタ領域を有するトランジスタ部と、
前記半導体基板に形成され、第1導電型のカソード領域を有するダイオード部と、
前記半導体基板に形成され、前記半導体基板の上面において前記トランジスタ部および前記ダイオード部の間に配置され、前記コレクタ領域を有する境界部と
を備え、
前記トランジスタ部および前記境界部のそれぞれは、
前記半導体基板の上面において長手方向を有し、前記半導体基板の上面から前記半導体基板の内部まで設けられた、1つ以上のゲートトレンチ部を含むトレンチ部と、
2つの前記トレンチ部に挟まれたメサ部と
を有し、
前記トランジスタ部および前記境界部の前記メサ部には、前記ドリフト領域よりもドーピング濃度の高いエミッタ領域が設けられ、
前記境界部の前記メサ部の上面において前記エミッタ領域が前記ゲートトレンチ部に接する部分であるチャネル部の、前記メサ部の上面における密度は、前記トランジスタ部の前記メサ部の上面における前記チャネル部の前記密度よりも小さい
半導体装置。 - 前記トランジスタ部および前記境界部の前記メサ部の上面には、前記エミッタ領域と、第2導電型の領域とが前記トレンチ部の長手方向に沿って交互に配置されており、
前記トレンチ部の長手方向における前記第2導電型の領域の長さは、前記境界部のほうが、前記トランジスタ部よりも大きい
請求項1に記載の半導体装置。 - 前記トレンチ部の長手方向における一つの前記エミッタ領域の長さは、前記トランジスタ部および前記境界部で同一である
請求項2に記載の半導体装置。 - 前記トレンチ部の長手方向における一つの前記エミッタ領域の長さは、前記境界部のほうが、前記トランジスタ部よりも小さい
請求項2に記載の半導体装置。 - 前記半導体基板の上面において、前記境界部における前記エミッタ領域は、前記トランジスタ部における前記エミッタ領域と対向する位置に配置されている
請求項2から4のいずれか一項に記載の半導体装置。 - 前記半導体基板の上面において、前記境界部における前記エミッタ領域は、前記トランジスタ部における前記第2導電型の領域と対向する位置に配置されている
請求項2から4のいずれか一項に記載の半導体装置。 - 前記境界部の前記メサ部における前記エミッタ領域のうち、前記トレンチ部の長手方向において最も端に配置された前記エミッタ領域は、前記トランジスタ部の前記メサ部における前記エミッタ領域のうち、前記トレンチ部の長手方向において最も端に配置された前記エミッタ領域よりも、前記長手方向における前記メサ部の中央寄りに配置されている
請求項2から6のいずれか一項に記載の半導体装置。 - 前記半導体基板に形成され、前記半導体基板の上面において前記ダイオード部および前記境界部の間に配置され、前記コレクタ領域を有する抑制部を更に備え、
前記抑制部は、前記メサ部を有し、
前記抑制部の前記メサ部は、上面において前記トランジスタ部の前記第2導電型の領域よりもドーピング濃度の低い第2導電型の領域を有する
請求項2から7のいずれか一項に記載の半導体装置。 - 前記トランジスタ部のそれぞれの前記メサ部の上面には、前記ゲートトレンチ部に接する一つの前記エミッタ領域が、前記トレンチ部の長手方向に沿って連続して設けられており、
前記境界部のそれぞれの前記メサ部の上面には、前記ゲートトレンチ部に接する複数の前記エミッタ領域が、前記トレンチ部の長手方向に沿って離散的に設けられている
請求項1に記載の半導体装置。 - 前記半導体基板に形成され、前記半導体基板の上面において前記トランジスタ部および前記境界部の間に配置され、前記コレクタ領域を有する引抜部を更に備え、
前記引抜部は、前記メサ部を有し、
前記引抜部の前記メサ部は、上面において第2導電型のコンタクト領域を有し、且つ、上面において第1導電型の領域を有さない
請求項1から9のいずれか一項に記載の半導体装置。 - 前記半導体基板に形成され、前記半導体基板の上面において前記ダイオード部および前記境界部の間に配置され、前記コレクタ領域を有する引抜部を更に備え、
前記引抜部は、前記メサ部を有し、
前記引抜部の前記メサ部は、上面において第2導電型のコンタクト領域を有し、且つ、上面において第1導電型の領域を有さない
請求項1から10のいずれか一項に記載の半導体装置。 - 前記境界部は2つ以上の前記メサ部を有し、
前記境界部のそれぞれの前記メサ部における前記チャネル部の密度は、前記ダイオード部に近いメサほど小さい
請求項1から11のいずれか一項に記載の半導体装置。 - 前記境界部における前記チャネル部の前記密度は、前記トランジスタ部における前記チャネル部の前記密度の10%以上、90%以下である
請求項1から12のいずれか一項に記載の半導体装置。 - 前記ダイオード部は、1つ以上の前記ゲートトレンチ部を含む前記トレンチ部と、前記メサ部とを有し、
前記ダイオード部の前記メサ部には、前記ドリフト領域よりもドーピング濃度の高いエミッタ領域が設けられる
請求項1から13のいずれか一項に記載の半導体装置。 - 前記半導体基板の上面において、前記境界部が前記トランジスタ部を囲んで配置されている
請求項1から14のいずれか一項に記載の半導体装置。 - 前記半導体基板の上面において、前記境界部が前記ダイオード部を囲んで配置されている
請求項1から15のいずれか一項に記載の半導体装置。
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