JP2018014418A - 半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 210000000746 body region Anatomy 0.000 claims abstract description 40
- 238000009825 accumulation Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 238000010992 reflux Methods 0.000 abstract 1
- 230000010355 oscillation Effects 0.000 description 19
- 230000003071 parasitic effect Effects 0.000 description 7
- 230000007423 decrease Effects 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Abstract
【解決手段】この半導体装置は、還流ダイオードを備えた複数のIGBT素子が並列に接続されて駆動される。IGBT素子は、トレンチゲートにゲート電圧が印加されるとともに、エミッタ領域が形成されるアクティブセルと、トレンチゲートがエミッタ領域と同電位とされるとともに、エミッタ領域が形成されないダミーセルと、トレンチゲートにゲート電圧が印加されるとともに、エミッタ領域が形成されないアクティブダミーセルと、を有する。そして、アクティブダミーセルは、ボディ領域が電気的にフローティングとされたフロートセルを有する。フロートセルの数は、アクティブセルとアクティブダミーセルの総数に対して、5%以上35%以下とされる。
【選択図】図6
Description
還流ダイオードを備えた複数のIGBT素子が並列に接続されて駆動される半導体装置であって、
IGBT素子は、第1導電型のコレクタ領域と、コレクタ領域に積層された第2導電型のドリフト領域と、ドリフト領域に積層された第1導電型のボディ領域と、ボディ領域を貫通してドリフト領域に達するトレンチゲートと、ボディ領域に取り囲まれつつトレンチゲートに絶縁膜を介して接触するエミッタ領域と、を備え、
IGBT素子は、
トレンチゲートにゲート電圧が印加されるとともに、エミッタ領域が形成されるアクティブセルと、
トレンチゲートがエミッタ領域と同電位とされるとともに、エミッタ領域が形成されないダミーセルと、
トレンチゲートにゲート電圧が印加されるとともに、エミッタ領域が形成されないアクティブダミーセルと、を有し、
アクティブダミーセルは、ボディ領域が電気的にフローティングとされたフロートセルを有し、
フロートセルの数は、アクティブセルとアクティブダミーセルの総数に対して、5%以上35%以下とされる。
最初に、図1を参照して、本実施形態に係る半導体装置100の概略構成について説明する。
以上、本発明の好ましい実施形態について説明したが、本発明は上記した実施形態になんら制限されることなく、本発明の主旨を逸脱しない範囲において、種々変形して実施することが可能である。
Claims (4)
- 還流ダイオードを備えた複数のIGBT素子が並列に接続されて駆動される半導体装置であって、
前記IGBT素子は、
第1導電型のコレクタ領域と、
前記コレクタ領域に積層された第2導電型のドリフト領域と、
前記ドリフト領域に積層された第1導電型のボディ領域と、
前記ボディ領域を貫通して前記ドリフト領域に達するトレンチゲートと、
前記ボディ領域に取り囲まれつつ、前記トレンチゲートに絶縁膜を介して接触するエミッタ領域と、を備え、
前記IGBT素子は、
前記トレンチゲートにゲート電圧が印加されるとともに、前記エミッタ領域が形成されるアクティブセルと、
前記トレンチゲートがエミッタ領域と同電位とされるとともに、前記エミッタ領域が形成されないダミーセルと、
前記トレンチゲートにゲート電圧が印加されるとともに、前記エミッタ領域が形成されないアクティブダミーセルと、を有し、
前記アクティブダミーセルは、前記ボディ領域が電気的にフローティングとされたフロートセルを有し、
前記フロートセルの数は、前記アクティブセルと前記アクティブダミーセルの総数に対して、5%以上35%以下とされる半導体装置。 - 前記ドリフト領域は、前記ボディ領域に接する領域に、前記ドリフト領域の他の領域よりも不純物濃度が高くされた電荷蓄積領域を有する請求項1に記載の半導体装置。
- 前記還流ダイオードは、前記IGBT素子が形成されたセル領域内に形成される請求項1または請求項2に記載の半導体装置。
- 前記還流ダイオードは、前記IGBT素子が形成されたセル領域の外部に配置される請求項1または請求項2に記載の半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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JP2016143299A JP6565814B2 (ja) | 2016-07-21 | 2016-07-21 | 半導体装置 |
PCT/JP2017/023901 WO2018016282A1 (ja) | 2016-07-21 | 2017-06-29 | 半導体装置 |
CN201780044661.6A CN109478564B (zh) | 2016-07-21 | 2017-06-29 | 半导体装置 |
US16/250,094 US10734376B2 (en) | 2016-07-21 | 2019-01-17 | Semiconductor device |
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JP2016143299A JP6565814B2 (ja) | 2016-07-21 | 2016-07-21 | 半導体装置 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2019220940A1 (ja) * | 2018-05-17 | 2019-11-21 | 富士電機株式会社 | 半導体装置 |
CN110610935A (zh) * | 2018-06-15 | 2019-12-24 | 英飞凌科技股份有限公司 | 电力电子装置 |
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JP6946219B2 (ja) * | 2018-03-23 | 2021-10-06 | 株式会社東芝 | 半導体装置 |
JP7353891B2 (ja) | 2019-09-20 | 2023-10-02 | 株式会社東芝 | 半導体装置及び半導体回路 |
DE102021113880A1 (de) * | 2021-05-28 | 2022-12-01 | Infineon Technologies Austria Ag | Rc-igbt enthaltende halbleitervorrichtung |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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