CN109478564B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN109478564B
CN109478564B CN201780044661.6A CN201780044661A CN109478564B CN 109478564 B CN109478564 B CN 109478564B CN 201780044661 A CN201780044661 A CN 201780044661A CN 109478564 B CN109478564 B CN 109478564B
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河野宪司
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Denso Corp
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Abstract

半导体装置具备多个IGBT元件和对应于各IGBT元件的续流二极管。多个IGBT元件并联地连接而被驱动。多个IGBT元件分别具有集电极区域(11)、漂移区域(10)、体区域(13)、将体区域贯通而到达漂移区域的沟槽栅极(G1、G2、G3、G4)、以及被体区域包围并且隔着绝缘膜而与沟槽栅极接触的发射极区域(14)。多个IGBT元件分别还具有形成了发射极区域的有源单元、没有形成发射极区域的伪单元、以及没有形成发射极区域的有源伪单元。有源伪单元具有体区域被电气地浮置的浮置单元。相对于有源单元和有源伪单元的总数，浮置单元的数量被设为5％以上且35％以下。

Description

半导体装置
关联申请的相互参照
本申请基于2016年7月21日提出申请的日本专利申请第2016－143299号主张优先权，这里引用其全部内容。
技术领域
本发明涉及多个开关元件被并联驱动的导体装置。
背景技术
如专利文献1那样，已知一种半导体装置，其通过使多个开关元件并联地连接并以适当的定时进行接通或断开，能够减小开关时的损失而进行输出电流的控制。
在并联驱动的半导体装置中，在开关元件间产生寄生电感。因此，在开关时产生感应电动势，产生电压振动及伴随着电压振动的输出电流的振动。
对于该电压振动，例如在采用绝缘栅双极型晶体管(IGBT)作为开关元件的情况下，能够采用对一部分单元不形成发射极区域的间隔剔除(日语原文：間引き)构造。关于间隔剔除构造，在不存在发射极区域的间隔剔除部，导通时成为沟道的体(body)区域被连接到发射极电极而成为发射极电位(通常接地)。
现有技术文献
专利文献
专利文献1：日本特开2000－40951号公报
发明概要
此外，通过调整存在于体区域与发射极电极之间的电阻的值，能够控制开关速度、导通电压、电压振动、由续流二极管(FWD)引起的波形失真的各量。
例如，如果将该电阻值设定得比较小，则空穴容易脱离，所以开关速度变快，另一方面，导通电压及电压振动变大。
另一方面，如果将该电阻值设定得比较大，则虽然能够抑制导通电压的增加和电压振动，但是由FWD引起的波形失真变大。
即，仅通过该电阻值的调整，无法消除开关速度、导通电压、电压振动、由续流二极管(FWD)引起的波形失真的各量的此消彼长。
发明内容
因此，本发明的目的在于，提供一种半导体装置，其兼顾了由开关元件的并联驱动引起的电压振动的降低和由FWD引起的波形失真的降低。
本发明的一技术方案的半导体装置具备多个IGBT元件以及与上述多个IGBT元件对应的续流二极管。多个IGBT元件并联地连接而被驱动。多个IGBT元件分别还具有第1导电型的集电极区域、层叠于集电极区域的第2导电型的漂移区域、层叠于漂移区域的第1导电型的体区域、将体区域贯通而到达漂移区域的沟槽栅极、以及被体区域包围并且隔着绝缘膜而与沟槽栅极接触的发射极区域。此外，多个IGBT元件分别还具有：有源单元，在沟槽栅极上被施加栅极电压，并且形成了发射极区域；伪单元，沟槽栅极被设为与发射极区域相同的电位，并且没有形成发射极区域；以及有源伪单元，在沟槽栅极上被施加栅极电压，并且没有形成发射极区域。此外，有源伪单元具有体区域被电气地浮置的浮置单元。进而，相对于有源单元和有源伪单元的总数，浮置单元的数量被设为5％以上且35％以下。
发明者发现，浮置单元相对于有源单元和有源伪单元的总数的比例越增加，由续流二极管(FWD)引起的波形失真越恶化。此外，发明者发现，浮置单元相对于有源单元和有源伪单元的总数的比例越减少，由并联驱动引起的电压振动越恶化。所以，通过将浮置单元的数量设定为有源单元和有源伪单元的总数的5％以上且35％以下，能够兼顾电压振动的降低和波形失真的降低。
附图说明
关于本发明的上述目的及其他目的、特征及优点一边参照附图一边通过下述详细的记述会变得更明确。
图1是表示第1实施方式的半导体装置的结构的等价电路图。
图2是表示开关元件的概略结构的俯视图。
图3是表示沿着图2的III－III线的截面的剖视图。
图4是有源单元及浮置单元的详细剖视图。
图5是表示集电极电压、阳极－阴极间电压、发射极电压的变化的图。
图6是表示与浮置率对应的波形失真及电压振动的量的变化的图。
图7是表示其他实施方式的有源单元及浮置单元的详细剖视图。
具体实施方式
以下，基于附图对本发明的实施方式进行说明。另外，在以下的各图相互间，对于相互相同或等同的部分赋予相同的标号。
(第1实施方式)
首先，参照图1对本实施方式的半导体装置100的概略结构进行说明。
本实施方式的半导体装置例如用于将多个逆导通绝缘栅双极型晶体管(RC－IGBT)并联连接而得到输出电流的开关电路。
图1是本实施方式的半导体装置100的等价电路。如图1所示，半导体装置100将在从电源VCC到作为基准电位的地电位(GND)之间串联连接的开关元件110并联连接2组而成。即，多个开关元件110相对于电源VCC并联地连接。开关元件110具备IGBT元件Tr。在本实施方式中，2个IGBT元件Tr在电源VCC与输出OUT之间并联地连接。高压侧的IGBT元件Tr的集电极端子被连接到电源VCC侧，发射极端子是输出OUT侧。此外，能够对各IGBT元件Tr的栅极端子施加栅极电压。另外，低压侧的IGBT元件Tr的集电极端子被连接到输出OUT侧，发射极端子是GND侧。低压侧的IGBT元件Tr也相对于输出OUT并联地连接。
此外，构成半导体装置100的开关元件110是RC－IGBT，具备与各IGBT元件Tr对应的续流二极管元件Di。各续流二极管元件Di以阳极端子被连接到对应的IGBT元件Tr的发射极端子的方式形成。
在并联连接的开关元件110之间产生寄生电感L。在图1中，作为代表例而示出了在电源VCC与开关元件110的连接布线、栅极布线、IGBT元件Tr的发射极布线中产生寄生电感L的例子，但是例如在开尔文发射极布线或其他布线中也会产生寄生电感L。
接着，参照图2～图4，对IGBT元件Tr及续流二极管元件Di的详细结构进行说明。多个开关元件110相互等价，并且各IGBT元件Tr及各续流二极管元件Di分别等价，所以对一个开关元件110进行说明。
开关元件110如图2所示，具备形成有IGBT元件Tr和续流二极管元件Di的单元区域111、和位于单元区域111的外周的非单元区域112。
在非单元区域112，形成有用于与外部电连接的焊盘113。在焊盘113，连接着未图示的键合线，例如电源VCC及栅极电压等经由该焊盘113而被输入到单元区域111。电源VCC与开关元件110之间的连接布线、栅极布线、IGBT元件Tr的发射极布线及开尔文发射极布线等布线类从焊盘113延伸形成并到达单元区域111。如果将并联连接的多个开关元件110相互接近地安装，则在这些布线间会产生寄生电感L。
单元区域111具有形成IGBT元件Tr的IGBT单元和形成续流二极管元件Di的二极管单元。IGBT单元和二极管单元成为彼此在相同的方向上延伸设置、并且在与延伸设置方向正交的方向上交替地配置的条带构造。
参照图3对IGBT单元及二极管单元的详细构造进行说明。图3是沿着图2中的III－III线的剖视图。在图3中，对后述的沟槽栅G1～G4及p导电型的半导体区域施加了影线，对n导电型的半导体区域没有施加影线。如图3所示，以虚线为边界，纸面左侧是IGBT单元，纸面右侧是二极管单元。
IGBT单元中，作为半导体区域，具备n导电型的漂移区域10、p导电型的集电极区域11、p导电型的体区域13、和n导电型的发射极区域14。此外，IGBT单元具备沟槽栅G1～G4。
漂移区域10层叠在集电极区域11上。体区域13层叠在漂移区域10上。体区域13在半导体基板的表面13a露出，未图示的发射极电极与体区域13连接。沟槽栅G1～G4从表面13a将体区域13贯通而到达漂移区域10。沟槽栅G1～G4隔着未图示的绝缘膜而与体区域13及漂移区域10相接。另外，漂移区域10在与体区域13接触的接触面表层具有与漂移区域10的其他部分相比杂质浓度高的电荷蓄积区域10b。即，漂移区域10包括电荷蓄积区域10b和除了电荷蓄积区域10b以外的部分10a。
本实施方式的沟槽栅G1～G4在构造上是等价的，但根据对沟槽栅G1～G4施加的栅极电压的不同而大体上分类为2种。即，沟槽栅分类为被施加栅极电压的有源栅极G1、G2、G4、和代替栅极电压而被连接到发射极电位(例如地电位：GND)的伪栅极G3。
进而，有源栅极分类为隔着绝缘膜而接触发射极区域14的沟槽栅极G1、和不接触发射极区域14的沟槽栅即有源伪栅极G2。发射极区域14连接着未图示的发射极电极，被设为发射极电位(GND)。此外，没有形成发射极区域14的体区域13的一部分也连接于发射极电极而被设为发射极电位。
沟槽栅G1～G4沿着IGBT单元的延伸设置方向而延伸设置。并且，本实施方式的沟槽栅极在与延伸设置方向正交的方向上交替地设定了有源栅极G1、G2、G4和伪栅极G3。此外，在有源栅极G1、G2、G4中，与发射极区域14相接的沟槽栅极G1、和有源伪栅极G2在与延伸设置方向正交的方向上被交替地设定。
在本说明书中，将包括有源栅极中的与发射极区域14相接的沟槽栅极G1、和夹着沟槽栅极G1而形成的体区域13的单元称作有源单元。此外，将包括有源伪栅极G2、和夹着有源伪栅极G2而形成的体区域13的单元称作有源伪单元。此外，将包括伪栅极G3和夹着伪栅极G3而形成的体区域13的单元称作伪单元。
进而，在本实施方式中，有源伪单元中的一部分被设为体区域13不与发射极电位连接而电气地浮置的浮置单元。在图3中，带有标号G4的有源伪栅极是属于该浮置单元的沟槽栅极。在图3中，与沟槽栅极G4相接的两旁的体区域13都没有与发射极电位连接而电气地浮置。在这样的形态下将浮置单元计数为1条，例如在仅单方的体区域13浮置的情况下，将浮置单元计数为0.5条。
参照图4对体区域13被设为发射极电位的有源单元和体区域13电气地浮置的浮置单元的构造更详细地进行说明。
在有源单元中，形成有包含在体区域13中并且与体区域13相比浓度高的p导电型的接触区域15。接触区域15与被设为发射极电位的发射极电极16电连接。由此，体区域13被设为发射极电位。沟槽栅极G1和发射极电极16被绝缘膜17电分离。在本实施方式中，沟槽栅极G1在一个方向上延伸设置，发射极区域14、接触区域15也沿着沟槽栅极G1延伸设置。即，从上表面观察，它们形成为条带状。
另一方面，在浮置单元中，如图4所示，体区域13和发射极电极16被绝缘膜17电绝缘，体区域13成为浮置的状态。
如图3所示，本实施方式的沟槽栅极中，有源栅极G1、G2、G4和伪栅极G3被交替地设定，进而，在有源栅极中，沟槽栅极G1和有源伪栅极G2被交替地设定。即，有源单元与伪单元相邻地配置，由两个单元共用在单元中包含的一部分体区域13。此外，伪单元和有源伪单元相邻地配置，由两个单元共用在单元中包含的一部分体区域13。
本实施方式的IGBT单元如图3所示，以包含3条有源单元和3条有源伪单元(其中1条是浮置单元)的单元群为单位，周期性地形成各单元。即，本实施方式的浮置单元的数量相对于有源单元和有源伪单元的总数而言是1条/6条＝16.7％。
另一方面，二极管单元中，作为半导体区域而具备与IGBT单元共通的漂移区域10、与IGBT单元共通的体区域13、以及相对于漂移区域10形成在与体区域13相反侧的n导电型的阴极区域12。另外，阴极区域12形成在与IGBT单元的集电极区域11相同的面内。二极管单元中的体区域13还能够另外命名为阳极区域。形成于二极管单元的沟槽栅极全部是伪栅极G3，其电位为与发射极电位相同的电位。此外，二极管单元的体区域13为发射极电位(GND)。另外，形成于IGBT单元的电荷蓄积区域10b在二极管单元侧也共通地形成。
接着，参照图5，说明开关元件110的集电极电压Vc、并联连接的2个IGBT元件Tr的发射极间电压ΔVe、二极管单元的阳极－阴极间电压Vak的动态。另外，dVe及dVak表示的电位差也在图1中图示。
如图5所示，在对有源栅极G1、G2、G4施加栅极电压的情况下IGBT元件导通。由此，集电极电压下降。另一方面，续流二极管元件Di的两端的电压Vak上升。
此时，在集电极电压Vc开始下降的定时，Vak在上升后下降，然后再次上升。将Vak最初上升的极大值和下降的极小值的差定义为由续流二极管Di引起的波形失真dVak。
此外，在集电极电压Vc下降而达到应收敛的大致一定值的定时，Vak停止上升而成为大致一定值，但此时起因于寄生电感L而发生电压振动。发射极电压Ve也起因于寄生电感L而发生电压振动，结果，并联连接的2个IGBT元件Tr的发射极间电压ΔVe振动。将该振动的振幅的最大值定义为电压振动dVe。
另外，在图5中，图示了来源于IGBT元件Tr的导通的波形失真dVak、以及电压振动dVe，但关于关断也是同样的。
接着，参照图6，说明采用本实施方式的半导体装置100的作用效果。
发明者在将浮置单元相对于有源单元与有源伪单元的总数的数值称作浮置率时，通过模拟求出了相对于浮置率的波形失真dVak及电压振动dVe的变化。图6是表示其结果的曲线图。
根据图6，在浮置率为5％以上的水准下，与不到5％的水准相比，能够抑制电压振动dVe。另一方面，在浮置率为35％以下的水准下，与比35％大的水准相比，能够抑制波形失真dVak。即，在浮置率为5％以上且35％以下的条件下，能够兼顾电压振动的降低和波形失真的降低。
此外，本实施方式的开关元件110，作为漂移区域10的一部分，具备杂质浓度高的电荷蓄积区域10b，所以与没有形成电荷蓄积区域10b的形态相比能够降低导通电压。即，开关元件110能够抑制导通电压的增加，并且兼顾电压振动的降低和波形失真的降低。
(其他实施方式)
以上，对本发明的优选的实施方式进行了说明，但本发明完全不受上述实施方式限制，在不脱离本发明主旨的范围内能够各种各样地变形实施。
在上述实施方式中，对具备电荷蓄积区域10b的开关元件110进行了说明，但电荷蓄积区域10b不是必须的结构，在特别要求导通电压的降低的情况下形成即可。此外，可以在漂移区域10、与集电极区域11或阴极区域12之间形成场截止区域。
此外，在上述实施方式中，说明了有源栅极G1、G2、G4和伪栅极G3交替地配置的例子，但并不限定于该例。只要浮置单元的数量相对于有源单元与有源伪单元的总数为5％以上35％以下，例如也可以对2个有源栅极形成1个伪栅极。
此外，在上述实施方式中，说明了接触区域15沿沟槽栅极延伸设置的例子，但接触区域15也可以如图7所示那样形成为点状。在这样的形态下，优选的是，使钨插塞18介于发射极电极16与接触区域15的接合间。
此外，在本实施方式中，说明了在开关元件110的单元区域中一并形成IGBT元件Tr和续流二极管元件Di的RC－IGBT的例子，但也可以将IGBT和续流二极管作为不同的芯片来准备，以相互并联连接的方式构成。
将本发明依据实施例进行了记述，但应理解的是本发明并不限定于该实施例及构造。本发明也包含各种各样的变形例及等价范围内的变形。除此以外，将各种各样的组合及形态，还有在它们中仅包含一要素、其以上或其以下的组合或形态也包含在本发明的范畴或思想范围中。

Claims (4)

1.一种半导体装置，其特征在于，
具备：
多个IGBT元件；以及
与上述多个IGBT元件分别对应的续流二极管(Di)；
上述多个IGBT元件并联地连接而被驱动；
上述多个IGBT元件分别具有：
第1导电型的集电极区域(11)；
第2导电型的漂移区域(10)，层叠于上述集电极区域；
第1导电型的体区域(13)，层叠于上述漂移区域；
沟槽栅极(G1、G2、G3、G4)，将上述体区域贯通而到达上述漂移区域；以及
发射极区域(14)，被上述体区域包围，并且隔着绝缘膜而与上述沟槽栅极接触；
上述多个IGBT元件分别还具有：
有源单元，在有源单元的上述沟槽栅极上被施加栅极电压，并且形成有上述发射极区域；
伪单元，伪单元的上述沟槽栅极被设为与发射极区域相同的电位，并且没有形成上述发射极区域；以及
有源伪单元，在有源伪单元的上述沟槽栅极上被施加栅极电压，并且没有形成上述发射极区域；
上述有源伪单元具有上述体区域被电气地浮置的浮置单元；
相对于上述有源单元和上述有源伪单元的总数，上述浮置单元的数量被设为5％以上且35％以下。
2.如权利要求1所述的半导体装置，其特征在于，
上述漂移区域在与上述体区域相接的区域具有与上述漂移区域的其他区域相比杂质浓度更高的电荷蓄积区域(10b)。
3.如权利要求1或2所述的半导体装置，其特征在于，
上述续流二极管形成在形成有上述IGBT元件的单元区域内。
4.如权利要求1或2所述的半导体装置，其特征在于，
上述续流二极管配置在形成有上述IGBT元件的单元区域的外部。
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