CN108475675B - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN108475675B
CN108475675B CN201680073924.1A CN201680073924A CN108475675B CN 108475675 B CN108475675 B CN 108475675B CN 201680073924 A CN201680073924 A CN 201680073924A CN 108475675 B CN108475675 B CN 108475675B
Authority
CN
China
Prior art keywords
electrode
gate
region
gate electrode
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201680073924.1A
Other languages
English (en)
Other versions
CN108475675A (zh
Inventor
柿本规行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Publication of CN108475675A publication Critical patent/CN108475675A/zh
Application granted granted Critical
Publication of CN108475675B publication Critical patent/CN108475675B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623Buried supplementary region, e.g. buried guard ring
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083Anode or cathode regions of thyristors or gated bipolar-mode devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • H01L29/407Recessed field plates, e.g. trench field plates, buried field plates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • H01L29/7396Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7804Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
    • H01L29/7805Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode in antiparallel, e.g. freewheel diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/868PIN diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/87Thyristor diodes, e.g. Shockley diodes, break-over diodes
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/08Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • H01L29/0696Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/538Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a push-pull configuration

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Conversion In General (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

半导体装置具备:逆导开关元件(10、20),在同一个半导体基板(70、90)上并联形成有二极管元件(12、22)和开关元件(11、21);驱动部(30、40),对形成于上述逆导开关元件的多个栅极电极(82)施加栅极电压;模式判定部(50),判定在正导模式和逆导模式中的哪个模式下驱动,在正导模式下电流主要流过上述开关元件,在逆导模式下电流主要流过上述二极管元件。

Description

半导体装置
相关申请的相互参照
本申请基于2016年1月27日提出的日本专利申请第2016-13713号主张优先权,这里引用其全部内容。
技术领域
本发明涉及设置有开关元件和逆导二极管的半导体装置。
背景技术
如专利文献1所记载那样,在逆导型的绝缘栅双极晶体管(RC-IGBT)中,已知当将IGBT元件区域切换为截止(off)状态且向二极管元件区域流过回流电流时、对绝缘沟槽栅电极施加负电压的半导体装置。
由此,从阳极区域流出的空穴容易沿着绝缘沟槽栅电极被注入到漂移层中,能够减少正向电压下降(以下称作正向电压)。
现有技术文献
专利文献
专利文献1:日本特开2011-238975号公报
发明概要
为了实现专利文献1所记载的动作,需要判定IGBT元件区域和二极管元件区域的哪个处于导通(on)状态,并切换栅极电压的极性。例如在通常的马达驱动用的逆变器(inverter)电路等中,按马达电角度周期来切换栅极电压的极性。IGBT元件区域及二极管元件区域的哪个是导通状态例如能够用输出电流的正负来判定。但是,在如逆变器电路那样输出电流的正负以较短的周期切换的方式下,根据电流传感器的公差,会产生不能精度良好地进行输出电流的正负判定的电流区域。该电流区域是输出电流为零附近的低电流区域。
以往,在不能判定输出电流的正负这样的电流区域中,考虑系统整体的动作的稳定性而假定IGBT元件区域处于导通状态。通常的RC-IGBT中的二极管元件区域为了抑制在栅极电极上被施加电压的栅极干扰而将栅极电极的电位固定在阳极电位,但在根据输出电流的极性而向二极管元件区域施加负电压的方式下无法进行电压的固定。由此,在输出电流的正负不能判定这样的电流区域中,在二极管元件区域的栅极电极上被施加正电压。因此,发明者发现了二极管元件区域的正向电压有可能增大的问题。发明内容
本发明的目的是,提供一种在所有的电流区域中兼顾恢复(recovery)特性的提高和正向电压的减小的半导体装置。
本发明的一技术方案的半导体装置具备:逆导开关元件,在同一个半导体基板上并联形成有二极管元件和开关元件;驱动部,对形成于逆导开关元件的多个栅极电极施加栅极电压;以及模式判定部,判定在正导模式和逆导模式中的哪个模式下驱动,在正导模式下电流主要流过开关元件,在逆导模式下电流主要流过二极管元件。二极管元件具有:第1导电型的第1杂质区域;第2导电型的第2杂质区域,连结于第1杂质区域而形成;第1电极,与第1杂质区域电连接;第2电极,与第2杂质区域电连接;以及第2导电型的第3杂质区域,存在于第1杂质区域,与第2杂质区域分离,并且形成于第1电极与第2电极之间的电流路径;通过对栅极电极施加规定的栅极电压,在被第2杂质区域和第3杂质区域夹着的第1杂质区域中的势垒区域产生反型层。开关元件,具有与二极管元件共用的第1电极及第2电极,并且,通过在栅极电极上被施加规定的栅极电压而成为导通的状态,在第1电极与第2电极之间流过电流。多个栅极电极,具有:第1栅极电极,被输入使开关元件成为导通状态的第1栅极电压;以及第2栅极电极,与第1栅极电压独立地被控制,被输入与第1电极的电位相同、或以第1电极的电位为基准而成为与第1栅极电压的极性相反的极性的第2栅极电压。属于二极管元件的栅极电极至少包括第2栅极电极,属于开关元件的栅极电极至少包括第1栅极电极。基于在第1电极与第2电极之间流过的电流,当模式判定部判定为逆导模式时、或无法判定是逆导模式还是正导模式时,在第2栅极电极上被施加第2栅极电压。
由此,除了在逆导模式下能够减小正向电压以外,在无法判定是逆导模式还是正导模式时,也能够减小二极管元件的正向电压。另外,当无法判定是逆导模式还是正导模式时,即使万一是正导模式,在无法进行模式的判定的电流区域中,也由于IGBT元件的输出电流充分小,所以IGBT元件的集电极-发射极间的饱和电压的增大有限。因而,通过采用本发明,与以往相比,能够减小无法判定是逆导模式还是正导模式时的起因于正向电压的增大的损耗。
附图说明
关于本发明的上述目的及其他目的、特征及优点,一边参照附图一边通过下述详细的记述会变得明确。
图1是表示第1实施方式的逆变器的概略结构的电路图。
图2是沿着图3所示的II-II线的剖面,是表示第1元件或第2元件的详细构造的剖视图。
图3是表示第1元件或第2元件的详细构造的俯视图。
图4是表示驱动部对第1元件或第2元件施加的栅极电压的样式的图。
图5是表示栅极电压的施加定时的时间图。
图6是表示栅极电压的施加定时的时间图。
图7是表示栅极电压的施加定时的时间图。
图8是表示第2实施方式的第1元件或第2元件的详细构造的剖视图。
图9是表示第3实施方式的第1元件或第2元件的详细构造的剖视图。
图10是表示横向二极管的构造的剖视图。
具体实施方式
以下,基于附图说明本发明的实施方式。另外,在以下的各图中,对于相互相同或等同的部分赋予相同的标号。
(第1实施方式)
首先,参照图1对本实施方式的半导体装置的概略结构进行说明。
在本实施方式中,说明将在同一个半导体基板上形成有二极管元件及绝缘栅双极晶体管元件(IGBT元件)的逆导绝缘栅双极晶体管(RC-IGBT)应用到作为半导体装置的逆变器中的方式。
如图1所示,逆变器100具备2个逆导绝缘栅双极晶体管10、20、用来对各逆导绝缘栅双极晶体管10、20的栅极电极施加栅极电压的驱动部30、40、和判定各逆导绝缘栅双极晶体管10、20的驱动状态的模式判定部50。
如图1所示,逆变器100构成为,在电源电压VCC与地电位GND之间串联地连接着2个逆导绝缘栅双极晶体管10、20。在2个逆导绝缘栅双极晶体管10、20的连接点上连接着负载200。在以下的记载中,将2个逆导绝缘栅双极晶体管10、20中的相对于负载200靠电源电压VCC侧的一个称作第1元件10,将地电位GND侧的一个称作第2元件20。即,第1元件10构成逆变器100中的上臂,第2元件20构成下臂。第1元件10及第2元件20相当于逆导开关元件。
第1元件10具有相当于开关元件的IGBT元件11、和二极管元件12。二极管元件12是所谓的续流二极管(freewheeling diode),以从IGBT元件11中的发射极朝向集电极为正向的方式,被并联地连接到IGBT元件11。
第2元件20与第1元件10是等价的,具有IGBT元件21和二极管元件22。二极管元件22以从IGBT元件21的发射极朝向集电极为正向的方式,被并联地连接到IGBT元件21。
第1元件10及第2元件20是双栅极构造的逆导开关元件,具有2种栅极电极。关于第1元件10及第2元件20的详细的元件构造,与图2及图3一起随后详述。
驱动部具有控制向第1元件10的栅极电压的施加的第1驱动部30、和控制向第2元件20的栅极电压的施加的第2驱动部40。第1驱动部30及第2驱动部40的构造是相互等价的。本实施方式的驱动部30、40如图1所示,分别被连接到2个栅极布线,能够向具有双栅极构造的第1元件10及第2元件的各自的栅极电极施加独立的栅极电压。具体而言,对于一方的栅极电极(后述的第1栅极电极82a)能够输入发射极电压Ve和+V1的2值,对于另一方的栅极电极(后述的第2栅极电极82b)能够输入+V1、Ve及-V2的3值。另外,所谓+V1,是以发射极电压Ve为基准的正电压,所谓-V2,是以发射极电压Ve为基准的负电压。
另外,第1栅极电压相当于+V1,第2栅极电压相当于Ve或-V2。
模式判定部50判定第1元件10及第2元件20的动作模式。这里,所谓动作模式,是在绝缘栅双极晶体管中用于区别电流主要流到IGBT元件中、还是电流主要流到二极管元件中的。在以下的记载中,将电流主要流到IGBT元件中而动作的状态称作正导模式,将电流主要流到二极管元件中而动作的状态称作逆导模式。
本实施方式的模式判定部50基于流过负载200的电流的朝向来判定第1元件10及第2元件20的动作模式。逆变器100具备与负载200串联连接的负载电流检测部60。负载电流检测部60是将在负载200中流动的负载电流I连同方向在内来检测的电流计。负载电流检测部60在负载电流I从第1元件10与第2元件20的连接点朝向负载200流动的情况设为正的电流,将相反的情况设为负的电流,向模式判定部50输出。
模式判定部50基于从负载电流检测部60输出的负载电流I的正负来判定动作模式。具体而言,在负载电流I为正的情况下,是电流主要流到第1元件10(上臂)的IGBT元件11及第2元件20(下臂)的二极管元件22中的状态。由此,模式判定部50将第1元件10的动作模式判定为正导模式,将第2元件20的动作模式判定为逆导模式。另一方面,在负载电流I为负的情况下,是电流主要流到第1元件10的二极管元件12及第2元件20的IGBT元件21中的状态。由此,模式判定部50将第1元件10的动作模式判定为逆导模式,将第2元件20的动作模式判定为正导模式。如果负载电流I比模式判定部50能够判定动作模式的电流水平小,则模式判定部50无法判定元件10或元件20的动作模式,但在这样的情况下向驱动部30、40通知不能进行模式判定。
模式判定部50将元件10、20的动作模式、或者不能进行模式判定向驱动部30、40通知。并且,驱动部30、40根据动作模式而向栅极电极施加栅极电压。
接着,参照图2,对第1元件10及第2元件20的详细构造进行说明。另外,由于第1元件10和第2元件20是相互等价的逆导绝缘栅双极晶体管而不将它们区分来进行说明,关于与图1共通的要素,与对第1元件10赋予的标号相互建立对应。此外,在图2中,对半导体基板70中的成为p导电型的杂质扩散层赋予阴影,省略了成为n导电型的杂质扩散层的阴影。
本实施方式的作为逆导开关元件的逆导绝缘栅双极晶体管如图2所示,形成在具有第1主面70a和作为其背面的第2主面70b的半导体基板70上。起到作为开关元件的功能的IGBT元件11和起到作为二极管的功能的二极管元件12分别形成在同一个半导体基板70上。
在第1主面70a,形成有例如由铝构成的阴极电极71。阴极电极71相当于二极管元件12的阴极端子或IGBT元件11的集电极端子,阴极电极71兼用作它们。此外,阴极电极71相当于第1电极。
此外,如图2所示,在半导体基板70的第1主面70a的表层,以与阴极电极71接触的方式形成有n导电型的阴极区域72a。此外,在与阴极区域72a同一层中形成有p导电型的集电极区域72b。集电极区域72b与阴极电极71接触并与阴极区域72a邻接。在IGBT元件11与二极管元件12的边界附近,二极管元件12能够作为IGBT11发挥作用。此外,IGBT元件11能够作为二极管元件12发挥作用。在本实施方式中,在功能上,将IGBT元件11和二极管元件12混合存在的区域称作混合区域,将阴极区域72a与集电极区域72b的界面称作二极管部12与IGBT部11的边界。阴极区域72a相当于第1杂质区域的一部分。
在阴极区域72a上层叠有n导电型的第1漂移区域73a,在集电极区域72b上层叠有n导电型的第2漂移区域73b。为了方便而将第1漂移区域73a及第2漂移区域73b的名称区分,但这些区域73a、73b实质上是由同一个杂质扩散层构成的连续的区域。第1漂移区域73a相当于第1杂质区域的一部分。
在第1漂移区域73a上层叠有p导电型的第1副阳极74a,在第2漂移区域73b上层叠有p导电型的第2副阳极74b。为了方便而将第1副阳极74a及第2副阳极74b的名称区分,但这些副阳极74a、74b实质上是由同一个杂质扩散层构成的连续的区域。另外,第1副阳极区域74a及第2副阳极区域74b相当于第3杂质区域。
在第1副阳极74a上层叠有n导电型的第1势垒(barrier)区域75a,在第2副阳极74b上层叠有n导电型的第2势垒区域75b。为了方便而将第1势垒区域75a及第2势垒区域75b的名称区分,但这些势垒区域75a、75b实质上是由同一个杂质扩散层构成的连续的区域。第1势垒区域75a相当于第1杂质区域的一部分。
在第1势垒区域75a上层叠有p导电型的阳极区域76a,在第2势垒区域75b上层叠有p导电型的体区域(body region)76b。为了方便而将阳极区域76a及体区域76b的名称区分,但本实施方式的这些区域76a、76b实质上是由同一个杂质扩散层构成的连续的区域。另外,阳极区域76a相当于第2杂质区域。
另外,所谓第1杂质区域,是包括阴极区域72a、第1漂移区域73a、第1势垒区域75a在内的n导电型的区域。并且,二极管元件12成为第1副阳极74a从作为第2杂质区域的阳极区域76a离开并被埋入在第1杂质区域内的构造。第1副阳极74a形成于在第1漂移区域73a与阳极区域76a之间流动的电流的电流路径。
在二极管元件12中,通过形成有上述的第1副阳极74a及第1势垒区域75a,从阳极区域76a向第1漂移区域73a的空穴的注入被抑制,施加在二极管元件12上的电压从正偏压切换为反偏压时的反向电流被限制。因此,与没有形成第1副阳极74a及第1势垒区域75a的二极管相比,能够使反向恢复电流变小从而能够使恢复特性提高。但是,由于由第1副阳极74a及第1势垒区域75a形成的pn结阻碍二极管元件12的正向电流的流动,所以正向电压VF变大。
此外,在第2主面70b的表层,以被体区域76b包围的方式形成有n导电型的发射极区域77。并且,以与发射极区域77、体区域76b及阳极区域76a接触的方式,在第2主面70b上形成有阳极电极78。阳极电极78相当于二极管元件12的阳极端子或IGBT元件11的发射极端子。此外,阳极电极78相当于第2电极。
如图2所示,IGBT元件11中,作为杂质扩散层而具有集电极区域72b、第2漂移区域73b、第2副阳极74b、第2势垒区域75b、体区域76b及发射极区域77。另一方面,二极管元件12中,作为杂质扩散层而具有阴极区域72a、第1漂移区域73a、第1副阳极74a、第1势垒区域75a及阳极区域76a。
根据IGBT元件11及二极管元件12的电气特性的要求,实质上位于同一层中的各杂质扩散层不妨碍使对应的区域的杂质浓度成为相互不同的浓度,这些区域的杂质浓度应被适当地设定。
进而,该逆导绝缘栅双极晶体管具有从第2主面70b向半导体基板70的厚度方向形成、并达到漂移区域73a、73b的沟槽栅80。沟槽栅80在IGBT元件11中将体区域76b、第2势垒区域75b、第2副阳极74b贯通而达到第2漂移区域73b,在二极管元件12中将阳极区域76a、第1势垒区域75a、第1副阳极74a贯通而达到第1漂移区域73a。
沟槽栅80包括绝缘膜81和导电性的栅极电极82,绝缘膜81成膜在以从第2主面70b向半导体基板70的厚度方向延伸而达到漂移区域73a、73b的方式被挖掘出的沟槽的内表面,栅极电极82以将沟槽填埋的方式形成。栅极电极82和发射极电极78由于隔着绝缘膜81而相互绝缘。此外,形成于IGBT元件11的发射极区域77被形成为与沟槽栅80相接,如果在栅极电极82上施加比阳极电极78高的电压,则在体区域76b及第2副阳极74b中形成沟道,在阳极电极78与阴极电极71之间,由于IGBT动作而流过输出电流。
本实施方式的多个栅极电极82被分类为第1栅极电极82a和第2栅极电极82b这2个栅极电极。第1栅极电极82a连接于第1栅极焊盘G1。第2栅极电极82b连接于第2栅极焊盘G2。在第1栅极电极82a和第2栅极电极82b分别被施加独立的电压。如图1所示,第1驱动部30向第1元件11的第1栅极电极82a及第2栅极电极82b供给电压。同样,第2驱动部40向第2元件21的第1栅极电极82a及第2栅极电极82b供给电压。
此外,p导电型的阳极区域76a及体区域76b、n导电型的第1、第2势垒区域75a、75b、和p导电型的第1、第2副阳极74a、74b形成了pnp型的寄生晶体管。n导电型的势垒区域75a、75b对于空穴而言,对于p导电型的区域成为势垒,但能够通过施加在栅极电极82上的电压(栅极电压)来控制其势垒高度。
如已经说明的那样,特别是对第2栅极电极82b,能够施加比阳极电极78(相当于第2电极,在IGBT中被称作发射极电极)的电压低V2的电压。即,能够使第2栅极电极82b的电位相对于阳极电极78成为负电位。由此,能够使势垒高度变动,以使势垒区域75a、75b的势垒消失。由此,二极管元件11可以看作第1势垒区域75a反型而阳极区域76a、第1势垒区域75a及第1副阳极74a为一体的p导电型的区域。即,二极管元件12成为简单的pn结二极管,与形成有第1副阳极74a的二极管相比,能够减小正向电压VF。
在本实施方式中,栅极电压V2被设定为至少能够使第1势垒区域75a产生沟道的值。换言之,电压V2被设定为在二极管元件12中由阳极区域76a、第1势垒区域75a和第1副阳极74a形成的寄生晶体管的阈值电压Vth以上。另一方面,栅极电压V1被设定为在IGBT元件11中能够使体区域76b产生沟道的值。换言之,栅极电压V1被设定为能够使作为开关元件的IGBT成为导通的状态的电压。
另外,本实施方式的n导电型相当于第1导电型,p导电型相当于第2导电型。导电型的关系性也可以相互相反。在此情况下,阳极和阴极的关系也为相反。
接着,参照图3,对本实施方式的第1元件10及第2元件20的平面布局进行说明。另外,第1元件10和第2元件20由于是相互等价的逆导绝缘栅双极晶体管,所以不进行它们的区别而进行说明。此外,关于标号,与图1及图2共通的要素和对第1元件10赋予的标号相互建立对应。沿着图3中的II-II线的剖面相当于图2。
如图3所示,本实施方式的绝缘栅双极晶体管其栅极电极82被形成为条状。将栅极焊盘G1、G2与栅极电极82相互电连接的栅极布线83在形成有IGBT元件11或二极管元件12的元件区域上沿着栅极电极82的延伸方向形成。栅极布线83包括将第1栅极焊盘G1与第1栅极电极82a连接的第1栅极布线83a、和将第2栅极焊盘G2与第2栅极电极82b连接的第2栅极布线83b。
如上述那样,对于第1栅极电极82a,能够施加阳极电极78(即发射极电极)的电位Ve、以及以Ve为基准的正电压+V1。此外,对于第2栅极电极82b,能够施加Ve、+V1、以及以Ve为基准的负电压-V2。
在该绝缘栅双极晶体管中,在IGBT元件11的栅极电极82中包括第1栅极电极82a和第2栅极电极82b两者。并且,对于二极管元件12的栅极电极82,仅分配了第2栅极电极82b。即,IGBT元件11至少能够被施加使IGBT成为导通状态的栅极电压V1,并且能够与栅极电压V1的施加独立地被施加栅极电压-V2。此外,二极管元件12至少能够被施加栅极电压-V2。
此外,如图3所示,在IGBT元件11与二极管元件12的边界附近的区域即混合区域,被分配了第2栅极电极82b。即,在混合区域,能够施加+V1和-V2两者。
另外,在形成有IGBT元件11的区域,优选的是,如图3所示,在与栅极布线83的延伸方向正交的方向上,交替地配置有第1栅极电极82a和第2栅极电极82b。当然,也可以将同种的栅极电极82以相互相邻的方式配置,但通过将第1栅极电极82a和第2栅极电极82b交替地配置,使后面详述的与关断(turn off)有关的开关速度变快的效果能够更大。此外,由于能够使发热源分散,所以在热方面是有利的。
此外,关于栅极电极82,并不一定全部的栅极电极82都需要属于第1栅极电极82a或第2栅极电极82b,也可以做成使一些栅极电极82与阳极电极78短路的间隔剔除构造。由于与阳极电极78短路的栅极电极82的电位被固定为阳极电压(相当于发射极电压),所以作为元件10、20整体能够使栅极电容变小。由此,能够抑制为了将元件10、20驱动所需要的驱动部30、40的驱动能力。
接着,参照图4,对本实施方式的半导体装置、特别是第1元件10及第2元件20的动作及作用效果进行说明。图4是将施加在第1栅极电极82a及第2栅极电极82b上的栅极电压与第1元件10或第2元件20的动作模式对应而图示的图。由于第1元件10和第2元件20相互是等价的,所以只要没有特别声明,就对第1元件10进行说明。
在元件10的状态中,有图4所示的A~D的状态。状态A是负载电流I充分大、能够判定是以正导模式动作中的状态。状态B是虽然实际为正导模式但负载电流I比能够判定动作模式的水平小、模式判定部50不能判定是正导模式还是逆导模式的状态。状态C是虽然实际是逆导模式但负载电流I比能够判定动作模式的水平小、不能判定是正导模式还是逆导模式的状态。状态D是负载电流I充分大、能够判定是以逆导模式动作中的状态。
在状态A下,驱动部30向第1栅极电极82a和第2栅极电极82b两者施加电压+V1。状态A下,元件10在正导模式下处于驱动中,可以期待作为IGBT的功能。由此,通过对属于形成有IGBT元件11的区域的第1栅极电极82a和第2栅极电极82b两者施加电压+V1,能够使得作为IGBT进行动作。另一方面,对属于形成有二极管元件12的区域的第2栅极电极82b也施加+V1。在本实施方式中,属于二极管元件12的栅极电极82都是第2栅极电极82b,对与IGBT元件11的边界附近即混合区域也施加+V1。由此,能够使混合区域作为IGBT发挥功能。
在状态B及状态C下,驱动部30对第1栅极电极82a施加电压+V1,并对第2栅极电极82b施加电压-V2。状态B及状态C是不能由模式判定部50判定元件10是以哪个动作模式动作中的电流区域。假如元件10是正导模式(状态B),则由于在属于IGBT元件11的第1栅极电极82a上被施加了电压+V1,所以能够作为IGBT正确地动作。此外,由于在属于IGBT元件11的第2栅极电极82b上被施加电压-V2,所以在IGBT元件11关断时,成为空穴容易向体区域76b流入的状态。即,第2漂移区域73b存在的空穴容易向体区域76b移动,能够使与关断有关的开关速度变快。
另一方面,即使假如元件10是逆导模式(状态C),也由于在属于二极管元件12的第2栅极电极82b上被施加电压-V2,所以能够起到减小正向电压VF的效果。此外,如上述那样,为了使IGBT元件11作为IGBT动作而在第1栅极电极82a上施加了电压+V1,但在IGBT元件11与二极管元件12的边界附近即混合区域,也通过第2栅极电极82b而施加了电压-V2,所以能够抑制因在第1栅极电极82a上施加电压+V1造成的栅极干扰。即,能够使二极管元件12可靠地作为二极管发挥功能。
在状态D下,驱动部30对第1栅极电极82b施加发射极电压Ve,并对第2栅极电极82b施加电压-V2。在状态D下,元件10在逆导模式下处于驱动中,可期待作为二极管的功能。由此,通过对属于形成有二极管元件12的区域的第2栅极电极82b施加电压-V2,能够起到减小正向电压VF的效果。另一方面,在第1栅极电极82a上被施加发射极电压Ve。因此,与第1栅极电极82a被施加以发射极电压Ve为基准的负电压的情况相比,施加负电压的功能仅为第2栅极电极82b侧就可以,能够使电路规模变小。
接着,参照图5~图7,关于向第2栅极电极82b施加栅极电压-V2的具体的定时,以3种例子进行说明。另外,图5~图7中的负载电流I是与图1所示的负载电流I同义的,关于负载电流I,以从第1元件10与第2元件20的连接点朝向负载200流动的情况为正的电流。此外,对第1栅极电极82a施加的栅极电压用来使IGBT元件11作为IGBT进行开关动作,同步于PWM基准信号而反复成为高电平和低电平。
<同步于PWM基准信号的实施例>
如图5所示,在该例中,对第2栅极电极82b施加的栅极电压也与第1栅极电极82a同样地同步于PWM基准信号而被施加。PWM基准信号的High(高)/Low(低)在与构成上臂的第1元件10对应的情况和与构成下臂的第2元件20对应的情况间成为相互反转的关系。在PWM基准信号为High的期间,图4所示的栅极电压为有效,在PWM基准信号为Low的期间,发射极电压Ve作为栅极电压被向各栅极电极82输入。
在时刻t1~时刻t2,模式判定部50判定为第1元件10是正导模式、第2元件20是逆导模式。因而,第1元件10以状态A动作。即,同步于PWM基准信号,高电平被设为+V1而低电平被设为Ve的被进行了PWM控制的栅极电压被施加于第1栅极电极82a和第2栅极电极82b两者。另一方面,第2元件20以状态D动作。即,在第1栅极电极82a上,始终施加发射极电压Ve,在第2栅极电极82b上,施加高电平被设为Ve而低电平被设为-V2的被进行了PWM控制的栅极电压。
在时刻t2~时刻t3,模式判定部50不能判定第1元件10及第2元件20的动作模式。因而,第1元件10及第2元件20以状态B或状态C动作。即,第1栅极电极82a被施加高电平被设为+V1而低电平被设为Ve的被进行了PWM控制的栅极电压。第2栅极电极82b被施加高电平被设为Ve而低电平被设为-V2的被进行了PWM控制的栅极电压。
在时刻t3~时刻t4,模式判定部50判定为第1元件10是逆导模式、第2元件20是正导模式。因而,第1元件10以状态D动作,第2元件20以状态A动作。栅极电压处于与时刻t1~时刻t2的第1元件10与第2元件20的关系相反的关系。
在时刻t4~时刻t5,模式判定部50不能判定第1元件10及第2元件20的动作模式。因而,第1元件10及第2元件20以状态B或状态C动作。即,栅极电压与时刻t2~时刻t3同样地变化。
在该例中,在状态C或状态D的逆导模式下,由于向二极管元件12施加相对于发射极电压Ve为负的电压-V2,所以能够减小正向电压VF。除此以外,如通常的驱动电路所实施的那样,为了使向第1元件10输入的PWM基准信号和向第2元件20输入的PWM基准信号不同时成为High而设定有一定时间的双方成为Low的死区时间(dead time),从而能够使在逆导绝缘栅双极晶体管的恢复期间中向二极管元件12施加的栅极电压成为Ve,所以与始终施加-V2的状态相比能够减小恢复损耗。
<始终被施加负电压的实施例>
如图6所示,在该例中,当在状态B~D下向第2栅极电极82b施加的栅极电压是-V2时,不论PWM基准信号如何都始终施加电压-V2。在该例中,也由于向二极管元件12施加相对于发射极电压Ve为负的电压-V2,所以能够减小正向电压VF。此外,在IGBT元件11中能够得到空穴容易向体区域76b流入的状况,能够使与关断有关的开关速度变快。但是,与上述的同步于PWM基准信号的动作相比,优选的是将V2的大小设定得较小。这是因为,如果过量地设定V2的大小,则在由逆导带来的二极管电流较大的状态下,二极管元件12的恢复损耗变大。在如该例那样不论PWM基准信号如何都始终施加电压-V2的方式中,虽然由正向电压VF导致的损耗的降低效果较高,但恢复损耗也有可能增大,所以对于由正向电压VF导致的损耗在系统整体的驱动损耗中所占的比例较大的系统是有效的。
<依赖于二极管电流的大小而施加负电压的例子>
在不论PWM基准信号如何都始终施加电压-V2的方式中,如上述那样,在二极管电流较大的情况下恢复损耗有可能增大。为了解决该问题,在该例中,如图7所示,对二极管电流、以及负载电流I设置阈值。在负载电流I的大小比阈值小的情况下在第2栅极电极82b上施加电压-V2,在负载电流I的大小为阈值以上的情况下在第2栅极电极82b上施加电压Ve。由此,能够减小二极管电流较大的情况下的恢复损耗。
(第2实施方式)
除了在第1实施方式中说明的作为第1元件10、第2元件20的逆导绝缘栅双极晶体管以外,优选的是,如图8所示那样,具有n导电型的柱区域79。柱区域79形成为,从半导体基板70的第2主面70b沿厚度方向延伸,将阳极区域76a或体区域76b贯通而达到第1势垒区域75a、第2势垒区域75b。柱区域79是掺杂有与第1、第2势垒区域75a、75b相同导电型的杂质的扩散层,柱区域79和势垒区域75a、75b是大致相同电位。
通过具有柱区域79,当在阳极电极78与阴极电极71之间施加了正偏压,则阳极电极78和柱区域79通过金属-半导体结面而短路。由于柱区域79和第1势垒区域75a是大致相同电位,所以第1势垒区域75a与阳极电极78的电位差大致等于金属-半导体结面处的电压降。由于金属-半导体结面处的电压降小于阳极区域76a与第1势垒区域75a之间的pn结的内建电压,所以从阳极区域76a向第1漂移区域73a的空穴的注入被抑制。
当阳极电极78与阴极电极71之间的电压从正偏压切换为反偏压,则在二极管元件12中,在正偏压的施加时从阳极区域76a向第1漂移区域73a的空穴的注入被抑制,所以恢复电流较小,恢复时间较短。
此外,在该二极管元件12中,当在阳极电极78与阴极电极71之间施加反偏压,则通过从第1副阳极74a与第1漂移区域73a之间的pn结的界面延伸的耗尽层而确保耐压(withstand voltage)。即,根据该二极管元件12,能够提高对于反偏压的耐压。
另外,在本实施方式中表示了IGBT元件11也形成有柱区域79的例子,但只要至少形成于二极管元件12就能够起到空穴注入抑制效果。因此,并不一定需要在IGBT元件11中形成柱区域79。
(第3实施方式)
关于在第1实施方式中参照图3对平面布局说明过的间隔剔除构造,在本实施方式中具体地说明。在本实施方式中,如在第2实施方式中说明的那样,具备柱区域79,如图9所示,在二极管元件12中,相互相邻的栅极电极82不与阳极电极78短路。换言之,与阳极电极78短路的栅极电极82所邻接的栅极电极82被分配为第2栅极电极82b。由此,形成在二极管元件12中的第1势垒区域75a隔着绝缘膜81而与至少一个第2栅极电极82b相接,所以二极管元件12能够起到因在第2栅极电极82b上施加负电压-V2带来的正向电压VF的降低效果。此外,还能够起到由间隔剔除构造带来的栅极电容的降低效果。
另外,在本实施方式中,对逆导绝缘栅双极晶体管具有柱区域79的结构进行了说明,但关于如第1实施方式那样不具有柱区域79的构造也是同样的。
(其他实施方式)
以上,对本发明的优选的实施方式进行了说明,但本发明不受上述的实施方式限制,在不脱离本发明的主旨的范围中能够各种各样地变形而实施。
在上述的各实施方式中,以具有沟槽栅80的纵向的绝缘栅双极晶体管为例进行了说明,但并不一定需要是具有沟槽型的栅极电极82的构造,也不一定需要是纵向。如图10所示,关于横向元件也能够应用本发明。具有势垒区域和栅极电极的二极管如图10所示,在n导电型的半导体基板90的一面90a的表层,形成有p导电型的阳极区域91。并且,以将阳极区域91包围的方式,n导电型的势垒区域92在一面90a露出一部分而形成。进而,夹着势垒区域92而在阳极区域91的相反侧形成有副阳极93。在阳极区域91,在一面90a上连结着金属制的阳极电极94。此外,在没有形成阳极区域91、势垒区域92及副阳极93的半导体基板90的一面90a,连结着阴极电极95。
二极管电流在阳极电极94与阴极电极95之间流动。在该例中,连结着阴极电极95的n导电型的半导体基板相当于第1杂质区域,连结着阳极电极94的阳极区域91相当于第2杂质区域。即,二极管电流在阴极电极95附近的半导体基板与阳极区域91之间流动,副阳极93和势垒区域92位于电流路径中。该横向的二极管还在势垒区域92露出的一面90a上隔着绝缘膜96形成有栅极电极97。与在第1实施方式中说明的纵向的二极管元件12同样,即使是横向的二极管,也能够通过具有势垒区域92而使恢复特性提高,通过向栅极电极97施加相对于阳极区域91的电位为负的电压,能够减小正向电压VF。由此,与第1实施方式同样,在模式判定部50不能判定是正导模式还是逆导模式的情况下,通过对栅极电极97施加负的电压,能够起到与第1实施方式同样的效果。
此外,在上述的各实施方式中,还能够限于在输入负电压-V2的定时施加发射极电压Ve。在此情况下,虽然由负电压施加带来的正向电压VF的降低效果较小,但在二极管元件12上不会被施加电压+V1,所以能够抑制起因于被施加+V1的二极管特性的恶化、特别是正向电压VF的增加。
此外,在上述的各实施方式中,对采用IGBT元件11作为与二极管元件12并联的开关元件的例子进行了说明,但开关元件例如也可以是MOSFET。在MOSFET的情况下,图2、图8及图9所示的开关元件区域(在上述的各实施方式中是IGBT元件11)的集电极区域72b成为n导电型的漏极区域,成为兼作开关元件和二极管元件的区域。即,也可以不将开关元件区域和二极管元件12区分制作。另外,图2、图8及图9所示的发射极区域77成为源极区域。在这样的方式中,实质上处于作为开关元件发挥功能的区域和作为二极管发挥功能的区域并联地形成的状态。
此外,在上述的各实施方式中,对栅极电极82形成为条状的例子进行了说明,但只要至少分为第1栅极电极82a和第2栅极电极82b,也可以是任意形状,例如也可以形成为格状。
此外,在逆导开关元件中的IGBT元件11、21侧,并不一定需要形成势垒区域92及副阳极93,可以是,在二极管元件12、22侧,副阳极93不是全面地而是部分地形成。
此外,在上述的各实施方式中,对IGBT元件11、21中的第1电极及第2电极、和二极管元件21、22中的第1电极及第2电极在元件内分别与共通的栅极焊盘G1、G2连接的例子进行了说明。但是,各个电极也可以在元件外连接,与二极管元件共用的第1电极及第2电极这一表现,也包括第1元件10或第2元件20外部的连接。
进而,在上述的各实施方式中,对在开关元件区域和二极管元件中共用地形成第1电极71的例子进行了说明,但也可以将IGBT元件11、21中的集电极电极、和二极管元件21、22中的阴极电极分别分体地形成,也包括各个电极在第1元件10或第2元件20外部被连接的情况。
此外,在上述的各实施方式中,对在开关元件区域和二极管元件中共用地形成第2电极78的例子进行了说明,但也可以将IGBT元件11、21中的发射极电极、和二极管元件21、22中的阳极电极分别分体地形成,也包括各个电极在第1元件10或第2元件20外部被连接的情况。
将本发明依据实施例进行了记述,但应理解的是本发明并不限定于该实施例或构造。本发明也包含各种各样的变形例或等价范围内的变形。除此以外,各种各样的组合或形态、进而在它们中仅包含一要素、其以上或其以下的其他组合或形态也包含在本发明的范畴或思想范围中。

Claims (10)

1.一种半导体装置,其特征在于,
具备:
逆导开关元件(10、20),在同一个半导体基板(70、90)上并联形成有二极管元件(12、22)和开关元件(11、21);
驱动部(30、40),对形成于上述逆导开关元件的多个栅极电极(82)施加栅极电压;以及
模式判定部(50),判定在正导模式和逆导模式中的哪个模式下驱动,在上述正导模式下电流主要流过上述开关元件,在上述逆导模式下电流主要流过上述二极管元件;
上述二极管元件具有:
第1导电型的第1杂质区域(72a、73a、75a);
第2导电型的第2杂质区域(76a、91),连结于上述第1杂质区域而形成;
第1电极(71、95),与上述第1杂质区域电连接;
第2电极(78、94),与上述第2杂质区域电连接;
通过对上述栅极电极施加规定的栅极电压,在上述第1杂质区域产生反型层;
上述开关元件,具有与上述二极管元件共用的上述第1电极及上述第2电极,并且,通过在上述栅极电极上被施加规定的栅极电压而成为导通的状态,在上述第1电极与上述第2电极之间流过电流;
上述多个栅极电极,具有:
第1栅极电极(82a),被输入使上述开关元件成为导通状态的第1栅极电压;以及
第2栅极电极(82b),与上述第1栅极电压独立地被控制,被输入与上述第2电极的电位相同、或以上述第2电极的电位为基准而成为与上述第1栅极电压的极性相反的极性的第2栅极电压;
属于上述二极管元件的上述栅极电极至少包括上述第2栅极电极,属于上述开关元件的上述栅极电极至少包括上述第1栅极电极;
基于在上述第1电极与上述第2电极之间流过的电流,当上述模式判定部判定为上述逆导模式时、或无法判定是上述逆导模式还是上述正导模式时,在上述第2栅极电极上被施加上述第2栅极电压。
2.如权利要求1所述的半导体装置,其特征在于,
上述二极管元件中的上述第1杂质区域,在与上述第2杂质区域 邻接的位置具有第1导电型的势垒区域(75a,92);
通过对上述栅极电极施加上述规定的栅极电压,在上述势垒区域产生反型层。
3.如权利要求1所述的半导体装置,其特征在于,
上述二极管还具有第2导电型的第3杂质区域(74a、93),该第3杂质区域存在于上述第1杂质区域并与上述第2杂质区域分离,并且该第3杂质区域形成于上述第1电极与上述第2电极之间的电流路径。
4.如权利要求1所述的半导体装置,其特征在于,
上述驱动部,当判定为上述逆导模式时、或无法判定是上述逆导模式还是上述正导模式时,将至少具有高电平和低电平这2值且被进行了PWM控制的栅极电压向上述第2栅极电极施加;
上述低电平是以上述第2电极的电位为基准而与上述第1栅极电压的极性相反的极性。
5.如权利要求1所述的半导体装置,其特征在于,
上述驱动部,当判定为上述逆导模式时、或无法判定是上述逆导模式还是上述正导模式时,始终将以上述第2电极的电位为基准而与上述第1栅极电压的极性相反的极性的栅极电压向上述第2栅极电极施加。
6.如权利要求1所述的半导体装置,其特征在于,
上述驱动部,当判定为上述逆导模式时,在流过上述第1电极与上述第2电极之间的二极管电流的大小是规定的阈值以上的情况下,将与上述第2电极的电位相同的栅极电压向上述第2栅极电极施加;
上述驱动部,在上述二极管电流的大小比规定的阈值小的情况下,将以上述第2电极的电位为基准而与上述第1栅极电压的极性相反的极性的栅极电压向上述第2栅极电极施加。
7.如权利要求1所述的半导体装置,其特征在于,
成为形成上述二极管元件的区域与形成上述开关元件的区域的边界的混合区域中的上述栅极电极,能够施加以上述第2电极的电位为基准而与上述第1栅极电压的极性相反的极性的栅极电压。
8.如权利要求1所述的半导体装置,其特征在于,
成为形成上述二极管元件的区域与形成上述开关元件的区域的边界的混合区域中的上述栅极电极,能够施加上述第1栅极电压。
9.如权利要求1所述的半导体装置,其特征在于,
属于上述开关元件的上述栅极电极包括上述第2栅极电极。
10.如权利要求1~9中任一项所述的半导体装置,其特征在于,
上述驱动部,在判定为上述逆导模式时,使被施加在上述第1栅极电极上的栅极电压与上述第2电极的电位相同。
CN201680073924.1A 2016-01-27 2016-12-16 半导体装置 Active CN108475675B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2016013713A JP6414090B2 (ja) 2016-01-27 2016-01-27 半導体装置
JP2016-013713 2016-01-27
PCT/JP2016/087505 WO2017130597A1 (ja) 2016-01-27 2016-12-16 半導体装置

Publications (2)

Publication Number Publication Date
CN108475675A CN108475675A (zh) 2018-08-31
CN108475675B true CN108475675B (zh) 2022-03-15

Family

ID=59398955

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201680073924.1A Active CN108475675B (zh) 2016-01-27 2016-12-16 半导体装置

Country Status (4)

Country Link
US (1) US10438852B2 (zh)
JP (1) JP6414090B2 (zh)
CN (1) CN108475675B (zh)
WO (1) WO2017130597A1 (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019017104A1 (ja) * 2017-07-18 2019-01-24 富士電機株式会社 半導体装置
JP7095303B2 (ja) 2018-02-14 2022-07-05 富士電機株式会社 半導体装置
WO2019159657A1 (ja) 2018-02-14 2019-08-22 富士電機株式会社 半導体装置
WO2019159391A1 (ja) 2018-02-14 2019-08-22 富士電機株式会社 半導体装置
JP7002431B2 (ja) * 2018-10-09 2022-01-20 三菱電機株式会社 半導体装置
JP2020109901A (ja) * 2019-01-04 2020-07-16 株式会社東芝 制御回路、半導体装置及び電気回路装置
JP7353891B2 (ja) * 2019-09-20 2023-10-02 株式会社東芝 半導体装置及び半導体回路
JP7456113B2 (ja) 2019-10-11 2024-03-27 富士電機株式会社 半導体装置
JP7352437B2 (ja) 2019-10-25 2023-09-28 株式会社東芝 半導体装置
JP7352443B2 (ja) * 2019-11-01 2023-09-28 株式会社東芝 半導体装置の制御方法
JP7319601B2 (ja) 2019-11-01 2023-08-02 株式会社東芝 半導体装置
JP7302469B2 (ja) * 2019-12-24 2023-07-04 株式会社デンソー 半導体装置
JP7233387B2 (ja) * 2020-01-24 2023-03-06 三菱電機株式会社 半導体モジュール
JP7335190B2 (ja) 2020-03-23 2023-08-29 株式会社東芝 半導体装置
JP7456902B2 (ja) * 2020-09-17 2024-03-27 株式会社東芝 半導体装置
JP7490604B2 (ja) 2021-03-22 2024-05-27 株式会社東芝 半導体装置
DE102022107009A1 (de) 2022-03-24 2023-09-28 Infineon Technologies Ag Dual-gate-leistungshalbleitervorrichtung und verfahren zum steuern einer dual-gateleistungshalbleitervorrichtung
CN116504822B (zh) * 2023-05-29 2024-02-09 上海林众电子科技有限公司 基于沟槽栅的逆导型igbt

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008072848A (ja) * 2006-09-14 2008-03-27 Mitsubishi Electric Corp 半導体装置
CN104576718A (zh) * 2013-10-22 2015-04-29 Abb技术有限公司 具有续流SiC二极管的RC-IGBT
CN104835841A (zh) * 2015-05-08 2015-08-12 邓华鲜 Igbt芯片的结构

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5828112A (en) * 1995-09-18 1998-10-27 Kabushiki Kaisha Toshiba Semiconductor device incorporating an output element having a current-detecting section
JP4765252B2 (ja) * 2004-01-13 2011-09-07 株式会社豊田自動織機 温度検出機能付き半導体装置
JP4380726B2 (ja) * 2007-04-25 2009-12-09 株式会社デンソー ブリッジ回路における縦型mosfet制御方法
DE102008045410B4 (de) * 2007-09-05 2019-07-11 Denso Corporation Halbleitervorrichtung mit IGBT mit eingebauter Diode und Halbleitervorrichtung mit DMOS mit eingebauter Diode
JP4240140B1 (ja) * 2007-09-10 2009-03-18 トヨタ自動車株式会社 給電装置とその駆動方法
JP4840370B2 (ja) 2008-01-16 2011-12-21 トヨタ自動車株式会社 半導体装置とその半導体装置を備えている給電装置の駆動方法
CN101946324B (zh) * 2008-02-14 2013-02-27 丰田自动车株式会社 反向导通半导体元件的驱动方法和半导体装置以及供电装置
JP4952638B2 (ja) * 2008-04-07 2012-06-13 トヨタ自動車株式会社 半導体素子と半導体装置とその駆動方法
JP2010263149A (ja) 2009-05-11 2010-11-18 Toyota Motor Corp 半導体装置
JP5858914B2 (ja) * 2010-08-04 2016-02-10 ローム株式会社 パワーモジュールおよび出力回路
JP2013026534A (ja) 2011-07-25 2013-02-04 Toyota Central R&D Labs Inc 半導体装置
JP4947230B2 (ja) * 2011-08-29 2012-06-06 トヨタ自動車株式会社 半導体装置
JP5742672B2 (ja) 2011-11-02 2015-07-01 株式会社デンソー 半導体装置
JP6064371B2 (ja) 2012-05-30 2017-01-25 株式会社デンソー 半導体装置
JP5942737B2 (ja) * 2012-09-24 2016-06-29 株式会社デンソー 半導体装置
JP2014073055A (ja) * 2012-10-01 2014-04-21 Denso Corp 電子回路
JP5949646B2 (ja) 2013-04-10 2016-07-13 株式会社デンソー 半導体装置
JP6056984B2 (ja) * 2013-11-05 2017-01-11 トヨタ自動車株式会社 半導体装置
JP6459791B2 (ja) 2014-07-14 2019-01-30 株式会社デンソー 半導体装置およびその製造方法
JP2016092163A (ja) 2014-11-03 2016-05-23 株式会社デンソー 半導体装置
JP6350298B2 (ja) 2015-01-21 2018-07-04 株式会社デンソー 半導体装置
JP6439460B2 (ja) 2015-01-23 2018-12-19 株式会社デンソー 駆動装置
JP6246415B2 (ja) * 2015-09-03 2017-12-13 三菱電機株式会社 電力変換装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008072848A (ja) * 2006-09-14 2008-03-27 Mitsubishi Electric Corp 半導体装置
CN104576718A (zh) * 2013-10-22 2015-04-29 Abb技术有限公司 具有续流SiC二极管的RC-IGBT
CN104835841A (zh) * 2015-05-08 2015-08-12 邓华鲜 Igbt芯片的结构

Also Published As

Publication number Publication date
JP6414090B2 (ja) 2018-10-31
WO2017130597A1 (ja) 2017-08-03
JP2017135255A (ja) 2017-08-03
US20180308757A1 (en) 2018-10-25
CN108475675A (zh) 2018-08-31
US10438852B2 (en) 2019-10-08

Similar Documents

Publication Publication Date Title
CN108475675B (zh) 半导体装置
JP6652173B2 (ja) 半導体装置
US9515067B2 (en) Semiconductor device having switching element and free wheel diode and method for controlling the same
US8604544B2 (en) Semiconductor device
US9276137B2 (en) Diode and semiconductor device including built-in diode
JP6117640B2 (ja) 半導体装置及び駆動システム
JP6053050B2 (ja) 逆導通igbt
JP5229288B2 (ja) 半導体装置およびその制御方法
JP2007214541A (ja) 半導体装置
JP6658021B2 (ja) 半導体装置
JP5488256B2 (ja) 電力用半導体装置
US20120319739A1 (en) Semiconductor device supplying charging current to element to be charged
JP2004296831A (ja) 半導体装置
CN109478564B (zh) 半导体装置
US20150287715A1 (en) Switching element and a diode being connected to a power source and an inductive load
US20080203535A1 (en) Semiconductor device
WO2016132417A1 (ja) 半導体集積回路
JP2015181178A (ja) 半導体装置
CN106663658B (zh) 半导体集成电路
JP3491049B2 (ja) 整流素子およびその駆動方法
CN111668212A (zh) 半导体装置
JP7407757B2 (ja) 半導体装置
KR20060124561A (ko) 반도체 집적회로 장치
CN109888006B (zh) 一种低功耗绝缘体上硅横向绝缘栅双极型晶体管
JP6048003B2 (ja) Igbtとダイオードが同一半導体基板に形成されている半導体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant