JP5488256B2 - 電力用半導体装置 - Google Patents
電力用半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 40
- 239000003990 capacitor Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 22
- 230000003071 parasitic effect Effects 0.000 description 27
- 238000011084 recovery Methods 0.000 description 19
- 239000010410 layer Substances 0.000 description 10
- 230000000052 comparative effect Effects 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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- H01L29/8611—Planar PN junction diodes
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0081—Power supply means, e.g. to the switch driver
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Description
図1は、実施の形態1に係る電力用半導体装置の回路図である。この電力用半導体装置は、HVIC(High Voltage Integrated Circuit)を適用したハーフブリッジ回路である。
VCC=VB+VF (式1)
VB=Q/CB+VS (式2)
VS=Von (式3)
ここで、VCCはVCC端子の電位、VBはVB端子の電位、VFは高耐圧ダイオードDBの順方向電圧[V]、QはコンデンサCBに充電される総電荷量[C]、CBはコンデンサCBの容量値[F]、VSはVS端子の電位、Vonはローサイドスイッチング素子Tr2のオン電圧[V]である。
VB−VS=Q/CB=Vcc−VF−Von (式4)
よって、充電時は高耐圧ダイオードDBを介して、この電荷量Qに相当する充電電流がコンデンサCBに供給される。
Pw=Ic×VCC=hFE×Ib×VCC (式5)
ここで、hFEは寄生PNPトランジスタの電流利得である。また、VCCは一定、通常hFE>1である。
Icnpn=hFEn×Ib (式6)
ここで、hFEnは寄生NPNトランジスタの電流利得である。
Ich=Ib+Icnpn=Ib(1+hFEn) (式7)
さらに、コンデンサCBへの供給電力Pbは下記の式で表される。
Pb=Ich×(VCC−VB−VS−VF) (式8)
図7は、実施の形態2に係る高耐圧ダイオードを示す断面図である。実施の形態1に比べてP+型コンタクト領域20とN+型コンタクト領域22の配置が逆である。従って、P+型コンタクト領域20は、N+型コンタクト領域22よりもカソード電極24に近い。
図9は、実施の形態3に係る高耐圧ダイオードを示す断面図である。実施の形態2の構成に加えて、N+型コンタクト領域22よりもカソード電極24から離れているP+型コンタクト領域54が設けられている。
図12は、実施の形態4に係る高耐圧ダイオードを示す平面図である。図13は、図12のA−A´に沿った断面図である。図14は、図12のB−B´に沿った断面図である。P−型半導体基板12の表面において、アノード電極26からカソード電極24に向かう方向とは垂直の方向に沿って、P+型コンタクト領域20とN+型コンタクト領域22が交互に配置されている。複数のP+型コンタクト領域20と複数のN+型コンタクト領域22よりもカソード電極24から離れた位置にP+型コンタクト領域54が設けられている。
図16は、実施の形態5に係る高耐圧ダイオードを示す平面図である。図17は、図16のA−A´に沿った断面図である。図18は、図16のB−B´に沿った断面図である。実施の形態4の構成に加えて、複数のP+型コンタクト領域20と複数のN+型コンタクト領域22よりもカソード電極24から離れた位置にN+型コンタクト領域56が設けられている。P+型コンタクト領域54は、N+型コンタクト領域56よりもカソード電極24から離れている。
図19は、実施の形態6に係る高耐圧ダイオードを示す断面図である。実施の形態3の構成に加えて、N型カソード領域14内に設けられ、P型アノード領域16に接続され、フィールド酸化膜28の下まで延びるP−型電圧保持領域58が設けられている。カソード電極24に高電位が印加されると、P−型電圧保持領域58においてカソード側からアノード側に空乏層が形成され、高電圧が保持される。同様に、N型カソード領域14においてアノード側からカソード側に空乏層が形成され、高電圧が保持される。
図20は、実施の形態7に係る高耐圧ダイオードを示す平面図である。図21は、図20のA−A´に沿った断面図である。図22は、図20のB−B´に沿った断面図である。P−型電圧保持領域58は、複数のストライプ状の領域を有する。この複数のストライプ状の領域は、P−型半導体基板12の表面において、アノード電極26からカソード電極24に向かう方向とは垂直の方向に沿って、等間隔で隔離して、互いに平行に並んでいる。
図23は、実施の形態8に係る高耐圧ダイオードを示す平面図である。図24は、図23のA−A´に沿った断面図である。図25は、図23のB−B´に沿った断面図である。実施の形態4の構成に加えて、実施の形態7の複数のストライプ状のP−型電圧保持領域58が設けられている。これにより、実施の形態4及び実施の形態7の効果を得ることができる。
図26は、実施の形態9に係る高耐圧ダイオードを示す平面図である。図27は、図26のA−A´に沿った断面図である。図28は、図26のB−B´に沿った断面図である。実施の形態5の構成に加えて、実施の形態7の複数のストライプ状のP−型電圧保持領域58が設けられている。これにより、実施の形態5及び実施の形態7の効果を得ることができる。
DB 高耐圧ダイオード(ダイオード)
Tr1 ハイサイドスイッチング素子
Tr2 ローサイドスイッチング素子
10a ハイサイド駆動回路
10b ローサイド駆動回路
12 P−型半導体基板(P型半導体基板)
14 N型カソード領域
16 P型アノード領域
20 P+型コンタクト領域(P型コンタクト領域、第1のP型領域)
22 N+型コンタクト領域(N型コンタクト領域、第1のN型領域)
24 カソード電極
26 アノード電極
28 フィールド酸化膜
54 P+型コンタクト領域(P型コンタクト領域、第2のP型領域)
56 N+型コンタクト領域(N型コンタクト領域、第2のN型領域)
58 P−型電圧保持領域(P型電圧保持領域)
Claims (5)
- 高圧側電位と低圧側電位との間に高圧側から順にトーテムポール接続されたハイサイドスイッチング素子及びローサイドスイッチング素子と、
前記ハイサイドスイッチング素子を駆動するハイサイド駆動回路と、
前記ローサイドスイッチング素子を駆動するローサイド駆動回路と、
一端が前記ハイサイドスイッチング素子と前記ローサイドスイッチング素子の接続点に接続され、他端が前記ハイサイド駆動回路の電源端子に接続され、前記ハイサイド駆動回路に駆動電圧を供給するコンデンサと、
アノードが電源に接続され、カソードが前記コンデンサの前記他端に接続され、前記電源からの電流を前記コンデンサの前記他端に供給するダイオードとを備え、
前記ダイオードは、
P型半導体基板と、
前記P型半導体基板の表面に設けられたN型カソード領域と、
前記N型カソード領域内に設けられたP型アノード領域と、
前記P型アノード領域内に設けられたP型コンタクト領域及びN型コンタクト領域と、
前記N型カソード領域に接続されたカソード電極と、
前記P型コンタクト領域及び前記N型コンタクト領域に接続されたアノード電極と、
前記アノード電極と前記カソード電極の間において前記P型半導体基板上に設けられたフィールド酸化膜と、
前記N型カソード領域内に設けられ、前記P型アノード領域に接続され、前記フィールド酸化膜の下まで延びるP型電圧保持領域とを有し、
前記P型電圧保持領域は、複数のストライプ状の領域を有し、
前記P型半導体基板の前記表面において、前記アノード電極から前記カソード電極に向かう方向とは垂直の方向に沿って、前記複数のストライプ状の領域が互いに平行に並んでいることを特徴とする電力用半導体装置。 - 前記P型コンタクト領域は、前記N型コンタクト領域よりも前記カソード電極に近い第1のP型領域を有することを特徴とする請求項1に記載の電力用半導体装置。
- 前記P型コンタクト領域は、前記N型コンタクト領域よりも前記カソード電極から離れている第2のP型領域を更に有することを特徴とする請求項2に記載の電力用半導体装置。
- 前記P型コンタクト領域は複数の第1のP型領域を有し、
前記N型コンタクト領域は複数の第1のN型領域を有し、
前記P型半導体基板の前記表面において、前記アノード電極から前記カソード電極に向かう方向とは垂直の方向に沿って、前記複数の第1のP型領域と前記複数の第1のN型領域が交互に配置されていることを特徴とする請求項1に記載の電力用半導体装置。 - 前記N型コンタクト領域は、前記複数の第1のP型領域及び前記複数の第1のN型領域よりも前記カソード電極から離れている第2のN型領域を更に有し、
前記P型コンタクト領域は、前記第2のN型領域よりも前記カソード電極から離れている第2のP型領域を更に有することを特徴とする請求項4に記載の電力用半導体装置。
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JP2010145346A JP5488256B2 (ja) | 2010-06-25 | 2010-06-25 | 電力用半導体装置 |
US13/018,823 US8362830B2 (en) | 2010-06-25 | 2011-02-01 | Power semiconductor device |
DE102011075367.2A DE102011075367B4 (de) | 2010-06-25 | 2011-05-05 | Leistungshalbleitervorrichtung |
CN201110140111.9A CN102299168B (zh) | 2010-06-25 | 2011-05-16 | 功率用半导体装置 |
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JP2010145346A JP5488256B2 (ja) | 2010-06-25 | 2010-06-25 | 電力用半導体装置 |
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US11824085B2 (en) | 2019-12-25 | 2023-11-21 | Mitsubishi Electric Corporation | Semiconductor device comprising a MOSFET having a RESURF region and higher peak impurity concentration diffusion region in the RESURF region |
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US8941188B2 (en) * | 2012-03-26 | 2015-01-27 | Infineon Technologies Austria Ag | Semiconductor arrangement with a superjunction transistor and a further device integrated in a common semiconductor body |
US9040384B2 (en) * | 2012-10-19 | 2015-05-26 | Freescale Semiconductor, Inc. | High voltage diode |
EP3010042B1 (en) * | 2013-06-14 | 2020-04-15 | Fuji Electric Co., Ltd. | Semiconductor device |
JP6244177B2 (ja) * | 2013-11-12 | 2017-12-06 | 日立オートモティブシステムズ株式会社 | 半導体装置 |
US9621058B2 (en) * | 2015-01-20 | 2017-04-11 | Infineon Technologies Austria Ag | Reducing switching losses associated with a synchronous rectification MOSFET |
TWI629785B (zh) * | 2016-12-29 | 2018-07-11 | 新唐科技股份有限公司 | 高電壓積體電路的高電壓終端結構 |
JP6950380B2 (ja) * | 2017-09-05 | 2021-10-13 | 富士電機株式会社 | 半導体集積回路 |
CN110854081B (zh) * | 2019-10-08 | 2022-01-04 | 深圳市稳先微电子有限公司 | 片上系统 |
CN113421922B (zh) * | 2021-06-25 | 2022-05-13 | 电子科技大学 | 一种具备栅极自钳位功能的三维igbt及其制造方法 |
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US5666280A (en) * | 1993-05-07 | 1997-09-09 | Philips Electronics North America Corporation | High voltage integrated circuit driver for half-bridge circuit employing a jet to emulate a bootstrap diode |
US5502632A (en) * | 1993-05-07 | 1996-03-26 | Philips Electronics North America Corporation | High voltage integrated circuit driver for half-bridge circuit employing a bootstrap diode emulator |
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JP3519226B2 (ja) * | 1996-12-16 | 2004-04-12 | 富士電機デバイステクノロジー株式会社 | 半導体装置 |
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2010
- 2010-06-25 JP JP2010145346A patent/JP5488256B2/ja active Active
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2011
- 2011-02-01 US US13/018,823 patent/US8362830B2/en active Active
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US11824085B2 (en) | 2019-12-25 | 2023-11-21 | Mitsubishi Electric Corporation | Semiconductor device comprising a MOSFET having a RESURF region and higher peak impurity concentration diffusion region in the RESURF region |
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US20110316115A1 (en) | 2011-12-29 |
CN102299168A (zh) | 2011-12-28 |
US8362830B2 (en) | 2013-01-29 |
CN102299168B (zh) | 2014-01-29 |
DE102011075367A1 (de) | 2011-12-29 |
DE102011075367B4 (de) | 2019-01-24 |
JP2012009694A (ja) | 2012-01-12 |
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