JP7407757B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7407757B2 JP7407757B2 JP2021044115A JP2021044115A JP7407757B2 JP 7407757 B2 JP7407757 B2 JP 7407757B2 JP 2021044115 A JP2021044115 A JP 2021044115A JP 2021044115 A JP2021044115 A JP 2021044115A JP 7407757 B2 JP7407757 B2 JP 7407757B2
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- 239000004065 semiconductor Substances 0.000 title claims description 273
- 239000012535 impurity Substances 0.000 claims description 56
- 239000010410 layer Substances 0.000 description 124
- 238000002347 injection Methods 0.000 description 21
- 239000007924 injection Substances 0.000 description 21
- 239000011229 interlayer Substances 0.000 description 21
- 239000000969 carrier Substances 0.000 description 15
- 230000006378 damage Effects 0.000 description 15
- 238000009413 insulation Methods 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 9
- 230000007423 decrease Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 230000004048 modification Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 238000004645 scanning capacitance microscopy Methods 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 238000011084 recovery Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000002452 interceptive effect Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Description
第1の実施形態の半導体装置は、第1の面と、第1の面と対向する第2の面を有する半導体層と、半導体層の第1の面の側に設けられた第1のゲート電極を、有する第1のトランジスタと、半導体層の第2の面の側に設けられた第2のゲート電極を、有する第2のトランジスタと、を含むトランジスタ領域と、半導体層と、第2のゲート電極に電気的に接続され半導体層の第2の面の側に設けられた第3のゲート電極を有し、第2のトランジスタの閾値電圧の絶対値よりも小さい閾値電圧の絶対値を有する第3のトランジスタと、を含みトランジスタ領域に隣接する隣接領域と、を備える。
第2の実施形態の半導体装置は、第1の面と、第1の面と対向する第2の面を有する半導体層と、半導体層の第1の面の側に設けられた第1のゲート電極を、有する第1のトランジスタと、半導体層の第2の面の側に設けられた第2のゲート電極を、有する第2のトランジスタと、を含むトランジスタ領域と、半導体層と、第2のゲート電極に電気的に接続され、所定の面積における占有割合が第2のゲート電極の所定の面積における占有割合よりも高く、半導体層の第2の面の側に設けられた第3のゲート電極を有する第3のトランジスタと、を含みトランジスタ領域に隣接する隣接領域と、を備える。
第3の実施形態の半導体装置は、半導体層は、第2の面の側に設けられた第2のトレンチと、第2の面の側に設けられた第3のトレンチと、を、更に含み、第2のゲート電極は、第2のトレンチの中に設けられ、第3のゲート電極は、第3のトレンチの中に設けられた点で、第2の実施形態の半導体装置と異なる。以下、第1又は第2の実施形態と重複する内容については、一部記述を省略する場合がある。
第4の実施形態の半導体装置は、終端領域を備えた半導体装置である点で、第1の実施形態の半導体装置と異なる。以下、第1の実施形態と重複する内容については、一部記述を省略する場合がある。
第5の実施形態の半導体装置は、第1の面と、第1の面と対向する第2の面を有する半導体層と、半導体層の第1の面の側に設けられた第1のゲート電極を、有する第1のトランジスタと、半導体層の第2の面の側に設けられた第2のゲート電極を、有する第2のトランジスタと、を含むトランジスタ領域と、半導体層と、第2のゲート電極に電気的に接続され、所定の面積における占有割合が第2のゲート電極の所定の面積における占有割合よりも高く、半導体層の第2の面の側に設けられた第3のゲート電極を有する第3のトランジスタと、を含みトランジスタ領域に隣接する隣接領域と、を備える。
12 上部電極(第1の電極)
14 下部電極(第2の電極)
31 第1のゲート電極
32 第2のゲート電極
33 第3のゲート電極
51 メインゲートトレンチ(第1のトレンチ)
53 第1の裏面トレンチ(第2のトレンチ)
54 第2の裏面トレンチ(第3のトレンチ)
60 第1のドレイン領域(第6の半導体領域)
62 第2のドレイン領域(第7の半導体領域)
64 第1のコレクタ領域(第4の半導体領域)
66 第2のコレクタ領域(第5の半導体領域)
70 ドリフト領域(第1の半導体領域)
72 ベース領域(第2の半導体領域)
74 エミッタ領域(第3の半導体領域)
100 RC-IGBT(半導体装置)
100a IGBT領域(トランジスタ領域)
100b ダイオード領域
100c 境界領域(隣接領域)
200 RC-IGBT(半導体装置)
300 RC-IGBT(半導体装置)
400 IGBT(半導体装置)
400a IGBT領域(トランジスタ領域)
400b 終端領域(隣接領域)
500 IGBT(半導体装置)
P1 第1の面
P2 第2の面
X 第1のトランジスタ
Y 第2のトランジスタ
Z 第3のトランジスタ
Claims (8)
- 第1の面と、前記第1の面と対向する第2の面を有する半導体層と、
前記半導体層の前記第1の面の側に設けられた第1のゲート電極を、有する第1のトランジスタと、
前記半導体層の前記第2の面の側に設けられた第2のゲート電極を、有する第2のトランジスタと、
を含むトランジスタ領域と、
前記半導体層と、
前記第2のゲート電極に電気的に接続され前記半導体層の前記第2の面の側に設けられた第3のゲート電極を有し、前記第2のトランジスタの閾値電圧の絶対値よりも小さい閾値電圧の絶対値を有する第3のトランジスタと、
を含み前記トランジスタ領域に隣接する隣接領域と、
を備えた半導体装置。 - 前記第1の面に接する第1の電極と、
前記第2の面に接する第2の電極と、
を更に備え、
前記半導体層は、
第1導電形の第1の半導体領域と、
前記第1の半導体領域と前記第1の面との間に設けられ、前記第1のゲート電極と対向する第2導電形の第2の半導体領域と、
前記第2の半導体領域と前記第1の面との間に設けられ、前記第1の電極と接する第1導電形の第3の半導体領域と、
前記第1の半導体領域と前記第2の面との間に設けられ、前記第2のゲート電極と対向し、前記第2の電極と接する第2導電形の第4の半導体領域と、
前記第1の半導体領域と前記第2の面との間に設けられ、前記第3のゲート電極と対向し、前記第2の電極と接する第2導電形の第5の半導体領域と、
前記第4の半導体領域と前記第2の面との間に設けられ、前記第2の電極と接する第1導電形の第6の半導体領域と、
前記第5の半導体領域と前記第2の面との間に設けられ、前記第2の電極と接する第1導電形の第7の半導体領域と、
を更に含み、
前記第3のゲート電極と対向する部分の前記第5の半導体領域の第2導電形不純物濃度は、前記第2のゲート電極と対向する部分の前記第4の半導体領域の第2導電形不純物濃度よりも低い請求項1記載の半導体装置。 - 前記第3のトランジスタの閾値電圧の絶対値は、前記第2のトランジスタの閾値電圧の絶対値の3分の2以下である請求項1又は請求項2いずれか一項記載の半導体装置。
- 第1の面と、前記第1の面と対向する第2の面を有する半導体層と、
前記半導体層の前記第1の面の側に設けられた第1のゲート電極を、有する第1のトランジスタと、
前記半導体層の前記第2の面の側に設けられた第2のゲート電極を、有する第2のトランジスタと、
を含むトランジスタ領域と、
前記半導体層と、
前記第2のゲート電極に電気的に接続され、所定の面積における占有割合が前記第2のゲート電極の前記所定の面積における占有割合よりも高く、前記半導体層の前記第2の面の側に設けられた第3のゲート電極を有する第3のトランジスタと、
を含み前記トランジスタ領域に隣接する隣接領域と、
を備えた半導体装置。 - 前記半導体層は、前記第1の面の側に設けられた第1のトレンチを、更に含み、
前記第1のゲート電極は、前記第1のトレンチの中に設けられた請求項1ないし請求項4いずれか一項記載の半導体装置。 - 前記半導体層は、前記第2の面の側に設けられた第2のトレンチと、前記第2の面の側に設けられた第3のトレンチと、を更に含み、
前記第2のゲート電極は、前記第2のトレンチの中に設けられ、
前記第3のゲート電極は、前記第3のトレンチの中に設けられた請求項1ないし請求項5いずれか一項記載の半導体装置。 - 前記半導体層と、ダイオードと、を含み前記トランジスタ領域との間に前記隣接領域が設けられたダイオード領域を、更に備える請求項1ないし請求項6いずれか一項記載の半導体装置。
- 前記隣接領域は、前記トランジスタ領域を囲む請求項1ないし請求項6いずれか一項記載の半導体装置。
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