JP6658021B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6658021B2 JP6658021B2 JP2016019253A JP2016019253A JP6658021B2 JP 6658021 B2 JP6658021 B2 JP 6658021B2 JP 2016019253 A JP2016019253 A JP 2016019253A JP 2016019253 A JP2016019253 A JP 2016019253A JP 6658021 B2 JP6658021 B2 JP 6658021B2
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- 210000000746 body region Anatomy 0.000 claims description 21
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- H02M7/5395—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0843—Source or drain regions of field-effect devices
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- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0009—Devices or circuits for detecting current in a converter
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0051—Diode reverse recovery losses
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
- H02M1/327—Means for protecting converters other than automatic disconnection against abnormal temperatures
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/66—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output with possibility of reversal
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- H02M7/72—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output with possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/79—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output with possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/797—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output with possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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Description
最初に、図1を参照して、本実施形態に係るダイオードおよびダイオードを含む半導体装置の概略構成について説明する。
本変形例におけるインバータ110は、上記した第1実施形態の第1駆動部30および第2駆動部40にスイッチSW3を追加した構成となっている。スイッチSW3は図4に示すように、IGBT部11,21のゲート電極とアノード電極(エミッタ電極と共通)とを同電位にするためのスイッチである。なお、PWM発振装置43は、外部ECUから出力されたPWM基準信号が入力され、スイッチSW1,SW2,SW3に出力する制御信号を生成するが、図4ではその図示を省略している。
第1実施形態および変形例1では、逆導通スイッチング素子の動作モードが逆導通モードである場合に、ゲート電極82に常に寄生ゲート電圧が印加されている形態について説明した。これに対して、本変形例では、図6に示すように、逆導通モード時においてもゲート電圧がPWM基準信号に同期して変動する。なお、第1駆動部30および第2駆動部40の回路構成は変形例1と同様であるから説明を省略する。また、順導通モードのついての動作も変形例1と同一であるから説明を省略する。
第1実施形態および変形例1および2では、負荷電流Iの向きに基づいて第1素子10および第2素子20の動作モードを判定する例を示した。動作モードの判定は、負荷電流Iの向きのほか、第1素子10および第2素子20の出力電流の向き、あるいは出力電圧に基づいて行うこともできる。
上記した第1実施形態および変形例1,2,3では、逆導通スイッチング素子の動作モードのみを条件にゲート電極82への寄生ゲート電圧の印加を決定する例を説明したが、動作モードに加えて種々の条件を追加してもよい。
本実施形態では、ダイオードおよびダイオードを含む半導体装置が昇圧回路、具体的には昇圧コンバータに適用される形態について説明する。なお、本実施形態の説明に供される各図において、第1実施形態において記載したインバータを構成する要素と同一の電子素子については同一の符号を付すこととする。
第2実施形態では、昇圧判定部51が、出力端子Voutの電圧が所定の閾値より高い場合を昇圧動作、閾値以下の場合を非昇圧動作と判定する例を示したが、昇圧判定部51による昇圧状態の判定は、出力端子Voutの電圧と閾値との比較以外の手段を用いることもできる。
第2実施形態および変形例5では、昇圧コンバータ120が昇圧動作中か非昇圧動作中かによって駆動部30,40が出力するゲート電圧の印加パターンを定める例について説明したが、リアクトル90を流れる電流の電流モードによって印加パターンを定めることもできる。
第1実施形態、第2実施形態および変形例1〜6において第1素子10、第2素子20たる逆導通絶縁ゲートバイポーラトランジスタは、図2に示す構造を有していることを説明した。図2を参照して説明した構造に加えて、図16に示すように、n導電型のピラー領域83を有していることが好ましい。ピラー領域83は、半導体基板70の第2主面70bから厚さ方向に延び、アノード領域77aあるいはボディ領域77bを貫通して第1バリア領域76a、第2バリア領域76bに至るように形成されている。ピラー領域83は、第1、第2バリア領域76a,76bと同一の不純物が略同濃度ドープされた拡散層であり、ピラー領域83とバリア領域76a,76bとは略同電位である。
以上、本発明の好ましい実施形態について説明したが、本発明は上記した実施形態になんら制限されることなく、本発明の主旨を逸脱しない範囲において、種々変形して実施することが可能である。
Claims (18)
- 同一の半導体基板にダイオード(12)とスイッチング素子(11)とが並列して形成された逆導通スイッチング素子(10,20)と、
前記逆導通スイッチング素子にゲート電圧を印加する駆動部(30,40)と、
主に前記スイッチング素子に電流が流れる順導通モードと、主に前記ダイオードに電流が流れる逆導通モードと、のいずれのモードで駆動しているかを判定するモード判定部(50)と、を備え、
前記ダイオードは、
半導体基板(70)の第1主面(70a)に形成された第1電極(71)と、
前記第1主面の表層であって前記第1電極上に積層された第1導電型の第1不純物領域(72a)と、
前記第1不純物領域上に積層され、前記第1不純物領域よりも不純物濃度が低くされた第1導電型の第1ドリフト領域(74a)と、
前記第1ドリフト領域上に積層された第2導電型の第2不純物領域(77a)と、
前記第2不純物領域上であって前記半導体基板の第1主面と反対の第2主面に形成された第2電極(79)と、
前記第1ドリフト領域と前記第2不純物領域との間に形成され、前記第1ドリフト領域よりも不純物濃度が高くされた第1導電型の第1バリア領域(76a)と、
前記第1バリア領域と前記第1ドリフト領域との間に形成された第2導電型の第1電界伸展防止領域(75a)と、を有し、
前記スイッチング素子は、
第1導電型の第2ドリフト領域(74b)と、
前記第2主面の表層に形成された第2導電型のボディ領域(77b)と、
前記半導体基板の第2主面の表層であって前記ボディ領域に取り囲まれて形成された第1導電型の第3不純物領域(78)と、を有し、
前記ダイオードおよび前記スイッチング素子は、
前記第2主面から前記第2不純物領域、および、前記第1バリア領域を貫通して前記第1ドリフト領域に至って形成され、前記ゲート電圧を印加するためのトレンチ電極(82)を有するトレンチゲート(80)と、を有し、
前記駆動部は、前記逆導通モードにおいて、前記ゲート電圧として、
前記第2電極との電位差の絶対値が、前記第2不純物領域と前記第1バリア領域と前記第1電界伸展防止領域とにより形成される寄生トランジスタの閾値電圧以上とされる寄生ゲート電圧を印加し、
前記駆動部は、前記逆導通モードにおいて、
ハイレベルとローレベルの2値を少なくとも有しPWM制御された前記ゲート電圧を前記トレンチゲートに印加するものであり、
前記ローレベルが前記寄生ゲート電圧である半導体装置。 - 前記逆導通モード時において前記第2電極と前記第1電極との間に流れるダイオード電流の電流値を検出するダイオード電流検出部(13)をさらに備え、
前記駆動部は、前記ダイオード電流検出部により検出される前記ダイオード電流が所定の閾値以下であることを条件に、前記ゲート電圧として前記寄生ゲート電圧を印加する請求項1に記載の半導体装置。 - 同一の半導体基板にダイオード(12)とスイッチング素子(11)とが並列して形成された逆導通スイッチング素子(10,20)と、
前記逆導通スイッチング素子にゲート電圧を印加する駆動部(30,40)と、
主に前記スイッチング素子に電流が流れる順導通モードと、主に前記ダイオードに電流が流れる逆導通モードと、のいずれのモードで駆動しているかを判定するモード判定部(50)と、を備え、
前記ダイオードは、
半導体基板(70)の第1主面(70a)に形成された第1電極(71)と、
前記第1主面の表層であって前記第1電極上に積層された第1導電型の第1不純物領域(72a)と、
前記第1不純物領域上に積層され、前記第1不純物領域よりも不純物濃度が低くされた第1導電型の第1ドリフト領域(74a)と、
前記第1ドリフト領域上に積層された第2導電型の第2不純物領域(77a)と、
前記第2不純物領域上であって前記半導体基板の第1主面と反対の第2主面に形成された第2電極(79)と、
前記第1ドリフト領域と前記第2不純物領域との間に形成され、前記第1ドリフト領域よりも不純物濃度が高くされた第1導電型の第1バリア領域(76a)と、
前記第1バリア領域と前記第1ドリフト領域との間に形成された第2導電型の第1電界伸展防止領域(75a)と、を有し、
前記スイッチング素子は、
第1導電型の第2ドリフト領域(74b)と、
前記第2主面の表層に形成された第2導電型のボディ領域(77b)と、
前記半導体基板の第2主面の表層であって前記ボディ領域に取り囲まれて形成された第1導電型の第3不純物領域(78)と、を有し、
前記ダイオードおよび前記スイッチング素子は、
前記第2主面から前記第2不純物領域、および、前記第1バリア領域を貫通して前記第1ドリフト領域に至って形成され、前記ゲート電圧を印加するためのトレンチ電極(82)を有するトレンチゲート(80)と、を有し、
前記駆動部は、前記逆導通モードにおいて、前記ゲート電圧として、
前記第2電極との電位差の絶対値が、前記第2不純物領域と前記第1バリア領域と前記第1電界伸展防止領域とにより形成される寄生トランジスタの閾値電圧以上とされる寄生ゲート電圧を印加し、
前記逆導通モード時において前記第2電極と前記第1電極との間に流れるダイオード電流の電流値を検出するダイオード電流検出部(13)をさらに備え、
前記駆動部は、前記ダイオード電流検出部により検出される前記ダイオード電流が所定の閾値以下であることを条件に、前記ゲート電圧として前記寄生ゲート電圧を印加する半導体装置。 - 前記逆導通スイッチング素子の温度を検出する温度検出部(17,18)をさらに備え、
前記駆動部は、前記温度検出部により検出される前記逆導通スイッチング素子の温度が所定の閾値以下であることを条件に、前記ゲート電圧として前記寄生ゲート電圧を印加する請求項1〜3のいずれか1項に記載の半導体装置。 - 同一の半導体基板にダイオード(12)とスイッチング素子(11)とが並列して形成された逆導通スイッチング素子(10,20)と、
前記逆導通スイッチング素子にゲート電圧を印加する駆動部(30,40)と、
主に前記スイッチング素子に電流が流れる順導通モードと、主に前記ダイオードに電流が流れる逆導通モードと、のいずれのモードで駆動しているかを判定するモード判定部(50)と、を備え、
前記ダイオードは、
半導体基板(70)の第1主面(70a)に形成された第1電極(71)と、
前記第1主面の表層であって前記第1電極上に積層された第1導電型の第1不純物領域(72a)と、
前記第1不純物領域上に積層され、前記第1不純物領域よりも不純物濃度が低くされた第1導電型の第1ドリフト領域(74a)と、
前記第1ドリフト領域上に積層された第2導電型の第2不純物領域(77a)と、
前記第2不純物領域上であって前記半導体基板の第1主面と反対の第2主面に形成された第2電極(79)と、
前記第1ドリフト領域と前記第2不純物領域との間に形成され、前記第1ドリフト領域よりも不純物濃度が高くされた第1導電型の第1バリア領域(76a)と、
前記第1バリア領域と前記第1ドリフト領域との間に形成された第2導電型の第1電界伸展防止領域(75a)と、を有し、
前記スイッチング素子は、
第1導電型の第2ドリフト領域(74b)と、
前記第2主面の表層に形成された第2導電型のボディ領域(77b)と、
前記半導体基板の第2主面の表層であって前記ボディ領域に取り囲まれて形成された第1導電型の第3不純物領域(78)と、を有し、
前記ダイオードおよび前記スイッチング素子は、
前記第2主面から前記第2不純物領域、および、前記第1バリア領域を貫通して前記第1ドリフト領域に至って形成され、前記ゲート電圧を印加するためのトレンチ電極(82)を有するトレンチゲート(80)と、を有し、
前記駆動部は、前記逆導通モードにおいて、前記ゲート電圧として、
前記第2電極との電位差の絶対値が、前記第2不純物領域と前記第1バリア領域と前記第1電界伸展防止領域とにより形成される寄生トランジスタの閾値電圧以上とされる寄生ゲート電圧を印加し、
前記逆導通スイッチング素子の温度を検出する温度検出部(17,18)をさらに備え、
前記駆動部は、前記温度検出部により検出される前記逆導通スイッチング素子の温度が所定の閾値以下であることを条件に、前記ゲート電圧として前記寄生ゲート電圧を印加する半導体装置。 - 前記逆導通スイッチング素子に電圧を供給する電源電圧(VCC)の電圧が所定の閾値以下であることを条件に、前記ゲート電圧として前記寄生ゲート電圧を印加する請求項1〜5のいずれか1項に記載の半導体装置。
- 前記電源電圧を検出するために、前記第2電極と前記第1電極との間に印加される電圧を検出する電圧検出部(14)をさらに備え、
前記駆動部は、前記電圧検出部により検出される電圧が所定の閾値以下であることを条件に、前記ゲート電圧として前記寄生ゲート電圧を印加する請求項6に記載の半導体装置。 - 2つの前記逆導通スイッチング素子が直列に接続されて、各逆導通スイッチング素子がそれぞれ上アームと下アームを構成し、前記上アームと前記下アームの接続点に負荷の一端が接続され、
前記負荷に流れる負荷電流を検出する負荷電流検出部(60)をさらに備え、前記接続点から前記負荷に向かって流れる電流を正とするとき、
前記モード判定部は、
前記負荷電流が正の場合に、前記上アームの逆導通スイッチング素子は順導通モードであり、前記下アームの逆導通スイッチング素子は逆導通モードであり、
前記負荷電流が負の場合に、前記上アームの逆導通スイッチング素子は逆導通モードであり、前記下アームの逆導通スイッチング素子は順導通モードである、と判定する請求項6または請求項7に記載の半導体装置。 - 2つの前記逆導通スイッチング素子が直列に接続されて、各逆導通スイッチング素子がそれぞれ上アームと下アームを構成し、
前記上アームと前記下アームの接続点にリアクトル(90)の一端が接続され、
前記リアクトルにおける前記逆導通スイッチング素子が接続された一端と反対の他端に入力電圧が印加され、
前記駆動部によりパルス制御された前記ゲート電圧に基づいて前記入力電圧を昇圧する昇圧回路が構成される請求項1〜5のいずれか1項に記載の半導体装置。 - 前記昇圧回路において、昇圧動作をしているか否かを判定する昇圧判定部(51)をさらに備え、
前記駆動部は、前記昇圧回路が昇圧動作をしていないことを条件に、前記ゲート電圧として前記寄生ゲート電圧を印加する請求項9に記載の半導体装置。 - 同一の半導体基板にダイオード(12)とスイッチング素子(11)とが並列して形成された逆導通スイッチング素子(10,20)と、
前記逆導通スイッチング素子にゲート電圧を印加する駆動部(30,40)と、
主に前記スイッチング素子に電流が流れる順導通モードと、主に前記ダイオードに電流が流れる逆導通モードと、のいずれのモードで駆動しているかを判定するモード判定部(50)と、を備え、
前記ダイオードは、
半導体基板(70)の第1主面(70a)に形成された第1電極(71)と、
前記第1主面の表層であって前記第1電極上に積層された第1導電型の第1不純物領域(72a)と、
前記第1不純物領域上に積層され、前記第1不純物領域よりも不純物濃度が低くされた第1導電型の第1ドリフト領域(74a)と、
前記第1ドリフト領域上に積層された第2導電型の第2不純物領域(77a)と、
前記第2不純物領域上であって前記半導体基板の第1主面と反対の第2主面に形成された第2電極(79)と、
前記第1ドリフト領域と前記第2不純物領域との間に形成され、前記第1ドリフト領域よりも不純物濃度が高くされた第1導電型の第1バリア領域(76a)と、
前記第1バリア領域と前記第1ドリフト領域との間に形成された第2導電型の第1電界伸展防止領域(75a)と、を有し、
前記スイッチング素子は、
第1導電型の第2ドリフト領域(74b)と、
前記第2主面の表層に形成された第2導電型のボディ領域(77b)と、
前記半導体基板の第2主面の表層であって前記ボディ領域に取り囲まれて形成された第1導電型の第3不純物領域(78)と、を有し、
前記ダイオードおよび前記スイッチング素子は、
前記第2主面から前記第2不純物領域、および、前記第1バリア領域を貫通して前記第1ドリフト領域に至って形成され、前記ゲート電圧を印加するためのトレンチ電極(82)を有するトレンチゲート(80)と、を有し、
前記駆動部は、前記逆導通モードにおいて、前記ゲート電圧として、
前記第2電極との電位差の絶対値が、前記第2不純物領域と前記第1バリア領域と前記第1電界伸展防止領域とにより形成される寄生トランジスタの閾値電圧以上とされる寄生ゲート電圧を印加し、
2つの前記逆導通スイッチング素子が直列に接続されて、各逆導通スイッチング素子がそれぞれ上アームと下アームを構成し、
前記上アームと前記下アームの接続点にリアクトル(90)の一端が接続され、
前記リアクトルにおける前記逆導通スイッチング素子が接続された一端と反対の他端に入力電圧が印加され、
前記駆動部によりパルス制御された前記ゲート電圧に基づいて前記入力電圧を昇圧する昇圧回路が構成され、
前記昇圧回路において、昇圧動作をしているか否かを判定する昇圧判定部(51)をさらに備え、
前記駆動部は、前記昇圧回路が昇圧動作をしていないことを条件に、前記ゲート電圧として前記寄生ゲート電圧を印加する半導体装置。 - 前記昇圧判定部は、前記昇圧回路の出力電圧が、所定の閾値より高いことを以って、前記昇圧回路が昇圧動作をしていると判定する請求項10または請求項11に記載の半導体装置。
- 前記昇圧判定部は、前記駆動部に、PWM制御された前記ゲート電圧を生成するための基準となるPWM基準信号が入力されていることを以って、前記昇圧回路が昇圧動作をしていると判定する請求項10〜12のいずれか1項に記載の半導体装置。
- 前記駆動部は、前記リアクトルに流れるリアクトル電流がゼロ点を含む不連続動作中であることを条件に、前記ゲート電圧として前記寄生ゲート電圧を印加する請求項9〜13のいずれか1項に記載の半導体装置。
- 同一の半導体基板にダイオード(12)とスイッチング素子(11)とが並列して形成された逆導通スイッチング素子(10,20)と、
前記逆導通スイッチング素子にゲート電圧を印加する駆動部(30,40)と、
主に前記スイッチング素子に電流が流れる順導通モードと、主に前記ダイオードに電流が流れる逆導通モードと、のいずれのモードで駆動しているかを判定するモード判定部(50)と、を備え、
前記ダイオードは、
半導体基板(70)の第1主面(70a)に形成された第1電極(71)と、
前記第1主面の表層であって前記第1電極上に積層された第1導電型の第1不純物領域(72a)と、
前記第1不純物領域上に積層され、前記第1不純物領域よりも不純物濃度が低くされた第1導電型の第1ドリフト領域(74a)と、
前記第1ドリフト領域上に積層された第2導電型の第2不純物領域(77a)と、
前記第2不純物領域上であって前記半導体基板の第1主面と反対の第2主面に形成された第2電極(79)と、
前記第1ドリフト領域と前記第2不純物領域との間に形成され、前記第1ドリフト領域よりも不純物濃度が高くされた第1導電型の第1バリア領域(76a)と、
前記第1バリア領域と前記第1ドリフト領域との間に形成された第2導電型の第1電界伸展防止領域(75a)と、を有し、
前記スイッチング素子は、
第1導電型の第2ドリフト領域(74b)と、
前記第2主面の表層に形成された第2導電型のボディ領域(77b)と、
前記半導体基板の第2主面の表層であって前記ボディ領域に取り囲まれて形成された第1導電型の第3不純物領域(78)と、を有し、
前記ダイオードおよび前記スイッチング素子は、
前記第2主面から前記第2不純物領域、および、前記第1バリア領域を貫通して前記第1ドリフト領域に至って形成され、前記ゲート電圧を印加するためのトレンチ電極(82)を有するトレンチゲート(80)と、を有し、
前記駆動部は、前記逆導通モードにおいて、前記ゲート電圧として、
前記第2電極との電位差の絶対値が、前記第2不純物領域と前記第1バリア領域と前記第1電界伸展防止領域とにより形成される寄生トランジスタの閾値電圧以上とされる寄生ゲート電圧を印加し、
2つの前記逆導通スイッチング素子が直列に接続されて、各逆導通スイッチング素子がそれぞれ上アームと下アームを構成し、
前記上アームと前記下アームの接続点にリアクトル(90)の一端が接続され、
前記リアクトルにおける前記逆導通スイッチング素子が接続された一端と反対の他端に入力電圧が印加され、
前記駆動部によりパルス制御された前記ゲート電圧に基づいて前記入力電圧を昇圧する昇圧回路が構成され、
前記駆動部は、前記リアクトルに流れるリアクトル電流がゼロ点を含む不連続動作中であることを条件に、前記ゲート電圧として前記寄生ゲート電圧を印加する半導体装置。 - 前記第2電極と前記第1バリア領域とを繋ぐように前記第2不純物領域を貫通して形成された第1導電型のピラー領域(83)を有する請求項1〜15のいずれか1項に記載の半導体装置。
- 前記逆導通スイッチング素子の出力電流の電流値を検出する出力電流検出部(13)をさらに備え、
前記第1電極から前記第2電極へ流れる前記出力電流を正とするとき、
前記モード判定部は、
前記出力電流が正の場合に、逆導通スイッチング素子は順導通モードであり、
前記出力電流が負の場合に、逆導通スイッチング素子は逆導通モードである、と判定する請求項1〜16のいずれか1項に記載の半導体装置。 - 前記逆導通スイッチング素子における前記第1電極の電圧を検出する電圧検出部(14)をさらに備え、
前記モード判定部は、
前記第1電極の電圧が前記第2電極の電圧よりも高い場合に、逆導通スイッチング素子は順導通モードであり、
前記第1電極の電圧が前記第2電極の電圧よりも低い場合に、逆導通スイッチング素子は逆導通モードである、と判定する請求項1〜17のいずれか1項に記載の半導体装置。
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