JP6414090B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6414090B2 JP6414090B2 JP2016013713A JP2016013713A JP6414090B2 JP 6414090 B2 JP6414090 B2 JP 6414090B2 JP 2016013713 A JP2016013713 A JP 2016013713A JP 2016013713 A JP2016013713 A JP 2016013713A JP 6414090 B2 JP6414090 B2 JP 6414090B2
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- 230000004888 barrier function Effects 0.000 claims description 43
- 239000012535 impurity Substances 0.000 claims description 39
- 239000000758 substrate Substances 0.000 claims description 14
- 239000010410 layer Substances 0.000 description 15
- 210000000746 body region Anatomy 0.000 description 13
- 238000011084 recovery Methods 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 7
- 238000001514 detection method Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
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- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
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- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/538—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a push-pull configuration
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Description
ダイオード素子は、第1導電型の第1不純物領域(72a,73a,75a)と、第1不純物領域に接合して形成された第2導電型の第2不純物領域(76a,91)と、第1不純物領域と電気的に接続される第1電極(71,95)と、第2不純物領域と電気的に接続される第2電極(78,94)と、を有し、ゲート電極に所定のゲート電圧が印加されることにより、第1不純物領域に反転層が生じるものであり、
スイッチング素子は、ダイオード素子と共通した第1電極および第2電極を有するとともに、ゲート電極に所定のゲート電圧が印加されることによりオンの状態とされて第1電極と第2電極との間に電流が流れるものであり、
複数のゲート電極は、スイッチング素子をオンの状態とする第1ゲート電圧が入力される第1ゲート電極(82a)と、第1ゲート電圧とは独立して制御され、第2電極の電位と同一、もしくは、第2電極の電位を基準として第1ゲート電圧の極性と反対の極性となる第2ゲート電圧が入力される第2ゲート電極(82b)と、を有し、
ダイオード素子に属するゲート電極は、少なくとも第2ゲート電極を含み、スイッチング素子に属するゲート電極は、少なくとも第1ゲート電極を含み、第1電極と第2電極との間を流れる電流に基づいて、モード判定部により、逆導通モードと判定された際、もしくは、逆導通モードか順導通モードかを判定できない際、第2ゲート電極に、第2ゲート電圧が印加されることを特徴としている。
最初に、図1を参照して、本実施形態に係る半導体装置の概略構成について説明する。
図5に示すように、この例では、第2ゲート電極82bに印加されるゲート電圧も、第1ゲート電極82aと同様にPWM基準信号に同期して印加される。PWM基準信号のHigh/Lowは、上アームを構成する第1素子10に対応するものと、下アームを構成する第2素子20に対応するものとで互いに反転した関係になっている。PWM基準信号がHighの期間において、図4に示すゲート電圧が有効となり、PWM基準信号がLowの期間はエミッタ電圧Veがゲート電圧として各ゲート電極82に入力される。
図6に示すように、この例では、状態B〜Dにおいて第2ゲート電極82bに印加されるゲート電圧が−V2であるとき、PWM基準信号に依らず常に電圧−V2が印加される。この例でも、ダイオード素子12にエミッタ電圧Veに対して負の電圧−V2を印加するので順電圧VFを低減することができる。また、IGBT素子11においてボディ領域76bへホールが流入しやすい状況をつくることができ、ターンオフに係るスイッチング速度を速くすることができる。ただし、上述したPWM基準信号に同期する動作に比べて、V2の大きさを小さく設定することが好ましい。これは、V2の大きさを過剰に設定すると逆導通によるダイオード電流が大きい状態では、ダイオード素子12におけるリカバリ損失が大きくなるためである。この例のように、PWM基準信号に依らず常に電圧−V2が印加されるような態様は、順電圧VFによる損失の低減効果が高いが、リカバリ損失も増大する虞があるため、システム全体の駆動損失に占める順電圧VFによる損失の割合が大きいシステムにおいて有効である。
PWM基準信号に依らず常に電圧−V2が印加される態様では、上記したように、ダイオード電流が大きい場合にリカバリ損失が増大してしまう虞がある。これを解決するため、この例では、図7に示すように、ダイオード電流、ひいては負荷電流Iに閾値を設ける。負荷電流Iの大きさが閾値より小さい場合には第2ゲート電極82bに電圧−V2が印加され、負荷電流Iの大きさが閾値以上の場合は、第2ゲート電極82bに電圧Veが印加される。これにより、ダイオード電流が大きい場合のリカバリ損失を低減することができる。
第1実施形態において説明した第1素子10、第2素子20たる逆導通絶縁ゲートバイポーラトランジスタに加えて、図8に示すように、n導電型のピラー領域79を有していることが好ましい。ピラー領域79は、半導体基板70の第2主面70bから厚さ方向に延び、アノード領域76aあるいはボディ領域76bを貫通して第1バリア領域75a、第2バリア領域75bに至るように形成されている。ピラー領域79は、第1、第2バリア領域75a,75bと同一の導電型の不純物がドープされた拡散層であり、ピラー領域79とバリア領域75a,75bとは略同電位である。
第1実施形態において図3を参照して平面レイアウトについて説明した間引き構造について、本実施形態において具体的に説明する。本実施形態では、第2実施形態において説明したように、ピラー領域79を備える態様であって、図9に示すように、ダイオード素子12において、互いに隣り合うゲート電極82をアノード電極78と短絡させないようになっている。換言すれば、アノード電極78と短絡したゲート電極82に隣接するゲート電極82は、第2ゲート電極82bに割り当てられている。これによれば、ダイオード素子12に形成された第1バリア領域75aは、少なくとも一つの第2ゲート電極82bに、絶縁膜81を介して接しているので、ダイオード素子12は、第2ゲート電極82bに負電圧−V2が印加されることによる順電圧VFの低減効果を奏することができる。また、間引き構造によるゲート容量の低減効果を奏することもできる。
以上、本発明の好ましい実施形態について説明したが、本発明は上記した実施形態になんら制限されることなく、本発明の主旨を逸脱しない範囲において、種々変形して実施することが可能である。
Claims (10)
- 同一の半導体基板(70,90)にダイオード素子(11)とスイッチング素子(12)とが並列して形成された逆導通スイッチング素子(10,20)と、
前記逆導通スイッチング素子に形成される複数のゲート電極(82)にゲート電圧を印加する駆動部(30,40)と、
主に前記スイッチング素子に電流が流れる順導通モードと、主に前記ダイオード素子に電流が流れる逆導通モードと、のいずれのモードで駆動しているかを判定するモード判定部(50)と、を備え、
前記ダイオード素子は、
第1導電型の第1不純物領域(72a,73a,75a)と、
前記第1不純物領域に接合して形成された第2導電型の第2不純物領域(76a,91)と、
前記第1不純物領域と電気的に接続される第1電極(71,95)と、
前記第2不純物領域と電気的に接続される第2電極(78,94)と、を有し、
前記ゲート電極に所定のゲート電圧が印加されることにより、前記第1不純物領域に反転層が生じるものであり、
前記スイッチング素子は、
前記ダイオード素子と共通した前記第1電極および前記第2電極を有するとともに、前記ゲート電極に所定のゲート電圧が印加されることによりオンの状態とされて前記第1電極と前記第2電極との間に電流が流れるものであり、
前記複数のゲート電極は、
前記スイッチング素子をオンの状態とする第1ゲート電圧が入力される第1ゲート電極(82a)と、
前記第1ゲート電圧とは独立して制御され、前記第2電極の電位と同一、もしくは、前記第2電極の電位を基準として前記第1ゲート電圧の極性と反対の極性となる第2ゲート電圧が入力される第2ゲート電極(82b)と、を有し、
前記ダイオード素子に属する前記ゲート電極は、少なくとも前記第2ゲート電極を含み、前記スイッチング素子に属する前記ゲート電極は、少なくとも前記第1ゲート電極を含み、
前記第1電極と前記第2電極との間を流れる電流に基づいて、前記モード判定部により、前記逆導通モードと判定された際、もしくは、前記逆導通モードか前記順導通モードかを判定できない際、前記第2ゲート電極に、前記第2ゲート電圧が印加される半導体装置。 - 前記ダイオード素子における前記第1不純物領域は、前記第2不純物領域に隣接する位置に第1導電型のバリア領域(75a,92)を有し、
前記ゲート電極に所定のゲート電圧が印加されることにより、前記バリア領域に反転層が生じる、請求項1に記載の半導体装置。 - 前記ダイオード素子は、
前記第1不純物領域にあって、前記第2不純物領域とは離間しつつ前記第1電極と前記第2電極との間の電流経路に形成された第2導通型の第3不純物領域(74a,93)をさらに有する、請求項1または請求項2に記載の半導体装置。 - 前記駆動部は、前記逆導通モードと判定された際、もしくは、前記逆導通モードか前記順導通モードかを判定できない際、ハイレベルとローレベルの2値を少なくとも有しPWM制御されたゲート電圧を前記第2ゲート電極に印加するものであり、
前記ローレベルは、前記第2電極の電位を基準として前記第1ゲート電圧の極性と反対の極性である請求項1〜3のいずれか1項に記載の半導体装置。 - 前記駆動部は、前記逆導通モードと判定された際、もしくは、前記逆導通モードか前記順導通モードかを判定できない際、常に前記第2電極の電位を基準として前記第1ゲート電圧の極性と反対の極性であるゲート電圧を前記第2ゲート電極に印加する請求項1〜3のいずれか1項に記載の半導体装置。
- 前記駆動部は、前記逆導通モードと判定された際、前記第1電極と前記第2電極との間に流れるダイオード電流の大きさが所定の閾値以上の場合に、前記第2電極の電位と同一のゲート電圧を前記第2ゲート電極に印加し、
前記ダイオード電流の大きさが所定の閾値より小さい場合に、前記第2電極の電位を基準として前記第1ゲート電圧の極性と反対の極性であるゲート電圧を前記第2ゲート電極に印加する請求項1〜3のいずれか1項に記載の半導体装置。 - 前記ダイオード素子が形成される領域と、前記スイッチング素子が形成される領域との境界となる混成領域における前記ゲート電極は、前記第2電極の電位を基準として前記第1ゲート電圧の極性と反対の極性であるゲート電圧が印加可能である請求項1〜6のいずれか1項に記載の半導体装置。
- 前記ダイオード素子が形成される領域と、前記スイッチング素子が形成される領域との境界となる混成領域における前記ゲート電極は、前記第1ゲート電圧が印加可能である請求項1〜7のいずれか1項に記載の半導体装置。
- 前記スイッチング素子に属する前記ゲート電極は、前記第2ゲート電極を含む請求項1〜8のいずれか1項に記載の半導体装置。
- 前記駆動部は、前記逆導通モードと判定された際、前記第1ゲート電極に印加されるゲート電圧を前記第2電極の電位と同一とする請求項1〜9のいずれか1項に記載の半導体装置。
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US10312904B2 (en) * | 2015-09-03 | 2019-06-04 | Mitsubishi Electric Corporation | Power converter |
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2016
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- 2016-12-16 WO PCT/JP2016/087505 patent/WO2017130597A1/ja active Application Filing
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11335787B2 (en) | 2019-10-25 | 2022-05-17 | Kabushiki Kaisha Toshiba | Semiconductor device |
US11563112B2 (en) | 2019-11-01 | 2023-01-24 | Kabushiki Kaisha Toshiba | Method for controlling semiconductor device |
US11837654B2 (en) | 2019-11-01 | 2023-12-05 | Kabushiki Kaisha Toshiba | Method for controlling semiconductor device |
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JP2017135255A (ja) | 2017-08-03 |
US20180308757A1 (en) | 2018-10-25 |
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WO2017130597A1 (ja) | 2017-08-03 |
US10438852B2 (en) | 2019-10-08 |
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