JP6729452B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6729452B2 JP6729452B2 JP2017042062A JP2017042062A JP6729452B2 JP 6729452 B2 JP6729452 B2 JP 6729452B2 JP 2017042062 A JP2017042062 A JP 2017042062A JP 2017042062 A JP2017042062 A JP 2017042062A JP 6729452 B2 JP6729452 B2 JP 6729452B2
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- 239000004065 semiconductor Substances 0.000 title claims description 69
- 239000010410 layer Substances 0.000 claims description 149
- 239000000758 substrate Substances 0.000 claims description 23
- 239000002344 surface layer Substances 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 description 31
- 239000002184 metal Substances 0.000 description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 18
- 229920005591 polysilicon Polymers 0.000 description 18
- 238000007689 inspection Methods 0.000 description 13
- 230000004048 modification Effects 0.000 description 13
- 238000012986 modification Methods 0.000 description 13
- 210000000746 body region Anatomy 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
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Description
ドリフト層上に形成された第2導電型のベース層(13)と、
ベース層を貫通してドリフト層に達する複数のトレンチ(14)と、
トレンチに接するように、ベース層の表層部分に形成された第1導電型のエミッタ領域(15)と、
ベース層及びエミッタ領域に接続されたエミッタ電極(20)と、
ドリフト層に対してベース層と反対側に形成された第1導電型のコレクタ層(30)と、
コレクタ層に接続されたコレクタ電極(31)と、
トレンチの壁面に形成されたゲート絶縁膜(17)と、
ゲート絶縁膜を介してトレンチ内に配置されたゲート電極(18)であって、電圧の印加により、エミッタ電極とドリフト層との間を繋ぐ反転層を生じさせる主ゲート電極(18a)、及び、反転層の発生に寄与しないダミーゲート電極(18b)と、
主ゲート電極及びダミーゲート電極に共通のゲートパッド(21a)と、
ダミーゲート電極とゲートパッドとの間に形成され、主ゲート電極に反転層を生じさせるためにゲートパッドに第1電圧が印加されると、ダミーゲート電極が反転層の発生に寄与しないように導通を遮断又は制限し、ゲートパッドに第1電圧とは極性が逆の第2電圧が印加されると、導通を許可する第1素子(24,33)と、
エミッタ電極とダミーゲート電極及び第1素子の接続点との間に形成され、第1電圧が印加されると導通を許可し、第2電圧が印加されると導通を遮断又は制限する第2素子(25,34)と、
を備える。
先ず、図1〜図3に基づき、本実施形態の半導体装置の構成について説明する。図1では、配置を明確化するために、エミッタ電極を破線で示し、ゲート電極、及び、該ゲート電極とパッドとを繋ぐ配線を実線で示している。本実施形態の半導体装置は、たとえばインバータやコンバータなどの電力変換回路に用いられる。本実施形態では、第1導電型をN型、第2導電型をP型としている。
本実施形態は、先行実施形態を参照できる。このため、先行実施形態に示した半導体装置10と共通する部分についての説明は省略する。
本実施形態は、先行実施形態を参照できる。このため、先行実施形態に示した半導体装置10と共通する部分についての説明は省略する。
本実施形態は、先行実施形態を参照できる。このため、先行実施形態に示した半導体装置10と共通する部分についての説明は省略する。
Claims (4)
- 第1導電型のドリフト層(12)を構成する半導体基板(11)と、
前記ドリフト層上に形成された第2導電型のベース層(13)と、
前記ベース層を貫通して前記ドリフト層に達する複数のトレンチ(14)と、
前記トレンチに接するように、前記ベース層の表層部分に形成された第1導電型のエミッタ領域(15)と、
前記ベース層及び前記エミッタ領域に接続されたエミッタ電極(20)と、
前記ドリフト層に対して前記ベース層と反対側に形成された第1導電型のコレクタ層(30)と、
前記コレクタ層に接続されたコレクタ電極(31)と、
前記トレンチの壁面に形成されたゲート絶縁膜(17)と、
前記ゲート絶縁膜を介して前記トレンチ内に配置されたゲート電極(18)であって、電圧の印加により、前記エミッタ電極と前記ドリフト層との間を繋ぐ反転層を生じさせる主ゲート電極(18a)、及び、前記反転層の発生に寄与しないダミーゲート電極(18b)と、
前記主ゲート電極及び前記ダミーゲート電極に共通のゲートパッド(21a)と、
前記ダミーゲート電極と前記ゲートパッドとの間に形成され、前記主ゲート電極に前記反転層を生じさせるために前記ゲートパッドに第1電圧が印加されると、前記ダミーゲート電極が前記反転層の発生に寄与しないように導通を遮断又は制限し、前記ゲートパッドに前記第1電圧とは極性が逆の第2電圧が印加されると、導通を許可する第1素子(24,33)と、
前記エミッタ電極と前記ダミーゲート電極及び前記第1素子の接続点との間に形成され、前記第1電圧が印加されると導通を許可し、前記第2電圧が印加されると導通を遮断又は制限する第2素子(25,34)と、
を備える半導体装置。 - 前記第1素子及び前記第2素子はともにダイオードであり、アノード同士が互いに接続されている請求項1に記載の半導体装置。
- 前記ダミーゲート電極を複数有し、
複数の前記ダミーゲート電極の少なくとも一部が、前記コレクタ層の上方に形成されている請求項1または請求項2に記載の半導体装置。 - 前記ドリフト層に対して前記ベース層と反対側に形成され、前記コレクタ層と並設された第1導電型のカソード層(39)をさらに備え、
前記コレクタ電極は、前記コレクタ層及び前記カソード層に接続されており、
前記ダミーゲート電極を複数有し、
前記半導体基板が、IGBT素子として動作するIGBT領域(11c)と、ダイオード素子として動作するダイオード領域(11d)と、を有し、
前記トレンチは、前記IGBT領域及び前記ダイオード領域にそれぞれ形成され、
複数の前記ダミーゲート電極の少なくとも一部が、前記ダイオード領域に形成されている請求項1〜3いずれか1項に記載の半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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JP2017042062A JP6729452B2 (ja) | 2017-03-06 | 2017-03-06 | 半導体装置 |
PCT/JP2018/001883 WO2018163624A1 (ja) | 2017-03-06 | 2018-01-23 | 半導体装置 |
CN201880004460.8A CN109983565B (zh) | 2017-03-06 | 2018-01-23 | 半导体装置 |
US16/358,756 US10840364B2 (en) | 2017-03-06 | 2019-03-20 | Semiconductor device |
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JP2017042062A JP6729452B2 (ja) | 2017-03-06 | 2017-03-06 | 半導体装置 |
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JP2018148044A JP2018148044A (ja) | 2018-09-20 |
JP2018148044A5 JP2018148044A5 (ja) | 2019-02-14 |
JP6729452B2 true JP6729452B2 (ja) | 2020-07-22 |
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JP (1) | JP6729452B2 (ja) |
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WO (1) | WO2018163624A1 (ja) |
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JP6946219B2 (ja) * | 2018-03-23 | 2021-10-06 | 株式会社東芝 | 半導体装置 |
JP7293592B2 (ja) * | 2018-09-14 | 2023-06-20 | 富士電機株式会社 | 半導体素子及び半導体装置 |
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