JP2001274355A - 半導体記憶装置及びデータ処理装置 - Google Patents

半導体記憶装置及びデータ処理装置

Info

Publication number
JP2001274355A
JP2001274355A JP2001008434A JP2001008434A JP2001274355A JP 2001274355 A JP2001274355 A JP 2001274355A JP 2001008434 A JP2001008434 A JP 2001008434A JP 2001008434 A JP2001008434 A JP 2001008434A JP 2001274355 A JP2001274355 A JP 2001274355A
Authority
JP
Japan
Prior art keywords
semiconductor memory
memory cell
semiconductor
memory device
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2001008434A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001274355A5 (enExample
Inventor
Tomoyuki Ishii
智之 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2001008434A priority Critical patent/JP2001274355A/ja
Publication of JP2001274355A publication Critical patent/JP2001274355A/ja
Publication of JP2001274355A5 publication Critical patent/JP2001274355A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/18—Peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/02—Structural aspects of erasable programmable read-only memories
    • G11C2216/06—Floating gate cells in which the floating gate consists of multiple isolated silicon islands, e.g. nanocrystals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
JP2001008434A 2000-01-18 2001-01-17 半導体記憶装置及びデータ処理装置 Withdrawn JP2001274355A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001008434A JP2001274355A (ja) 2000-01-18 2001-01-17 半導体記憶装置及びデータ処理装置

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2000013893 2000-01-18
JP2000-13893 2000-01-18
JP2001008434A JP2001274355A (ja) 2000-01-18 2001-01-17 半導体記憶装置及びデータ処理装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2009142286A Division JP2009260364A (ja) 2000-01-18 2009-06-15 半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2001274355A true JP2001274355A (ja) 2001-10-05
JP2001274355A5 JP2001274355A5 (enExample) 2006-03-23

Family

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Family Applications (2)

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JP2001008434A Withdrawn JP2001274355A (ja) 2000-01-18 2001-01-17 半導体記憶装置及びデータ処理装置
JP2009142286A Pending JP2009260364A (ja) 2000-01-18 2009-06-15 半導体記憶装置

Family Applications After (1)

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Country Status (4)

Country Link
US (5) US6839260B2 (enExample)
JP (2) JP2001274355A (enExample)
KR (1) KR100817657B1 (enExample)
TW (1) TW587252B (enExample)

Cited By (31)

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JP2001358315A (ja) * 2000-04-14 2001-12-26 Infineon Technologies Ag Ｍｒａｍメモリ
JP2005353912A (ja) * 2004-06-11 2005-12-22 Renesas Technology Corp 半導体記憶装置
JP2007172826A (ja) * 2001-07-17 2007-07-05 Sanyo Electric Co Ltd 半導体メモリ装置
JP2008527585A (ja) * 2004-12-30 2008-07-24 サンディスク・スリー・ディ・リミテッド・ライアビリティ・カンパニー 複数ヘッドデコーダの複数のレベルを使用した高密度メモリアレイの階層復号化のための機器および方法
JP2008529270A (ja) * 2005-01-25 2008-07-31 ノーザン ライツ セミコンダクター コーポレイション 磁気抵抗メモリを有するシングルチップ
JP2008529275A (ja) * 2005-01-26 2008-07-31 フリースケール セミコンダクター インコーポレイテッド 窒化酸化物層を有する半導体デバイスおよびこのための方法
JP2008192277A (ja) * 2007-01-31 2008-08-21 Northern Lights Semiconductor Corp 磁性メモリを備えた集積回路
JP2009099814A (ja) * 2007-10-17 2009-05-07 Spansion Llc 半導体装置
JP2010146722A (ja) * 2002-01-18 2010-07-01 Sandisk Corp 複数読出しにより不揮発性メモリにおけるノイズの影響を低減する方法
US7916538B2 (en) 2008-01-28 2011-03-29 Samsung Electronics Co., Ltd. Memory device employing NVRAM and flash memory cells
JP2011165240A (ja) * 2010-02-05 2011-08-25 Toshiba Corp 半導体記憶装置
JP2011228709A (ja) * 2010-04-20 2011-11-10 Micron Technology Inc マルチレベルアーキテクチャを有するフラッシュメモリ
JP2012501038A (ja) * 2008-08-25 2012-01-12 サンディスク スリーディー，エルエルシー 区分データ線を有するメモリシステム
JP2012178554A (ja) * 2011-02-02 2012-09-13 Semiconductor Energy Lab Co Ltd 半導体メモリ装置
JP2012178555A (ja) * 2011-02-02 2012-09-13 Semiconductor Energy Lab Co Ltd 半導体メモリ装置
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JP2013145875A (ja) * 2011-12-15 2013-07-25 Semiconductor Energy Lab Co Ltd 記憶装置
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JP2016187047A (ja) * 2010-09-13 2016-10-27 株式会社半導体エネルギー研究所 記憶装置
JP2017092492A (ja) * 2009-12-25 2017-05-25 株式会社半導体エネルギー研究所 半導体装置
JP2017527976A (ja) * 2014-06-16 2017-09-21 インテル・コーポレーション 高電圧デバイスを集積させたシリコンダイ
JPWO2016181256A1 (ja) * 2015-05-12 2018-03-08 株式会社半導体エネルギー研究所 半導体装置、電子部品および電子機器
JP2018041985A (ja) * 2010-09-14 2018-03-15 株式会社半導体エネルギー研究所 半導体装置
JP2019091914A (ja) * 2012-02-29 2019-06-13 株式会社半導体エネルギー研究所 半導体装置
JP2019179925A (ja) * 2010-07-02 2019-10-17 株式会社半導体エネルギー研究所 半導体装置
JP2020150282A (ja) * 2011-03-10 2020-09-17 株式会社半導体エネルギー研究所 メモリ装置
JP2021044045A (ja) * 2019-09-13 2021-03-18 本田技研工業株式会社 半導体装置
JP2022529165A (ja) * 2019-04-30 2022-06-17 長江存儲科技有限責任公司 ３次元相変化メモリを伴う３次元メモリデバイス
JP2022153594A (ja) * 2011-01-26 2022-10-12 株式会社半導体エネルギー研究所 半導体装置

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