JP2009099814A - 半導体装置 - Google Patents
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- JP2009099814A JP2009099814A JP2007270745A JP2007270745A JP2009099814A JP 2009099814 A JP2009099814 A JP 2009099814A JP 2007270745 A JP2007270745 A JP 2007270745A JP 2007270745 A JP2007270745 A JP 2007270745A JP 2009099814 A JP2009099814 A JP 2009099814A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 230000015654 memory Effects 0.000 claims abstract description 218
- 239000000758 substrate Substances 0.000 claims description 14
- 230000008859 change Effects 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 229910000314 transition metal oxide Inorganic materials 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 91
- 238000009792 diffusion process Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000014759 maintenance of location Effects 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 150000004770 chalcogenides Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000012782 phase change material Substances 0.000 description 2
- 230000006378 damage Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/10—Phase change RAM [PCRAM, PRAM] devices
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Abstract
【解決手段】抵抗値の変化によりデータを記憶する不揮発性の第1可変抵抗素子REx、及び第1可変抵抗素子RExを選択する選択トランジスタTRを含む第1メモリセルMCxと、複数の第1メモリセルMCxが平面状に配列して設けられた第1メモリ層12と、抵抗値の変化によりデータを記憶する不揮発性の第2可変抵抗素子REz、及び第2可変抵抗素子REzを選択する選択ダイオードSDを含む第2メモリセルMCzと、複数の第2メモリセルMCzが平面状に配列して設けられた第2メモリ層14と、を具備し、複数の第2メモリ層14が、第1メモリ層12の上方に積層して設けられていることを特徴とする半導体装置。
【選択図】図1
Description
12 第1メモリ層
14 第2メモリ層
20 制御部
22 アドレスデコーダ
24 昇圧回路
26 入出力回路
30 半導体基板
32 ビットラインコンタクト
34 ソースラインコンタクト
36 ゲート
38 ワードラインコンタクト
40 拡散領域(ドレイン側)
41 拡散領域(ソース側)
42 導電部材
46 P型ウェル
50 トランジスタ層
52 可変抵抗素子層
60 電極
Claims (12)
- 抵抗値の変化によりデータを記憶する不揮発性の第1可変抵抗素子、及び前記第1可変抵抗素子を選択する選択トランジスタを含む第1メモリセルと、
複数の前記第1メモリセルが平面状に配列して設けられた第1メモリ層と、
抵抗値の変化によりデータを記憶する不揮発性の第2可変抵抗素子、及び前記第2可変抵抗素子を選択する選択ダイオードを含む第2メモリセルと、
複数の前記第2メモリセルが平面状に配列して設けられた第2メモリ層と、
を具備し、
複数の前記第2メモリ層が、前記第1メモリ層の上方に積層して設けられていることを特徴とする半導体装置。 - 前記第2メモリセルは、前記第1メモリ層及び前記第2メモリ層の積層方向に、前記可変抵抗素子及び前記選択ダイオードが積層してなることを特徴とする請求項1に記載の半導体装置。
- 前記第2メモリセルは、前記第1メモリ層及び前記第2メモリ層の積層方向から見た場合の面積が、前記第1メモリセルより小さいことを特徴とする請求項1または2に記載の半導体装置。
- 前記第2メモリ層は、
複数の第2ビットラインと、
前記複数の第2ビットラインに対し交差する方向に設けられた複数の第2ワードラインと、
を含み、
前記第2メモリセルは、前記第2ビットラインと前記第2ワードラインとの交差領域に設けられ、その一端が前記第2ビットラインに、他端が前記第2ワードラインに接続され、
前記複数の第2メモリ層のうち上下方向に隣接する2つの第2メモリ層は、前記第2ビットライン及び前記第2ワードラインのいずれかを共有する、
ことを特徴とする請求項1から3のうちいずれか1項に記載の半導体装置。 - 前記複数の第2メモリ層のうち上下方向に隣接する2つの第2メモリ層のうち、上側の層に含まれる前記第2メモリセルと、下側の層に含まれる前記第2メモリセルとは、最小加工寸法の半分の寸法だけずらして設けられていることを特徴とする請求項4に記載の半導体装置。
- 前記第1メモリセルは、
1つの前記選択トランジスタと、
前記選択トランジスタのドレイン端子またはソース端子に接続された1つの前記第1可変抵抗素子と、
からなることを特徴とする請求項1から5のうちいずれか1項に記載の半導体装置。 - 前記第1メモリ層及び前記第2メモリ層を支持する半導体基板を具備し、
前記選択トランジスタの少なくとも一部は、前記半導体基板内に形成されていることを特徴とする請求項1から6のうちいずれか1項に記載の半導体装置。 - 前記第1メモリ層は、
前記選択トランジスタが形成された選択トランジスタ層と、
前記選択トランジスタ層の上方に形成され、前記第1可変抵抗素子が形成された第1可変抵抗素子層と、
を含むことを特徴とする請求項1から7のうちいずれか1項に記載の半導体装置。 - 前記第1メモリ層は、
複数の第1ビットラインと、
前記複数の第1ビットラインに対し交差する方向に設けられた複数の第1ワードラインと、
前記複数の第1ビットラインに沿った方向に設けられた複数のソースラインと、
を含み、
前記第1メモリセルは、前記第1ビットラインと前記第1ワードラインとの交差領域に設けられ、その一端が前記第1ビットラインに、他端が前記ソースラインに接続され、
前記複数の第1メモリセルのうち隣接する2つの第1メモリセルは、前記ソースラインを共有している、
ことを特徴とする請求項1から8のうちいずれか1項に記載の半導体装置。 - 前記可変抵抗素子は、遷移金属酸化物からなることを特徴とする請求項1から9のうちいずれか1項に記載の半導体装置。
- 前記選択ダイオードは、前記遷移金属酸化物と金属電極からなるショットキーダイオードであることを特徴とする請求項10に記載の半導体装置。
- 前記第1メモリセルは、電源投入時に読み出されるブートプログラム、及びOSプログラムのうち少なくとも一方を含むデータを記憶することを特徴とする請求項1から11のうちいずれか1項に記載の半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007270745A JP5557419B2 (ja) | 2007-10-17 | 2007-10-17 | 半導体装置 |
US12/253,619 US7894238B2 (en) | 2007-10-17 | 2008-10-17 | Semiconductor memory device with stacked memory cell structure |
US13/005,456 US8289750B2 (en) | 2007-10-17 | 2011-01-12 | Semiconductor memory device featuring selective data storage in a stacked memory cell structure |
US13/622,796 US8773885B2 (en) | 2007-10-17 | 2012-09-19 | Semiconductor memory device featuring selective data storage in a stacked memory cell structure |
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JP2007270745A JP5557419B2 (ja) | 2007-10-17 | 2007-10-17 | 半導体装置 |
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JP2009099814A true JP2009099814A (ja) | 2009-05-07 |
JP5557419B2 JP5557419B2 (ja) | 2014-07-23 |
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JP2007270745A Active JP5557419B2 (ja) | 2007-10-17 | 2007-10-17 | 半導体装置 |
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JP (1) | JP5557419B2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US8477524B2 (en) | 2009-12-25 | 2013-07-02 | Samsung Electronics Co., Ltd. | Nonvolatile memory devices and related methods and systems |
KR20150033948A (ko) * | 2013-09-25 | 2015-04-02 | 에스케이하이닉스 주식회사 | 전자 장치 |
Families Citing this family (14)
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US20070192132A1 (en) | 2006-02-10 | 2007-08-16 | Debra Thesman | System and method of prioritizing and administering healthcare to patients having multiple integral diagnoses |
JP5557419B2 (ja) | 2007-10-17 | 2014-07-23 | スパンション エルエルシー | 半導体装置 |
JP5198146B2 (ja) * | 2008-05-22 | 2013-05-15 | 株式会社東芝 | 不揮発性記憶装置 |
US8223525B2 (en) * | 2009-12-15 | 2012-07-17 | Sandisk 3D Llc | Page register outside array and sense amplifier interface |
JP5732827B2 (ja) * | 2010-02-09 | 2015-06-10 | ソニー株式会社 | 記憶素子および記憶装置、並びに記憶装置の動作方法 |
JP5295991B2 (ja) * | 2010-02-15 | 2013-09-18 | 株式会社東芝 | 不揮発性半導体記憶装置、及び不揮発性半導体記憶装置の制御方法 |
KR20120114611A (ko) * | 2011-04-07 | 2012-10-17 | 에스케이하이닉스 주식회사 | 자화성 저장 소자를 구비한 반도체 메모리 장치 및 그 구동방법 |
US20120329015A1 (en) | 2011-06-24 | 2012-12-27 | Debra Thesman | Hierarchical condition categories program |
US10424032B2 (en) | 2012-12-12 | 2019-09-24 | Quality Standards, Llc | Methods for administering preventative healthcare to a patient population |
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JP5557419B2 (ja) | 2014-07-23 |
US8773885B2 (en) | 2014-07-08 |
US7894238B2 (en) | 2011-02-22 |
US20120014162A1 (en) | 2012-01-19 |
US20130016552A1 (en) | 2013-01-17 |
US8289750B2 (en) | 2012-10-16 |
US20090262569A1 (en) | 2009-10-22 |
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