DE60044974D1 - Mehrschichtige leiterplatte und leiterplatten-herstellungsmethode - Google Patents

Mehrschichtige leiterplatte und leiterplatten-herstellungsmethode

Info

Publication number
DE60044974D1
DE60044974D1 DE60044974T DE60044974T DE60044974D1 DE 60044974 D1 DE60044974 D1 DE 60044974D1 DE 60044974 T DE60044974 T DE 60044974T DE 60044974 T DE60044974 T DE 60044974T DE 60044974 D1 DE60044974 D1 DE 60044974D1
Authority
DE
Germany
Prior art keywords
conductor plate
multilayer
manufacturing
plate manufacturing
multilayer conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60044974T
Other languages
English (en)
Inventor
Hui Zhong
Kenichi Shimada
Yukihiko Toyoda
Motoo Asai
Dongdong Wang
Koji Sekine
Yoshitaka Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP22885299A external-priority patent/JP2001053448A/ja
Priority claimed from JP11230875A external-priority patent/JP2001057466A/ja
Priority claimed from JP26693299A external-priority patent/JP2001094263A/ja
Priority claimed from JP26932099A external-priority patent/JP2001094239A/ja
Priority claimed from JP2000102769A external-priority patent/JP4535559B2/ja
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Application granted granted Critical
Publication of DE60044974D1 publication Critical patent/DE60044974D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/285—Permanent coating compositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
DE60044974T 1999-08-12 2000-07-28 Mehrschichtige leiterplatte und leiterplatten-herstellungsmethode Expired - Lifetime DE60044974D1 (de)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP22885299A JP2001053448A (ja) 1999-08-12 1999-08-12 プリント配線板、ソルダーレジスト樹脂組成物およびプリント配線板の製造方法
JP11230875A JP2001057466A (ja) 1999-08-17 1999-08-17 プリント配線板、ソルダーレジスト樹脂組成物およびプリント配線板の製造方法
JP26693299A JP2001094263A (ja) 1999-09-21 1999-09-21 多層プリント配線板および半導体装置
JP26932099A JP2001094239A (ja) 1999-09-22 1999-09-22 多層プリント配線板および半導体装置
JP2000102769A JP4535559B2 (ja) 2000-04-04 2000-04-04 多層プリント配線板
PCT/JP2000/005044 WO2001013686A1 (fr) 1999-08-12 2000-07-28 Carte de circuits imprimes multicouches, composition d'epargne de soudage, procede de fabrication de ladite carte imprimee et dispositif semi-conducteur

Publications (1)

Publication Number Publication Date
DE60044974D1 true DE60044974D1 (de) 2010-10-28

Family

ID=27529834

Family Applications (2)

Application Number Title Priority Date Filing Date
DE60044974T Expired - Lifetime DE60044974D1 (de) 1999-08-12 2000-07-28 Mehrschichtige leiterplatte und leiterplatten-herstellungsmethode
DE60045173T Expired - Lifetime DE60045173D1 (de) 1999-08-12 2000-07-28 Mehrschichtige Leiterplatte mit einer Lötstoppzusammensetzung

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE60045173T Expired - Lifetime DE60045173D1 (de) 1999-08-12 2000-07-28 Mehrschichtige Leiterplatte mit einer Lötstoppzusammensetzung

Country Status (6)

Country Link
US (3) US7916492B1 (de)
EP (4) EP1211920B1 (de)
CN (3) CN101925260A (de)
DE (2) DE60044974D1 (de)
TW (5) TWI233327B (de)
WO (1) WO2001013686A1 (de)

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US7371974B2 (en) 2001-03-14 2008-05-13 Ibiden Co., Ltd. Multilayer printed wiring board
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JP4478115B2 (ja) * 2006-01-27 2010-06-09 三共化成株式会社 導電性回路の形成方法
KR100771467B1 (ko) * 2006-10-30 2007-10-30 삼성전기주식회사 회로기판 및 그 제조방법
TWI316381B (en) * 2007-01-24 2009-10-21 Phoenix Prec Technology Corp Circuit board and fabrication method thereof
JP5154819B2 (ja) * 2007-04-03 2013-02-27 新光電気工業株式会社 基板及びその製造方法
US8440916B2 (en) * 2007-06-28 2013-05-14 Intel Corporation Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method
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CN103118496B (zh) * 2013-01-25 2016-02-17 广东生益科技股份有限公司 一种改善厚铜印制电路板阻焊开裂的方法
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JP2015231003A (ja) * 2014-06-06 2015-12-21 イビデン株式会社 回路基板および回路基板の製造方法
CN104320920B (zh) * 2014-10-13 2017-05-10 北京卫星制造厂 一种基于低内应力的电子产品涂覆方法
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KR102295103B1 (ko) * 2015-02-24 2021-08-31 삼성전기주식회사 회로기판 및 회로기판 조립체
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JP2018014446A (ja) * 2016-07-22 2018-01-25 イビデン株式会社 ソルダーレジスト及びプリント配線板
US10849233B2 (en) 2017-07-10 2020-11-24 Catlam, Llc Process for forming traces on a catalytic laminate
WO2018101404A1 (ja) * 2016-12-02 2018-06-07 株式会社アルバック 配線基板の加工方法
US10349520B2 (en) 2017-06-28 2019-07-09 Catlam, Llc Multi-layer circuit board using interposer layer and conductive paste
US10765012B2 (en) 2017-07-10 2020-09-01 Catlam, Llc Process for printed circuit boards using backing foil
DE102017217815A1 (de) * 2017-10-06 2019-04-11 Conti Temic Microelectronic Gmbh Verfahren zum Herstellen einer elektronischen Komponente, elektronische Komponente und Lötstopplack
US10670964B2 (en) 2017-11-21 2020-06-02 International Business Machines Corporation Ruggedized solder mask material
US10827624B2 (en) 2018-03-05 2020-11-03 Catlam, Llc Catalytic laminate with conductive traces formed during lamination
CN113423750B (zh) * 2019-02-12 2023-11-21 纳美仕有限公司 光固化性树脂组合物和使其固化而得到的固化物
EP3709779A1 (de) * 2019-03-12 2020-09-16 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Komponententräger und verfahren zur herstellung davon
KR102633142B1 (ko) * 2019-08-26 2024-02-02 삼성전자주식회사 반도체 패키지
KR20220097718A (ko) 2020-12-31 2022-07-08 삼성전자주식회사 배선 기판 및 이를 포함하는 반도체 모듈
CN113194626A (zh) * 2021-04-02 2021-07-30 惠州美锐电子科技有限公司 一种pcb板的生产方法

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Also Published As

Publication number Publication date
EP2053908B1 (de) 2011-12-21
US7916492B1 (en) 2011-03-29
TW200410606A (en) 2004-06-16
TWI236327B (en) 2005-07-11
TWI235633B (en) 2005-07-01
EP1211920A4 (de) 2007-02-28
TW200410622A (en) 2004-06-16
CN100387103C (zh) 2008-05-07
TWI233327B (en) 2005-05-21
CN1378769A (zh) 2002-11-06
EP2053908A1 (de) 2009-04-29
EP1211920B1 (de) 2010-09-15
TW200410618A (en) 2004-06-16
US20080041615A1 (en) 2008-02-21
US20100163288A1 (en) 2010-07-01
TW200410623A (en) 2004-06-16
EP1211920A1 (de) 2002-06-05
TWI235632B (en) 2005-07-01
US7910836B2 (en) 2011-03-22
CN1553761A (zh) 2004-12-08
CN101925260A (zh) 2010-12-22
WO2001013686A1 (fr) 2001-02-22
TWI236317B (en) 2005-07-11
EP2028915A1 (de) 2009-02-25
DE60045173D1 (de) 2010-12-09
EP2053909A1 (de) 2009-04-29
EP2053909B1 (de) 2010-10-27

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