TWI640990B - 升壓保護電路 - Google Patents

升壓保護電路 Download PDF

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TWI640990B
TWI640990B TW106107166A TW106107166A TWI640990B TW I640990 B TWI640990 B TW I640990B TW 106107166 A TW106107166 A TW 106107166A TW 106107166 A TW106107166 A TW 106107166A TW I640990 B TWI640990 B TW I640990B
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Taiwan
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transistor
voltage
terminal
boosted
protection circuit
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TW106107166A
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TW201826277A (zh
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李玠澤
陳致均
黃正達
林俊宏
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力旺電子股份有限公司
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    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
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    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
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    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
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  • Power Engineering (AREA)
  • Quality & Reliability (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Semiconductor Integrated Circuits (AREA)
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Abstract

升壓保護電路包含第一電晶體、第二電晶體、第三電晶體及第四電晶體。第一電晶體、第二電晶體及第四電晶體的第一端耦接，用以接收寫入電壓。第三電晶體的控制端用以接收工作電壓。第四電晶體的第二端用以在第四電晶體導通時輸出寫入電壓。當寫入電壓非預期地升壓且工作電壓未升壓時，第一電晶體為導通，第二電晶體為截止，及該第四電晶體為截止，以避免第四電晶體之第二端輸出寫入電壓。

Description

升壓保護電路
本發明描述了一種升壓保護電路，尤指一種具有避免非預期升壓功能的升壓保護電路 。
非揮發性記憶體(Non-Volatile Memory，NVM)是一種在沒有電力供應至記憶體區塊的情況下，仍然能夠維持原本儲存之資料的記憶體。非揮發性記憶體可應用於許多設備，例如磁性裝置、光碟片、快閃記憶體或是其它半導體製程的記憶裝置。非揮發性記憶體可分為電子式尋址系統(Electrically Addressed Systems)的記憶體，例如唯讀記憶體(Read-Only Memory)，以及機械式尋址系統(Mechanically Addressed Systems)的記憶體，例如硬碟、光碟、磁帶等裝置。並且，非揮發性記憶體不需要將本身儲存之資料做週期性地更新。因此，非揮發性記憶體常被用來當成備份資料的裝置或是能長時間儲存資料的裝置。
為了驅動非揮發性記憶體的內部電路，各種不同的電壓會被依序用來控制以及致能非揮發性記憶體。舉例而言，輸入至內部電路的工作電壓可被用來控制內部電路的核心電路(Core Circuit)。輸入至內部電路的輸入/輸出電壓(I/O Voltage)可被用來控制內部電路的輸入/輸出裝置。輸入至內部電路的寫入電壓可被用來控制內部電路的資料存取操作。藉由適當調整這些不同的電壓，非揮發性記憶體即可正常地被驅動。並且，在這些電壓中，內部電路的工作電壓必須要先被升壓。
在非揮發性記憶體的內部電路中，當輸入的電壓非預期地升壓時(例如寫入電壓非預期地升壓)，且工作電壓尚未升壓時(例如寫入電壓在工作電壓之前就升壓)，非揮發性記憶體的內部電路就會進入異常的操作狀態，將導致功率消耗以及電路發生干擾等現象。
本發明一實施例提出一種升壓保護電路，包含第一電晶體、第二電晶體、第三電晶體及第四電晶體。第一電晶體包含用以接收寫入電壓的第一端、控制端、及第二端。第二電晶體包含耦接於第一電晶體之第一端的第一端、耦接於第一電晶體之第二端的控制端、及耦接於第一電晶體之控制端的第二端。第三電晶體包含耦接於第一電晶體之第二端的第一端、用以接收工作電壓的控制端、及用以接收接地電壓的第二端。第四電晶體包含耦接於第二電晶體之第一端的第一端、耦接於第一電晶體之第二端的控制端、及用以在第四電晶體導通時輸出寫入電壓的第二端。
本發明另一實施例提出一種升壓保護電路，包含第一電晶體、電容、第二電晶體、第三電晶體、第四電晶體、第五電晶體、以及第六電晶體。第一電晶體包含用以接收寫入電壓的第一端、控制端、及第二端。電容包含耦接於第一電晶體之第一端的第一端、及耦接於第一電晶體之第二端的第二端。第二電晶體包含耦接於第一電晶體之第一端的第一端、耦接於第一電晶體之第二端的控制端、及耦接於第一電晶體之控制端的第二端。第三電晶體包含耦接於第一電晶體之第二端的第一端、用以接收工作電壓的控制端、以及用以接收接地電壓的第二端。第四電晶體包含耦接於第一電晶體之第一端的第一端、耦接於第二電晶體之第二端的控制端、及第二端。第五電晶體包含耦接於第四電晶體之第二端的第一端、用於接收工作電壓的控制端、及用以接收接地電壓的第二端。第六電晶體包含耦接於第一電晶體之第一端的第一端、耦接於第五電晶體之第一端的控制端、及用以在第六電晶體導通時輸出寫入電壓的第二端。
本發明另一實施例提出一種升壓串列系統，包含至少一個升壓保護電路以及內部電路。至少一個升壓保護電路用以接收至少一個驅動電壓，並據以輸出至少一個輸出電壓。內部電路耦接於至少一個升壓保護電路，用以接收一個工作電壓及至少一個輸出電壓。當驅動電壓非預期地升壓且工作電壓尚未升壓時，對應的升壓保護電路執行電路保護功能，以避免驅動電壓輸出至內部電路。
第1圖係為升壓保護電路100之第一實施例的電路圖。升壓保護電路100包含第一電晶體T101、第二電晶體T102、第三電晶體T103及第四電晶體T104。第一電晶體T101包含用以接收寫入電壓VPP的第一端、控制端、及第二端。第二電晶體T102包含耦接於第一電晶體T101之第一端的第一端、耦接於第一電晶體T101之第二端的控制端、及耦接於第一電晶體T101之控制端的第二端。第三電晶體T103包含耦接於第一電晶體T101之第二端的第一端、用以接收工作電壓VDD的控制端、及用以接收接地電壓VSS的第二端。第四電晶體T104包含耦接於第二電晶體T102之第一端的第一端、耦接於第一電晶體T101之第二端的控制端、及用以在第四電晶體T104導通時輸出寫入電壓VPP的第二端。第四電晶體T104的控制端電壓的代號為PWRBLK，下文稱為：電壓PWRBLK。第一電晶體T101的控制端電壓的代號為ZPWRBLK，下文稱為：電壓ZPWRBLK。為了避免混淆，第四電晶體T104之第二端所輸出的電壓之代號為VPPIN，下文稱為：電壓VPPIN。換句話說，當第四電晶體T104導通時，電壓VPPIN會相等於寫入電壓VPP。當第四電晶體T104截止時，電壓VPPIN可為低電壓或是為浮接狀態的電壓。並且，第四電晶體T104的第二端耦接於內部電路10。因此，內部電路10可接收第四電晶體T104之第二端的電壓VPPIN。再者，於升壓保護電路100中，第一電晶體T101、第二電晶體T102、及第四電晶體T104可為P型金屬氧化物半導體場效電晶體。第三電晶體T103可為N型金屬氧化物半導體場效電晶體。在其他實施例中，這些半導體場效電晶體可為輸入/輸出裝置(I/O Devices)。並且，輸入/輸出裝置的閘極氧化層的厚度可以比半導體場效電晶體的閘極氧化層的厚度要大。當寫入電壓VPP非預期地升壓且工作電壓VDD尚未升壓時，升壓保護電路100可執行電路保護功能。當工作電壓VDD升壓時，升壓保護電路100可視為旁路電路而可忽略。以下將說明升壓保護電路100的操作模式。
在初始狀態，工作電壓VDD在低電壓(可為浮接狀態的電壓或是近似於接地電壓VSS)。因此，第三電晶體T103會被截止。電壓ZPWRBLK以及電壓PWRBLK的初始狀態也會在低電壓。當寫入電壓VPP非預期地升壓，且工作電壓VDD尚未升壓時(異常狀態)，電壓ZPWRBLK以及電壓PWRBLK會透過第一電晶體T101以及第二電晶體T102逐漸升壓。此時，在第四電晶體T104之第一端與控制端之間會產生寄生電容Cgs。由於寄生電容Cgs具可充電特性並且可視為耦合電導元件，因此電壓PWRBLK的升壓速度會比電壓ZPWRBLK的升壓速度要快。在升壓保護電路100中，當電壓PWRBLK升壓而滿足VPP-PWRBLK＜|Vthp|的條件時，第二電晶體T102將會截止。電壓Vthp的定義為第二電晶體T102的臨界電壓。隨後，電壓ZPWRBLK會固定在一個比電壓PWRBLK要小的穩態電壓上，因此第一電晶體T101將保持持續導通的狀態。舉例而言，當電壓PWRBLK升壓至趨近於寫入電壓VPP(例如7.5伏特)，電壓ZPWRBLK會固定在一個約為寫入電壓VPP的一半之穩態電壓上(例如3.42~3.75伏特)。因為電壓PWRBLK可升壓至趨近於寫入電壓VPP，第四電晶體T104會在截止狀態。因此，寫入電壓VPP將可以被截止的第四電晶體T104阻隔，而不會由第四電晶體T104的第一端進入第二端。換句話說，第四電晶體T104的第二端將可避免輸出非預期升壓的寫入電壓VPP。因此，對於升壓保護電路100而言，功率消耗以及電路發生干擾等現象的風險將可以降低。簡言之，當寫入電壓VPP非預期地升壓，且工作電壓VDD尚未升壓時，第一電晶體T101為導通，第二電晶體T102為截止，及第四電晶體T104為截止，以避免第四電晶體T104之第二端輸出寫入電壓VPP至內部電路10。
當工作電壓VDD已經升壓且寫入電壓VPP尚未升壓時(正常狀態)，第三電晶體T103會是導通狀態。之後，電壓PWRBLK會下拉至趨近於接地電壓VSS，這將導致第二電晶體T102被導通。由於第二電晶體T102被導通，因此寫入電壓VPP將可透過第二電晶體T102傳輸。然而，由於寫入電壓VPP尚未升壓(可為浮接狀態的電壓或是近似於接地電壓VSS)，第一電晶體T101將維持導通，因此低電壓的寫入電壓VPP將會透過第一電晶體T101及第三電晶體T103保持與接地電壓VSS相同的低電位。由於電壓PWRBLK已經被下拉至趨近於接地電壓VSS，因此第四電晶體T104會被導通。在第四電晶體T104被導通後，寫入電壓VPP將可透過第四電晶體T104傳輸至內部電路10。換句話說，當工作電壓VDD已經升壓且寫入電壓VPP尚未升壓時，由於第四電晶體T104為導通狀態，升壓保護電路100可視為一個旁路電路。亦即，寫入電壓VPP可直接透過第四電晶體T101輸出至內部電路10。
當工作電壓VDD已經升壓且寫入電壓VPP也已經升壓時(正常狀態)，第三電晶體T103會是導通狀態。之後，電壓PWRBLK會下拉至趨近於接地電壓VSS，這將導致第二電晶體T102被導通。由於第二電晶體T102被導通，因此寫入電壓VPP將可透過第二電晶體T102傳輸。然而，由於寫入電壓VPP在工作電壓VDD升壓時也已經升壓，電壓ZPWBLK會透過第二電晶體T102被升壓至趨近於寫入電壓VPP。之後，由於電壓ZPWBLK被升壓至趨近於寫入電壓VPP，因此第一電晶體T101會被截止，這將導致電壓PWRBLK會維持與接地電壓VSS相近的電位。由於電壓PWRBLK會維持與接地電壓VSS相近的電位，因此第四電晶體T104會被導通。因此，第四電晶體T104之第二端的電壓VPPIN會約略等於寫入電壓VPP(例如7.5伏特)。換句話說，當工作電壓VDD已經升壓且寫入電壓VPP也已經升壓時，由於第四電晶體T104為導通狀態，升壓保護電路100可視為一個旁路電路。亦即，寫入電壓VPP可直接透過第四電晶體T104輸出至內部電路10。
為了增加升壓保護電路100的效能(例如降低電路的反應時間)，升壓保護電路100也可引入電容C。第2圖係為升壓保護電路200之第二實施例的電路圖。升壓保護電路200的電路架構類似於升壓保護電路100的電路架構。升壓保護電路200內之第一電晶體T101、第二電晶體T102、第三電晶體T103、及第四電晶體T104的佈局方式和電路元件相同於升壓保護電路100，因此電路元件的符號將沿用升壓保護電路100。升壓保護電路200與升壓保護電路100的差異之處在於，升壓保護電路200之第一電晶體T101的第一端以及第二端之間耦接了電容C。詳細地說，電容C包含耦接於第一電晶體T101之第一端的第一端，以及耦接於第一電晶體T101之第二端的第二端。電容C可為金屬氧化物半導體(Metal-Oxide-Semiconductor)電容。升壓保護電路200的操作模式類似於升壓保護電路100的操作模式。在升壓保護電路200中，當寫入電壓VPP非預期地升壓，且工作電壓VDD尚未升壓時，由於電容C與寄生電容Cgs的共同耦合效應，電壓PWRBLK會快速地升壓。換句話說，升壓保護電路200利用耦合效應讓電壓PWRBLK升壓的等效電容與電容C和寄生電容Cgs有關。由於電容C與寄生電容Cgs的共同耦合效應可以讓PWRBLK快速地升壓，因此耦合效能將獲得提升。也因如此，升壓保護電路200的電路反應時間的效能會比升壓保護電路100要優。
第3圖係為升壓保護電路300之第三實施例的電路圖。升壓保護電路300的電路架構類似於升壓保護電路100的電路架構。升壓保護電路300內之第一電晶體T101、第二電晶體T102、第三電晶體T103、及第四電晶體T104的佈局方式和電路元件相同於升壓保護電路100，因此電路元件的符號將沿用升壓保護電路100。升壓保護電路300與升壓保護電路100的差異之處在於，升壓保護電路300引入了第五電晶體T105。詳細地說，第五電晶體T105包含耦接於第二電晶體T102之第二端的第一端、耦接於第一電晶體T101之第二端的控制端、以及用以接收接地電壓VSS的第二端。第五電晶體可為N型金屬氧化物半導體場效電晶體。以下將說明升壓保護電路300的操作模式。
在初始狀態，工作電壓VDD在低電壓(可為浮接狀態的的電壓或是近似於接地電壓VSS)。因此，第三電晶體T103會被截止。電壓ZPWRBLK以及電壓PWRBLK的初始狀態也會在低電壓。當寫入電壓VPP非預期地升壓，且工作電壓VDD尚未升壓時(異常狀態)，電壓ZPWRBLK以及電壓PWRBLK會分別透過第一電晶體T101以及第二電晶體T102逐漸升壓。當電壓PWRBLK升壓至第五電晶體T105的門檻電壓時，第五電晶體T105會被導通。並且，當電壓PWRBLK升壓而滿足VPP-PWRBLK＜|Vthp|的條件時，第二電晶體T102將會截止。電壓Vthp的定義為第二電晶體T102的臨界電壓。隨後，電壓ZPWRBLK會透過導通的第五電晶體T105而被下拉至趨近於接地電壓VSS，這將導致第一電晶體T101為完全導通的狀態。舉例而言，當電壓PWRBLK升壓至趨近於寫入電壓VPP(例如7.5伏特)，電壓ZPWRBLK會被下拉至趨近於接地電壓VSS(例如0伏特)。因為電壓PWRBLK可升壓至趨近於寫入電壓VPP，第四電晶體T104會在截止狀態。因此，寫入電壓VPP將可以被截止的第四電晶體T104阻隔，而不會由第四電晶體T104的第一端進入第二端。簡言之，當電壓PWRBLK升壓到夠大(達到第五電晶體T105的臨界電壓)，第五電晶體T105會被導通，因此升壓保護電路300可視為使用了主動式的方法，透過第五電晶體T105將電壓ZPWRBLK強制下拉到趨近於接地電壓VSS。類似前述的功能，當寫入電壓VPP非預期地升壓，且工作電壓VDD尚未升壓時，第一電晶體T101為導通，第二電晶體T102為截止，第四電晶體T104為截止，及第五電晶體T105為導通，以避免第四電晶體T104之第二端輸出寫入電壓VPP至內部電路10。
當工作電壓VDD已經升壓且寫入電壓VPP尚未升壓或已經升壓時，第三電晶體T103會是導通狀態。隨後，電壓PWRBLK會下拉至趨近於接地電壓VSS，這將導致第二電晶體T102被導通且第五電晶體T105被截止。如同前述提及，在第一種狀況，也就是當工作電壓VDD已經升壓且寫入電壓VPP尚未升壓時，由於電壓PWRBLK會下拉至趨近於接地電壓VSS，因此第四電晶體T104會被導通。在第四電晶體T104被導通後，寫入電壓VPP將可透過第四電晶體T104傳輸至內部電路10。在第二種狀況，也就是當工作電壓VDD已經升壓且寫入電壓VPP也已經升壓時，電壓ZPWBLK會透過導通的第二電晶體T102被升壓至趨近於寫入電壓VPP。因此第一電晶體T101會被完全截止。這將導致電壓PWRBLK會維持與接地電壓VSS相近的電位。由於電壓PWRBLK會維持與接地電壓VSS相近的電位，因此第四電晶體T104會被導通。因此，第四電晶體T104之第二端的電壓VPPIN會約略等於寫入電壓VPP(例如7.5伏特)。換句話說，當工作電壓VDD已經升壓，無論寫入電壓VPP是否已經升壓，升壓保護電路300可視為一個旁路電路。亦即，寫入電壓VPP可直接透過第四電晶體T104輸出至內部電路10。
第4圖係為升壓保護電路400之第四實施例的電路圖。升壓保護電路400包含第一電晶體T401、電容C、第二電晶體T402、第三電晶體T403、第四電晶體T404、第五電晶體T405、以及第六電晶體T406。第一電晶體T401包含用以接收寫入電壓VPP的第一端、控制端、及第二端。電容C包含耦接於第一電晶體T401之第一端的第一端、及耦接於第一電晶體T401之第二端的第二端。第二電晶體T402包含耦接於第一電晶體T401之第一端的第一端、耦接於第一電晶體T401之第二端的控制端、及耦接於第一電晶體T401之控制端的第二端。第三電晶體T403包含耦接於第一電晶體T401之第二端的第一端、用以接收工作電壓VDD的控制端、及用以接收接地電壓VSS的第二端。第四電晶體T404包含耦接於第一電晶體T401之第一端的第一端、耦接於第二電晶體T402之第二端的控制端、及第二端。第五電晶體T405包含耦接於第四電晶體T404之第二端的第一端、用於接收工作電壓VDD的控制端、及用以接收接地電壓VSS的第二端。第六電晶體T406包含耦接於第一電晶體T401之第一端的第一端、耦接於第五電晶體T405之第一端的控制端、及用以在第六電晶體T406導通時輸出寫入電壓VPP的第二端。在升壓保護電路400中，第二電晶體T402的控制端電壓的代號為PWRBLK1，下文稱為：電壓PWRBLK1。第二電晶體T402的第二端電壓的代號為ZPWRBLK1，下文稱為：電壓ZPWRBLK1。為了避免混淆，第六電晶體T406之第二端所輸出的電壓之代號為VPPIN1，下文稱為：電壓VPPIN1。換句話說，當第六電晶體T406導通時，電壓VPPIN1會相等於寫入電壓VPP。當第六電晶體T406截止時，電壓VPPIN1可為低電壓或是為浮接狀態的電壓。並且，第六電晶體T406的第二端耦接於內部電路10。因此，內部電路10可接收第六電晶體T406之第二端的電壓VPPIN1。再者，於升壓保護電路400中，第一電晶體T401、第二電晶體T402、第四電晶體T404、及第六電晶體T406可為P型金屬氧化物半導體場效電晶體。第三電晶體T403及第五電晶體T405可為N型金屬氧化物半導體場效電晶體。類似地，當寫入電壓VPP非預期地升壓且工作電壓VDD尚未升壓時，升壓保護電路400可執行電路保護功能。當工作電壓VDD升壓時，升壓保護電路400可視為旁路電路而可忽略。以下將說明升壓保護電路400的操作模式。
在初始狀態，工作電壓VDD在低電壓(可為浮接狀態的電壓或是近似於接地電壓VSS)。因此，第三電晶體T403以及第五電晶體T405會被截止。電壓ZPWRBLK1以及電壓PWRBLK1的初始狀態也會在低電壓。當寫入電壓VPP非預期地升壓，且工作電壓VDD尚未升壓時(異常狀態)，電壓ZPWRBLK1以及電壓PWRBLK1會透過第一電晶體T401以及第二電晶體T402逐漸升壓。此時，由於電容C具可充電特性並且可視為耦合電導元件，因此電壓PWRBLK1的升壓速度會比電壓ZPWRBLK1的升壓速度要快。在升壓保護電路400中，當電壓PWRBLK1升壓而滿足VPP-PWRBLK1＜|Vthp|的條件時，第二電晶體T402將會截止。電壓Vthp的定義為第二電晶體T402的臨界電壓。隨後，電壓ZPWRBLK1會固定在一個比電壓PWRBLK1要小的穩態電壓上，因此第一電晶體T401將保持持續導通的狀態。舉例而言，當電壓PWRBLK1升壓至趨近於寫入電壓VPP(例如7.5伏特)，電壓ZPWRBLK1會固定在一個約為寫入電壓VPP的一半之穩態電壓上(例如3.42~3.75伏特)。因為電壓ZPWRBLK1不夠高，因此第四電晶體T404會被導通。並且，因為工作電壓VDD尚未升壓而在低電壓的狀態，因此第五電晶體T405會被截止。因此，第四電晶體T404之第二端的電壓會趨近於寫入電壓VPP，這將導致第六電晶體T406變為截止狀態。因此，寫入電壓VPP將可以被截止的第六電晶體T406阻隔，而不會由第六電晶體T406的第一端進入第二端。換句話說，第六電晶體T406的第二端將可避免輸出非預期升壓的寫入電壓VPP。因此，對於升壓保護電路400而言，功率消耗以及電路發生干擾等現象的風險將可以降低。簡言之，當寫入電壓VPP非預期地升壓，且工作電壓VDD尚未升壓時，第一電晶體T401為導通，第二電晶體T402為截止，第四電晶體T404為導通，及第六電晶體T406為截止，以避免第六電晶體T406之第二端輸出寫入電壓VPP至內部電路10。
當工作電壓VDD已經升壓且寫入電壓VPP尚未升壓或已經升壓時，第三電晶體T403會是導通狀態。隨後，電壓PWRBLK1會下拉至趨近於接地電壓VSS，這將導致第二電晶體T102被導通。如同前述提及，在第一種狀況，也就是當工作電壓VDD已經升壓且寫入電壓VPP尚未升壓時，由於電壓PWRBLK1會下拉至趨近於接地電壓VSS，因此第二電晶體T402會被導通。但由於寫入電壓VPP尚未升壓，因此電壓ZPWBLK1不會被升壓，這將導致第四電晶體T404會維持在導通狀態。也由於寫入電壓VPP尚未升壓，因此即便第四電晶體T404為導通狀態，第六電晶體T406之控制端所接收到的電壓仍為低電壓。因此，第六電晶體T406會被導通。由於第六電晶體T406會被導通，因此寫入電壓VPP將可透過第六電晶體T406傳至內部電路10。在第二種狀況，也就是當工作電壓VDD已經升壓且寫入電壓VPP也已經升壓時，電壓ZPWBLK1會透過導通的第二電晶體T402被升壓至趨近於寫入電壓VPP。因此第一電晶體T401會被完全截止。這將導致電壓PWRBLK1會維持與接地電壓VSS相近的電位。由於電壓PWRBLK1會維持與接地電壓VSS相近的電位，因此第二電晶體T402會被維持在導通狀態。這將會保持電壓ZPWBLK1維持在趨近於寫入電壓VPP的高電位。並且，由於電壓ZPWBLK1會維持在趨近於寫入電壓VPP的高電位，因此第四電晶體T404將會被截止。第五電晶體T405的第一端之電壓會因為導通的第五電晶體T405而變為接地電壓VSS。隨後，第六電晶體T406會變為導通狀態。因此，第六電晶體T406之第二端的電壓VPPIN1會趨近於寫入電壓VPP(例如7.5伏特)。換句話說，當工作電壓VDD已經升壓，無論寫入電壓VPP是否已經升壓，升壓保護電路400可視為一個旁路電路。亦即，寫入電壓VPP可直接透過第六電晶體T406輸出至內部電路10。
第5圖係為包含第1圖至第4圖其一實施例所述之升壓保護電路的升壓串列系統500的架構圖。在第5圖中，升壓串列系統500具有兩個成對的電壓級、內部電路10、升壓保護電路100a、以及升壓保護電路100b。輸入至內部電路10的工作電壓VDD1可用來控制內部電路10的核心電路。透過升壓保護電路100b輸入至內部電路10的輸入/輸出電壓(I/O Voltage)VDD2可用來控制內部電路10的輸入/輸出裝置。透過升壓保護電路100a輸入至內部電路10的寫入電壓VPP可用來控制內部電路10的資料存取操作。升壓串列系統500具有兩個成對的電壓級之定義為，工作電壓VDD1與輸入/輸出電壓VDD2為一成對的電壓級，而工作電壓VDD1與寫入電壓VPP為另一個成對的電壓級。並且，前述升壓保護電路100至400之一的電路架構可以應用於升壓保護電路100a或升壓保護電路100b的電路架構。舉例而言，第一電晶體T101或T401的第一端可被用來接收輸入/輸出電壓VDD2。第三電晶體T103或T403的控制端可被用來接收工作電壓VDD1。藉由如此應用，升壓保護電路100b將可具備前述實施例之升壓保護電路(100、200、300或400)的功效。亦即，當輸入/輸出電壓VDD2非預期地升壓且工作電壓VDD1尚未升壓時，升壓保護電路100b可避免輸出非預期升壓的輸入/輸出電壓VDD2至內部電路10。換句話說，被內部電路10接收的電壓VDD2IN不會因為輸入/輸出電壓VDD2非預期地升壓而有異常的升壓現象。類似地，第一電晶體T101或T401的第一端可被用來接收寫入電壓VPP。第三電晶體T103或T403的控制端可被用來接收工作電壓VDD1。藉由如此應用，升壓保護電路100a將可具備前述實施例之升壓保護電路(100、200、300或400)的功效。亦即，當寫入電壓VPP非預期地升壓且工作電壓VDD1尚未升壓時，升壓保護電路100a可避免輸出非預期升壓的寫入電壓VPP至內部電路10。換句話說，被內部電路10接收的電壓VPP_IN不會因為寫入電壓VPP非預期地升壓而有異常的升壓現象。然而，升壓串列系統500之任何合理的硬體變更都屬於本發明所揭露的範疇。舉例而言，升壓串列系統500可以引入超過兩個成對的電壓級以及超過兩個對應的升壓保護電路。
綜上所述，本發明揭露了多個升壓保護電路的實施例。升壓保護電路可應用於被多個成對的電壓級所控制之升壓串列系統。當任何的驅動電壓非預期地升壓，且工作電壓尚未升壓時，升壓保護電路可執行電路保護功能。當工作電壓升壓時，升壓保護電路可視為旁路電路而可忽略。並且，升壓保護電路可使用精簡的電路結構即可具有自動化的電路保護功能，不需要額外或是複雜的接腳或端點來控制電路保護的操作。藉由使用升壓保護電路，功率消耗以及電路發生干擾等現象的風險將可以降低。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
100、200、300、400、100a、100b‧‧‧升壓保護電路
500‧‧‧升壓串列系統
T101至T105、T401至T406‧‧‧電晶體
VPP‧‧‧寫入電壓
VDD、VDD1‧‧‧工作電壓
VSS‧‧‧接地電壓
Cgs‧‧‧寄生電容
ZPWRBLK、PWRBLK、VPPIN、ZPWRBLK1、PWRBLK1、VPPIN1、VDD2IN、VPP_IN‧‧‧電壓
10‧‧‧內部電路
C‧‧‧電容
VDD2‧‧‧輸入/輸出電壓
第1圖係為本發明之升壓保護電路之第一實施例的電路圖。 第2圖係為本發明之升壓保護電路之第二實施例的電路圖。 第3圖係為本發明之升壓保護電路之第三實施例的電路圖。 第4圖係為本發明之升壓保護電路之第四實施例的電路圖。 第5圖係為本發明之包含第1圖至第4圖其一所述之升壓保護電路的升壓串列系統的架構圖。

Claims (10)

  1. 一種升壓保護電路，包含：一第一電晶體，包含：一第一端，用以接收一寫入電壓；一控制端；及一第二端；一第二電晶體，包含：一第一端，耦接於該第一電晶體之該第一端；一控制端，耦接於該第一電晶體之該第二端；及一第二端，耦接於該第一電晶體之該控制端；一第三電晶體，包含：一第一端，耦接於該第一電晶體之該第二端；一控制端，用以接收一工作電壓；及一第二端，用以接收一接地電壓；及一第四電晶體，包含：一第一端，耦接於該第二電晶體之該第一端；一控制端，耦接於該第一電晶體之該第二端；及一第二端，用以在該第四電晶體導通時輸出該寫入電壓；其中當該寫入電壓非預期地升壓且該工作電壓尚未升壓時，該第一電晶體為導通，該第二電晶體為截止，及該第四電晶體為截止，以避免該第四電晶體之該第二端輸出該寫入電壓。
  2. 如請求項1所述之升壓保護電路，其中該第一電晶體、該第二電晶體及該第四電晶體係為P型金屬氧化物半導體場效電晶體。
  3. 如請求項1所述之升壓保護電路，其中該第三電晶體係為N型金屬氧化物半導體場效電晶體。
  4. 如請求項1所述之升壓保護電路，其中該第四電晶體之該控制端的一電壓等於該寫入電壓，且該第一電晶體之該控制端的一電壓等於該寫入電壓的一半。
  5. 如請求項1所述之升壓保護電路，其中該第四電晶體之該第一端與該控制端之間產生一寄生電容，以使當該寫入電壓非預期地升壓且該工作電壓尚未升壓時，該第四電晶體之該控制端的該電壓的升壓速度快於該第一電晶體之該控制端的該電壓的升壓速度。
  6. 如請求項1所述之升壓保護電路，另包含：一電容，包含：一第一端，耦接於該第一電晶體之該第一端；及一第二端，耦接於該第一電晶體之該第二端。
  7. 如請求項6所述之升壓保護電路，其中該電容係為一金屬氧化物半導體(Metal-Oxide-Semiconductor)電容。
  8. 如請求項6所述之升壓保護電路，其中當該寫入電壓非預期地升壓且該工作電壓尚未升壓時，該第一電晶體為導通，該第二電晶體為截止，及該第四電晶體為截止，以避免該第四電晶體之該第二端輸出該寫入電壓。
  9. 如請求項8所述之升壓保護電路，其中該第四電晶體之該控制端的一電壓等於該寫入電壓，且該第一電晶體之該控制端的一電壓等於該寫入電壓的一半。
  10. 如請求項9所述之升壓保護電路，其中該第四電晶體之該第一端與該控制端之間產生一寄生電容，以使當該寫入電壓非預期地升壓且該工作電壓尚未升壓時，該第四電晶體之該控制端的該電壓的升壓速度快於該第一電晶體之該控制端的該電壓的升壓速度。
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TW106100742A TWI614766B (zh) 2016-01-19 2017-01-10 非揮發性記憶體
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Families Citing this family (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI606448B (zh) * 2015-07-29 2017-11-21 國立交通大學 介電質熔絲型記憶電路及其操作方法
US10181357B2 (en) * 2015-08-18 2019-01-15 Ememory Technology Inc. Code generating apparatus and one time programming block
US10032521B2 (en) * 2016-01-08 2018-07-24 Synopsys, Inc. PUF value generation using an anti-fuse memory array
US10020268B2 (en) 2016-04-13 2018-07-10 Ememory Technology Inc. Random number generator device and control method thereof
US10090027B2 (en) * 2016-05-25 2018-10-02 Ememory Technology Inc. Memory system with low read power
US10469083B2 (en) 2016-07-10 2019-11-05 Imec Vzw Breakdown-based physical unclonable function
US10122538B2 (en) * 2016-10-12 2018-11-06 Ememory Technology Inc. Antifuse physically unclonable function unit and associated control method
US10395745B2 (en) 2016-10-21 2019-08-27 Synposys, Inc. One-time programmable bitcell with native anti-fuse
US10446562B1 (en) * 2017-01-10 2019-10-15 Synopsys, Inc. One-time programmable bitcell with partially native select device
JP6349008B1 (ja) * 2017-04-13 2018-06-27 力旺電子股▲ふん▼有限公司ｅＭｅｍｏｒｙ Ｔｅｃｈｎｏｌｏｇｙ Ｉｎｃ． 乱数発生装置及びその制御方法
US11615859B2 (en) * 2017-04-14 2023-03-28 Attopsemi Technology Co., Ltd One-time programmable memories with ultra-low power read operation and novel sensing scheme
US10776521B2 (en) 2017-04-21 2020-09-15 Apple Inc. Security techniques based on memory timing characteristics
US10090309B1 (en) * 2017-04-27 2018-10-02 Ememory Technology Inc. Nonvolatile memory cell capable of improving program performance
US10276239B2 (en) * 2017-04-27 2019-04-30 Ememory Technology Inc. Memory cell and associated array structure
EP3407336B1 (en) * 2017-05-22 2022-08-17 Macronix International Co., Ltd. Unchangeable phyisical unclonable function in non-volatile memory
US10276253B2 (en) * 2017-08-04 2019-04-30 Micron Technology, Inc. Apparatuses and methods including anti-fuses and for reading and programming of same
US10623192B2 (en) * 2017-08-25 2020-04-14 Synopsys, Inc. Gate oxide breakdown in OTP memory cells for physical unclonable function (PUF) security
US10649735B2 (en) * 2017-09-12 2020-05-12 Ememory Technology Inc. Security system with entropy bits
US10915464B2 (en) 2017-09-12 2021-02-09 Ememory Technology Inc. Security system using random number bit string
CN109658963B (zh) * 2017-10-11 2020-11-17 华邦电子股份有限公司 电阻式存储器存储装置的操作方法
TWI652683B (zh) 2017-10-13 2019-03-01 力旺電子股份有限公司 用於記憶體的電壓驅動器
CN107945824A (zh) * 2017-11-21 2018-04-20 上海华虹宏力半导体制造有限公司 用于sonos存储器的复位电路及复位方法
US11063772B2 (en) 2017-11-24 2021-07-13 Ememory Technology Inc. Multi-cell per bit nonvolatile memory unit
US11050575B2 (en) 2018-01-10 2021-06-29 Ememory Technology Inc. Entanglement and recall system using physically unclonable function technology
US10505521B2 (en) * 2018-01-10 2019-12-10 Ememory Technology Inc. High voltage driver capable of preventing high voltage stress on transistors
TWI696111B (zh) * 2018-01-10 2020-06-11 力旺電子股份有限公司 隨機碼產生器
CN110018810B (zh) 2018-01-10 2021-05-18 力旺电子股份有限公司 随机码产生器
US11055065B2 (en) * 2018-04-18 2021-07-06 Ememory Technology Inc. PUF-based true random number generation system
US10714199B1 (en) * 2018-05-09 2020-07-14 Synopsys, Inc. PUF latch for OTP memory arrays and method of operation
CN110489351B (zh) * 2018-05-14 2021-03-09 英韧科技(上海)有限公司 芯片指纹管理装置及安全芯片
TWI669714B (zh) 2018-05-29 2019-08-21 力旺電子股份有限公司 電壓控制裝置及記憶體系統
US10923483B2 (en) * 2018-05-31 2021-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. EFuse
US10839872B2 (en) * 2018-07-03 2020-11-17 Ememory Technology Inc. Random bit cell using an initial state of a latch to generate a random bit
CN109087679A (zh) * 2018-07-27 2018-12-25 上海华力集成电路制造有限公司 存储单元及其构成的存储阵列和otp
US11170115B2 (en) * 2018-07-30 2021-11-09 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for secure external access of the PUF information to an authorized entity
CN109062830B (zh) * 2018-08-02 2021-10-22 中国科学院微电子研究所 一种非易失性存储器的控制系统
US10685727B2 (en) * 2018-08-10 2020-06-16 Ememory Technology Inc. Level shifter
EP3680800B1 (en) * 2018-08-10 2021-10-27 Shenzhen Weitongbo Technology Co., Ltd. Physical unclonable function (puf) device
US11176969B2 (en) 2018-08-20 2021-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuit including a first program device
US11380693B2 (en) * 2018-08-20 2022-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including anti-fuse cell structure
US10797064B2 (en) * 2018-09-19 2020-10-06 Ememory Technology Inc. Single-poly non-volatile memory cell and operating method thereof
US11416416B2 (en) * 2019-01-13 2022-08-16 Ememory Technology Inc. Random code generator with non-volatile memory
US10748591B2 (en) * 2019-01-13 2020-08-18 Ememory Technology Inc. Random code generator
US11514174B2 (en) 2019-01-23 2022-11-29 Micron Technology, Inc. Memory devices with cryptographic components
US11294640B2 (en) 2019-03-13 2022-04-05 Ememory Technology Inc. Random number generator
US10924112B2 (en) 2019-04-11 2021-02-16 Ememory Technology Inc. Bandgap reference circuit
CN110164499B (zh) * 2019-05-24 2023-02-28 中国科学院微电子研究所 一种非易失性存储器的控制系统
US11152380B2 (en) * 2019-08-06 2021-10-19 Globalfoundries Singapore Pte. Ltd. Memory device and a method for forming the memory device
CN115085759A (zh) 2019-10-17 2022-09-20 立积电子股份有限公司 射频装置
US11663455B2 (en) * 2020-02-12 2023-05-30 Ememory Technology Inc. Resistive random-access memory cell and associated cell array structure
US11189356B2 (en) * 2020-02-27 2021-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. One-time-programmable memory
US11468945B2 (en) * 2020-10-15 2022-10-11 Arm Limited 3D storage architecture with tier-specific controls
US20220199622A1 (en) * 2020-12-18 2022-06-23 Ememory Technology Inc. Resistive memory cell and associated cell array structure
US11329836B1 (en) * 2021-03-12 2022-05-10 Globalfoundries U.S. Inc. Twin cell memory-based physically unclonable function
US11594541B2 (en) * 2021-03-26 2023-02-28 Nanya Technology Corporation One-time programmable memory array and manufacturing method thereof
CN113129985B (zh) * 2021-03-29 2024-05-03 深圳市国微电子有限公司 一种物理不可克隆单元及读取电路
CN115241181A (zh) 2021-04-23 2022-10-25 联华电子股份有限公司 单次可编程存储器元件
US20230047939A1 (en) 2021-08-13 2023-02-16 Ememory Technology Inc. Fuse-type one time programming memory cell
FR3133699A1 (fr) * 2022-03-21 2023-09-22 Stmicroelectronics (Rousset) Sas Mémoire morte programmable
US20240071538A1 (en) * 2022-08-24 2024-02-29 Jmem Technology Co., Ltd. Multi-state one-time programmable memory circuit
TWI828568B (zh) * 2023-03-27 2024-01-01 華邦電子股份有限公司 物理不可複製函數代碼產生裝置及物理不可複製函數代碼的產生方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030098712A1 (en) * 2001-11-28 2003-05-29 Fujitsu Limited Level conversion circuit for which an operation at power voltage rise time is stabilized
US20090027972A1 (en) * 2006-03-16 2009-01-29 Freescale Semiconductor, Inc. Wordline driver for a non-volatile memory device, a non-volatile memory device and method
TWI344152B (en) * 2006-09-21 2011-06-21 Mediatek Inc Memory circuits and malfunction protection methods thereof
US8063662B2 (en) * 2007-07-06 2011-11-22 Analog Devices, Inc. Methods and apparatus for predictable level shifter power-up state
US20150214938A1 (en) * 2014-01-27 2015-07-30 Fuji Electric Co., Ltd. Delay circuit

Family Cites Families (94)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0666115B2 (ja) * 1983-09-26 1994-08-24 株式会社東芝 半導体記憶装置
JPS62180607A (ja) 1986-02-04 1987-08-07 Fujitsu Ltd 半導体集積回路
US4787066A (en) * 1987-08-03 1988-11-22 Sgs-Thomson Microelectronics, Inc. Non-volatile shadow storage cell with improved level shifting circuit and reduced tunnel device count for improved reliability
US4825410A (en) 1987-10-26 1989-04-25 International Business Machines Corporation Sense amplifier control circuit
GB8923037D0 (en) 1989-10-12 1989-11-29 Inmos Ltd Timing control for a memory
US5243226A (en) * 1991-07-31 1993-09-07 Quicklogic Corporation Programming of antifuses
US5316971A (en) 1992-09-18 1994-05-31 Actel Corporation Methods for programming antifuses having at least one metal electrode
JPH0845269A (ja) * 1994-07-27 1996-02-16 Hitachi Ltd 半導体記憶装置
US5528173A (en) * 1995-05-10 1996-06-18 Micron Technology, Inc. Low power, high speed level shifter
US6023431A (en) * 1996-10-03 2000-02-08 Micron Technology, Inc. Low current redundancy anti-fuse method and apparatus
JP2001351398A (ja) * 2000-06-12 2001-12-21 Nec Corp 記憶装置
EP1186924A3 (en) * 2000-09-05 2003-08-13 Matsushita Electric Industrial Co., Ltd. Optical signal reading apparatus using light leaked out of light transmission path
US6584526B1 (en) * 2000-09-21 2003-06-24 Intel Corporation Inserting bus inversion scheme in bus path without increased access latency
KR100375219B1 (ko) 2000-11-09 2003-03-07 삼성전자주식회사 반도체 메모리 장치의 데이터 라인 프리챠지 회로
US7187228B1 (en) 2001-06-22 2007-03-06 Quicklogic Corporation Method of programming an antifuse
FR2836751A1 (fr) * 2002-02-11 2003-09-05 St Microelectronics Sa Cellule memoire a programmation unique non destructrice
JP2003257180A (ja) * 2002-03-04 2003-09-12 Nec Electronics Corp ＤＲＡＭ（ＤｙｎａｍｉｃＲａｎｄｏｍＡｃｃｅｓｓＭｅｍｏｒｙ）及びその動作方法
JP2004310904A (ja) * 2003-04-07 2004-11-04 Renesas Technology Corp 不揮発性半導体記憶装置
JP2005276348A (ja) * 2004-03-25 2005-10-06 Fujitsu Ltd 半導体記憶装置、及びプリチャージ制御方法
TWI267863B (en) * 2004-04-12 2006-12-01 Samsung Electronics Co Ltd High voltage generating circuit preserving charge pumping efficiency
US20050289435A1 (en) * 2004-06-29 2005-12-29 Mulla Dean A Fast approximate DINV calculation in parallel with coupled ECC generation or correction
US7205820B1 (en) * 2004-07-08 2007-04-17 Pmc-Sierra, Inc. Systems and methods for translation of signal levels across voltage domains
JP4383987B2 (ja) * 2004-08-18 2009-12-16 株式会社東芝 Ｍｏｓ型電気ヒューズとそのプログラム方法
JP4709525B2 (ja) * 2004-10-14 2011-06-22 株式会社東芝 不揮発性半導体記憶装置
US7190626B2 (en) * 2005-05-13 2007-03-13 Taiwan Semiconductor Manufacturing Co., Ltd. Memory system with bit-line discharging mechanism
US7253496B2 (en) * 2005-06-28 2007-08-07 Cypress Semiconductor Corporation Antifuse circuit with current regulator for controlling programming current
US7280425B2 (en) * 2005-09-30 2007-10-09 Intel Corporation Dual gate oxide one time programmable (OTP) antifuse cell
US7359265B2 (en) 2006-01-04 2008-04-15 Etron Technology, Inc. Data flow scheme for low power DRAM
JP4894854B2 (ja) * 2006-02-27 2012-03-14 富士通株式会社 データ送信装置、データ送受信システム及びデータ送受信システムの制御方法
KR100694972B1 (ko) * 2006-03-27 2007-03-14 주식회사 하이닉스반도체 센싱 노드용 프리차지 전압을 선택적으로 변경하는 기능을가지는 플래시 메모리 장치 및 그 독출 동작 방법
US7508694B2 (en) * 2006-09-27 2009-03-24 Novelics, Llc One-time-programmable memory
KR100825788B1 (ko) * 2006-10-31 2008-04-28 삼성전자주식회사 메모리 셀 센싱 이전에 비트라인의 프리차아지 전압 레벨을유지할 수 있는 플래쉬 메모리 장치의 센스 앰프 회로 및플래쉬 메모리 셀 센싱 방법
US20080316660A1 (en) 2007-06-20 2008-12-25 Ememory Technology Inc. Electrostatic discharge avoiding circuit
US7551497B2 (en) * 2007-09-20 2009-06-23 Mediatek Inc. Memory circuits preventing false programming
US7804327B2 (en) * 2007-10-12 2010-09-28 Mediatek Inc. Level shifters
JP5112846B2 (ja) * 2007-12-27 2013-01-09 セイコーインスツル株式会社 電源切替回路
US8255758B2 (en) * 2008-01-21 2012-08-28 Apple Inc. Decoding of error correction code using partial bit inversion
US8031506B2 (en) 2008-03-21 2011-10-04 Broadcom Corporation One-time programmable memory cell
TWI430275B (zh) 2008-04-16 2014-03-11 Magnachip Semiconductor Ltd 用於程式化非揮發性記憶體裝置之方法
US8127204B2 (en) * 2008-08-15 2012-02-28 Micron Technology, Inc. Memory system and method using a memory device die stacked with a logic die using data encoding, and system using the memory system
US7782116B2 (en) * 2008-09-05 2010-08-24 Fairchild Semiconductor Corporation Power supply insensitive voltage level translator
US8910009B1 (en) * 2008-09-08 2014-12-09 Marvell International Ltd. Method and apparatus for enhancing error detection in data transmission
US8395923B2 (en) * 2008-12-30 2013-03-12 Intel Corporation Antifuse programmable memory array
US8125842B2 (en) 2009-03-31 2012-02-28 Agere Systems Inc. Tracking circuit for reducing faults in a memory
CN101923896A (zh) * 2009-06-12 2010-12-22 威刚科技（苏州）有限公司 电子存储装置及其纠错方法
US9013910B2 (en) * 2009-07-30 2015-04-21 Ememory Technology Inc. Antifuse OTP memory cell with performance improvement prevention and operating method of memory
JP4937316B2 (ja) * 2009-08-21 2012-05-23 株式会社東芝 不揮発性半導体記憶装置
US20110246857A1 (en) 2010-04-02 2011-10-06 Samsung Electronics Co., Ltd. Memory system and method
US8279693B2 (en) * 2010-04-09 2012-10-02 Qualcomm Incorporated Programmable tracking circuit for tracking semiconductor memory read current
JP5343916B2 (ja) * 2010-04-16 2013-11-13 富士通セミコンダクター株式会社 半導体メモリ
US8217705B2 (en) * 2010-05-06 2012-07-10 Micron Technology, Inc. Voltage switching in a memory device
KR101115623B1 (ko) * 2010-07-09 2012-02-15 주식회사 하이닉스반도체 불휘발성 메모리 장치 및 이의 동작 방법
JP5466594B2 (ja) * 2010-07-29 2014-04-09 ルネサスエレクトロニクス株式会社 半導体記憶装置及びアンチヒューズのプログラム方法
US9224496B2 (en) 2010-08-11 2015-12-29 Shine C. Chung Circuit and system of aggregated area anti-fuse in CMOS processes
CN102375698B (zh) * 2010-08-23 2014-06-25 群联电子股份有限公司 数据串分派与传送方法、存储器控制器与存储器储存装置
US8339831B2 (en) * 2010-10-07 2012-12-25 Ememory Technology Inc. Single polysilicon non-volatile memory
US8300450B2 (en) 2010-11-03 2012-10-30 International Business Machines Corporation Implementing physically unclonable function (PUF) utilizing EDRAM memory cell capacitance variation
JP2012109329A (ja) * 2010-11-16 2012-06-07 Elpida Memory Inc 半導体装置及びその制御方法
KR101953088B1 (ko) * 2011-01-31 2019-03-04 에버스핀 테크놀러지스, 인크. 스핀 토크 자기 랜덤 액세스 메모리에 대한 기록 방법
WO2012106358A1 (en) * 2011-01-31 2012-08-09 Everspin Technologies, Inc. Method of reading and writing to a spin torque magnetic random access memory with error correcting code
JP5204868B2 (ja) * 2011-04-12 2013-06-05 シャープ株式会社 半導体記憶装置
JP5269151B2 (ja) * 2011-06-09 2013-08-21 シャープ株式会社 半導体記憶装置
US8724363B2 (en) 2011-07-04 2014-05-13 Ememory Technology Inc. Anti-fuse memory ultilizing a coupling channel and operating method thereof
KR20130011058A (ko) * 2011-07-20 2013-01-30 에스케이하이닉스 주식회사 반도체 장치 및 이의 동작방법
KR101115756B1 (ko) * 2011-09-23 2012-03-06 권의필 고집적 프로그램이 가능한 비휘발성 메모리 및 그 제조 방법
US8508971B2 (en) * 2011-11-08 2013-08-13 Wafertech, Llc Semiconductor device with one-time programmable memory cell including anti-fuse with metal/polycide gate
KR20130092174A (ko) * 2012-02-10 2013-08-20 에스케이하이닉스 주식회사 불휘발성 반도체 메모리 장치 및 이 장치의 데이터 센싱 방법
US8698922B2 (en) * 2012-02-14 2014-04-15 Omni Vision Technologies, Inc. Black level correction for imaging pixels
JP5395203B2 (ja) * 2012-03-23 2014-01-22 力晶科技股▲ふん▼有限公司 レベルシフト回路及びそれを用いた半導体デバイス
FR2990291A1 (fr) * 2012-05-03 2013-11-08 St Microelectronics Sa Procede de controle du claquage d'un antifusible
US8681528B2 (en) * 2012-08-21 2014-03-25 Ememory Technology Inc. One-bit memory cell for nonvolatile memory and associated controlling method
US9142275B2 (en) * 2012-10-31 2015-09-22 Taiwan Semiconductor Manufacturing Co., Ltd. Wordline tracking for boosted-wordline timing scheme
US8830766B2 (en) 2013-01-23 2014-09-09 Lsi Corporation Margin free PVT tolerant fast self-timed sense amplifier reset circuit
US20140293673A1 (en) 2013-03-28 2014-10-02 Ememory Technology Inc. Nonvolatile memory cell structure and method for programming and reading the same
US9281074B2 (en) 2013-05-16 2016-03-08 Ememory Technology Inc. One time programmable memory cell capable of reducing leakage current and preventing slow bit response
US20150007337A1 (en) * 2013-07-01 2015-01-01 Christian Krutzik Solid State Drive Physical Uncloneable Function Erase Verification Device and Method
JP6106043B2 (ja) * 2013-07-25 2017-03-29 ルネサスエレクトロニクス株式会社 半導体集積回路装置
KR20150019442A (ko) * 2013-08-14 2015-02-25 삼성전자주식회사 퓨즈 셀들의 프로그래밍 방법 및 메모리 복구 방법
KR101489758B1 (ko) 2013-08-26 2015-02-04 한국전자통신연구원 플래시 메모리의 동작 제어 방법 및 장치
CN104464816B (zh) * 2013-09-21 2019-03-01 上峰科技股份有限公司 单次可编程记忆体及其操作方法和编程方法以及电子系统
EP3349343B1 (en) * 2013-11-08 2019-07-17 Delta Electronics (Thailand) Public Co., Ltd. Resistorless precharging
US9628086B2 (en) * 2013-11-14 2017-04-18 Case Western Reserve University Nanoelectromechanical antifuse and related systems
US20150143130A1 (en) * 2013-11-18 2015-05-21 Vixs Systems Inc. Integrated circuit provisioning using physical unclonable function
CN103730164B (zh) * 2013-12-27 2017-01-04 深圳市国微电子有限公司 一种可编程存储单元
US9501352B2 (en) * 2014-03-05 2016-11-22 Kabushiki Kaisha Toshiba Memory device
US9823860B2 (en) * 2014-03-14 2017-11-21 Nxp B.V. One-time programming in reprogrammable memory
US9349472B2 (en) * 2014-03-25 2016-05-24 Integrated Silicon Solution, Inc. Flash memory device with sense-amplifier-bypassed trim data read
US9768957B2 (en) 2014-04-23 2017-09-19 Cryptography Research, Inc. Generation and management of multiple base keys based on a device generated key
JP6200370B2 (ja) * 2014-04-23 2017-09-20 ルネサスエレクトロニクス株式会社 データバス駆動回路、それを備えた半導体装置及び半導体記憶装置
US9778903B2 (en) * 2014-05-12 2017-10-03 Micron Technology, Inc. Apparatuses and methods for timing domain crossing
US9431111B2 (en) * 2014-07-08 2016-08-30 Ememory Technology Inc. One time programming memory cell, array structure and operating method thereof
KR102169197B1 (ko) * 2014-09-16 2020-10-22 에스케이하이닉스 주식회사 향상된 프로그램 효율을 갖는 안티퓨즈 오티피 메모리 셀 및 셀 어레이
KR20160071054A (ko) * 2014-12-11 2016-06-21 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그의 동작 방법
US9627088B2 (en) * 2015-02-25 2017-04-18 Ememory Technology Inc. One time programmable non-volatile memory and read sensing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030098712A1 (en) * 2001-11-28 2003-05-29 Fujitsu Limited Level conversion circuit for which an operation at power voltage rise time is stabilized
US20090027972A1 (en) * 2006-03-16 2009-01-29 Freescale Semiconductor, Inc. Wordline driver for a non-volatile memory device, a non-volatile memory device and method
TWI344152B (en) * 2006-09-21 2011-06-21 Mediatek Inc Memory circuits and malfunction protection methods thereof
US8063662B2 (en) * 2007-07-06 2011-11-22 Analog Devices, Inc. Methods and apparatus for predictable level shifter power-up state
US20150214938A1 (en) * 2014-01-27 2015-07-30 Fuji Electric Co., Ltd. Delay circuit

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