TWI627833B - 具有高可靠度的電源切換裝置 - Google Patents
具有高可靠度的電源切換裝置 Download PDFInfo
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- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
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Abstract
電源切換裝置包含第一位準移位電路、第一電晶體、第二電晶體、第二位準移位電路、第三電晶體、第四電晶體、第五電晶體及第六電晶體。第一電晶體耦接於第一位準移位電路。第二電晶體耦接於第二位準移位電路。第一電晶體耦接於第二電晶體,用以輸出一個輸出電壓。第五電晶體及第六電晶體組成電壓選擇器。第三電晶體及第四電晶體耦接於第二電晶體,用以控制電壓選擇器輸出至第一位準移位電路及第二位準移位電路的驅動電壓。電源切換裝置中,輸入至第一位準移位電路及第二位準移位電路的驅動電壓在寫入模式或是在讀取模式下都能保持穩定。
Description
本發明揭露一種電源切換裝置,尤指一種在寫入模式及讀取模式下,位準移位電路的驅動電壓都能保持穩定的電源切換裝置。
非揮發性記憶體(Non-Volatile Memory,NVM)是一種在沒有電力供應至記憶體區塊的情況下,仍然能夠維持原本儲存之資料的記憶體。非揮發性記憶體可應用於許多設備,例如磁性裝置、光碟片、快閃記憶體或是其它半導體製程的記憶裝置。非揮發性記憶體可分為電子式尋址系統(Electrically Addressed Systems)的記憶體,例如唯讀記憶體(Read-Only Memory),以及機械式尋址系統(Mechanically Addressed Systems)的記憶體,例如硬碟、光碟、磁帶等裝置。並且,非揮發性記憶體不需要將本身儲存之資料做週期性地更新。因此,非揮發性記憶體常被用來當成備份資料的裝置或是能長時間儲存資料的裝置。
一般而言,非揮發性記憶體可被執行寫入操作以及讀取操作的功能。為了驅動記憶體的寫入操作以及讀取操作,電路會使用電源切換裝置產生適當的電壓至記憶體之內部晶片中。在正常操作下,使用者(或以自動化的方式)可操作外部的控制訊號以控制電源切換裝置,進而產生對應寫入操作或讀取操作的電壓。一般電源切換裝置會利用電壓選擇器(Voltage Selector),並結合位準移位電路(Level Shift Circuit)以控制對應的電晶體輸出正確的電壓。然而,在某些低壓驅動的情況下,電壓選擇器會無法輸出正確的驅動電壓至位準移位電路以控制電晶體,這將導致電源切換裝置失能或是輸出錯誤的電壓。
本發明一實施例提出一種電源切換裝置,包含第一位準移位電路、第一電晶體、第二電晶體、第二位準移位電路、第三電晶體、第四電晶體、第五電晶體及第六電晶體。第一位準移位電路用以根據驅動電壓調整第一控制電壓的位準,以產生第一閘極電壓。第一電晶體包含用以接收工作電壓的第一端、耦接於第一位準移位電路並用以接收第一閘極電壓的控制端、以及用以輸出一個輸出電壓的第二端。第二電晶體包含第一端、控制端、以及耦接於第一電晶體之第二端的第二端。第二位準移位電路耦接於第二電晶體之控制端,用以根據驅動電壓調整第二控制電壓的位準,以產生第二閘極電壓至第二電晶體之控制端。第三電晶體包含用以接收寫入電壓的第一端、用以接收第三閘極電壓的控制端、以及耦接於第二電晶體之第一端的第二端。第四電晶體包含耦接於第三電晶體之第二端的第一端、用以接收第二控制電壓的控制端、以及耦接於接地端的第二端。第五電晶體包含用以接收工作電壓的第一端、耦接於第四電晶體之第一端的控制端、以及用以輸出驅動電壓的第二端。第六電晶體包含耦接於第四電晶體之第一端的第一端、用以接收工作電壓的控制端、以及耦接於第五電晶體之第二端的第二端。
第1圖為電源切換裝置100的架構圖。電源切換裝置100包含第一位準移位電路LS1、第一電晶體T1、第二電晶體T2、第二位準移位電路LS2、第三電晶體T3、第四電晶體T4、第五電晶體T5及第六電晶體T6。第一位準移位電路LS1用以根據驅動電壓VV調整第一控制電壓IN1的位準,以產生第一閘極電壓GV1。第一電晶體T1包含用以接收工作電壓VDD的第一端、耦接於第一位準移位電路LS1並用以接收第一閘極電壓GV1的控制端、以及用以輸出一個輸出電壓VPPIN的第二端。當電源切換裝置100應用在控制及驅動記憶體電路時,輸出電壓VPPIN可輸出至記憶體之內部晶片,藉以提供適當電壓以便操作。第二電晶體T2包含第一端、控制端、以及耦接於第一電晶體T1之第二端的第二端。第二位準移位電路LS2耦接於第二電晶體T2之控制端,用以根據驅動電壓VV調整第二控制電壓IN2的位準,以產生第二閘極電壓GV2至第二電晶體T2之控制端。第三電晶體T3包含用以接收寫入電壓VPP的第一端、用以接收第三閘極電壓GV3的控制端、以及耦接於第二電晶體T2之第一端的第二端。第四電晶體T4包含耦接於第三電晶體T3之第二端的第一端、用以接收第二控制電壓IN2的控制端、以及耦接於接地端的第二端。第五電晶體包含用以接收工作電壓VDD的第一端、耦接於第四電晶體T4之第一端的控制端、以及用以輸出驅動電壓VV的第二端。第六電晶體T6包含耦接於第四電晶體T4之第一端的第一端、耦接於第五電晶體T5之第一端的控制端、以及耦接於第五電晶體T5之第二端的第二端。在電源切換裝置100中,第一電晶體T1、第二電晶體T2、第三電晶體T3、第五電晶體T5及第六電晶體T6可為P型金屬氧化物半導體場效電晶體。第四電晶體T4可為N型金屬氧化物半導體場效電晶體。並且,第一位準移位電路LS1以及第二位準移位電路LS2可為任何形式的位準移位電路,具有控制電壓與輸出的閘極電壓為同向的特性。並且,第五電晶體T5及第六電晶體T6可組成電壓選擇器,用以輸出驅動電壓VV。以下將說明電源切換裝置100在不同模式下的運作情況。
當電源切換裝置100在寫入模式(Program Mode)時,寫入電壓VPP會大於工作電壓VDD。並且,第一控制電壓IN1大於第二控制電壓IN2。例如,寫入電壓VPP可為高電位的電壓,工作電壓VDD可為低電位的電壓,第一控制電壓IN1可為高電位的電壓,第二控制電壓IN2可為低電位的電壓。並且,第三閘極電壓GV3可等於第二控制電壓IN2,亦為低電位。由於第三電晶體T3的控制端接收了低電位的第三閘極電壓GV3,因此第三電晶體T3為導通。由於第四電晶體T4的控制端接收了低電位的第二控制電壓IN2,因此第四電晶體T4為截止,等同於端點電壓VPP_SW之壓降路徑被關閉。第四電晶體T4之第一端的端點電壓VPP_SW會等於高電位的寫入電壓VPP。由於第五電晶體T5的控制端接收了高電位的端點電壓VPP_SW,因此第五電晶體T5為截止。由於第六電晶體T6的控制端接收了低電位的工作電壓VDD,因此第六電晶體T6為導通。由於第六電晶體T6為導通,因此第六電晶體T6的第二端將輸出與寫入電壓VPP相同電位的驅動電壓VV。因此,驅動電壓VV將可以致能第一位準移位電路LS1以及第二位準移位電路LS2的運作。例如,第一位準移位電路LS1可以根據驅動電壓VV,調整高電位的控制電壓IN1以輸出同向的第一閘極電壓GV1而使第一電晶體T1截止。類似地,第二位準移位電路LS2可以根據驅動電壓VV,調整低電位的控制電壓IN2以輸出同向的第二閘極電壓GV2而使第二電晶體T2導通。因此,在電源切換裝置100中,高電位的寫入電壓VPP會經由導通的第三電晶體T3以及第二電晶體T2傳至第二電晶體T2之第二端。換句話說,在寫入模式時,電源切換裝置100最終會輸出與高電位的寫入電壓VPP同電位的輸出電壓VPPIN。
當電源切換裝置100在讀取模式(Read Mode)時,寫入電壓VPP會小於或等於工作電壓VDD。並且,第一控制電壓IN1小於第二控制電壓IN2。例如,寫入電壓VPP可為與工作電壓VDD相近電位的電壓、寫入電壓VPP也可為接地電壓、寫入電壓VPP也可為小於工作電壓VDD之浮接狀態(Floating State)電壓。第一控制電壓IN1可為低電位的電壓,第二控制電壓IN2可為高電位的電壓。並且,第三閘極電壓GV3可等於第二控制電壓IN2,亦為高電位。由於第三電晶體T3的控制端接收了高電位的第三閘極電壓GV3,因此第三電晶體T3為截止。由於第四電晶體T4的控制端接收了高電位的第二控制電壓IN2,因此第四電晶體T4為導通,等同於端點電壓VPP_SW之壓降路徑被開啟。第四電晶體T4之第一端的端點電壓VPP_SW會等於接地電壓。由於第五電晶體T5的控制端接收了電位為接地電壓的端點電壓VPP_SW,因此第五電晶體T5為導通。由於第六電晶體T6的控制端接收了較高電位的工作電壓VDD,因此第六電晶體T6為截止。因此第五電晶體T5的第二端將輸出與工作電壓VDD相同電位的驅動電壓VV。因此,驅動電壓VV將可以致能第一位準移位電路LS1以及第二位準移位電路LS2的運作。例如,第一位準移位電路LS1可以根據驅動電壓VV,調整低電位的控制電壓IN1以輸出同向的第一閘極電壓GV1而使第一電晶體T1導通。類似地,第二位準移位電路LS2可以根據驅動電壓VV,調整高電位的控制電壓IN2以輸出同向的第二閘極電壓GV2而使第二電晶體T2截止。因此,在電源切換裝置100中,工作電壓VDD會經由第一電晶體T1傳至第一電晶體T1之第二端。換句話說,在讀取模式時,電源切換裝置100最終會輸出與工作電壓VDD同電位的輸出電壓VPPIN。並且,應當理解的是,由於第三電晶體T3為截止狀態,因此寫入電壓VPP為與工作電壓VDD相近電位的電壓、寫入電壓VPP為接地電壓、或寫入電壓為小於工作電壓VDD的浮接狀態電壓之各種不同的電壓狀態下,都不會影響電源切換裝置100最終的輸出結果。
因此,當電源切換裝置100在寫入模式時,最終會輸出與寫入電壓VPP同電位的輸出電壓VPPIN。當電源切換裝置100在讀取模式時,最終會輸出與工作電壓VDD同電位的輸出電壓VPPIN。所以,電源切換裝置可產生適當的輸出電壓VPPIN至記憶體之內部晶片中。本實施例在實際運作時,當電源切換裝置100在寫入模式時,寫入電壓VPP可為9伏特,工作電壓VDD可為1.5伏特,第一控制電壓IN1可為1.5伏特,第二控制電壓IN2可為0伏特,端點電壓VPP_SW會變成9伏特,驅動電壓VV可為9伏特,而最終輸出的輸出電壓VPPIN可為9伏特。當電源切換裝置100在讀取模式時,寫入電壓VPP可為1.5伏特、0伏特或是小於工作電壓VDD的浮接狀態,工作電壓VDD可為1.5伏特,第一控制電壓IN1可為0伏特,第二控制電壓IN2可為1.5伏特,端點電壓VPP_SW會變成0伏特,驅動電壓VV可為1.5伏特,而最終輸出的輸出電壓VPPIN可為1.5伏特。為了描述更為清楚,表A將列出上述模式的各種電壓狀態,如下(為了方便表達,表A中之伏特的代號以”V”來表示):
表A
第2圖為電源切換裝置200的架構圖。在本發明中,任何硬體的合理變更皆屬於本發明所揭露的範疇。因此,在上述電源切換裝置100中,也可以加入額外的第三位準移位電路LS3,以達到相同的電源切換功效。換句話說,電源切換裝置200的電路架構類似於電源切換裝置100的電路架構。差別之處在於電源切換裝置200加入了第三位準移位電路LS3。第三位準移位電路LS3耦接於第三電晶體T3之控制端,用以根據寫入電壓VPP調整第二控制電壓IN2的位準,以產生第三閘極電壓GV3至第三電晶體T3之控制端。如前述提及,本發明所使用的位準移位電路可為任何形式的位準移位電路,但必須要具有控制電壓與輸出的閘極電壓為同向的特性。換句話說,當電源切換裝置200在寫入模式時,第二控制電壓IN2可為低電位的電壓,以使第三位準移位電路LS3輸出低電位的第三閘極電壓GV3至第三電晶體T3之控制端而將第三電晶體T3導通。當電源切換裝置200在讀取模式時,第二控制電壓IN2可為高電位的電壓,以使第三位準移位電路LS3輸出高電位的第三閘極電壓GV3至第三電晶體T3之控制端而將第三電晶體T3截止。由於電源切換裝置200其餘元件的電路架構以及操作模式均類似於電源切換裝置100,因此其描述於此將省略。並且,加入了第三位準移位電路LS3的電源切換裝置200由於可以將第三閘極電壓GV3調整至適當的電位,因此也可以用在當寫入電壓VPP大於工作電壓VDD之讀取模式的情況。換句話說,加入了第三位準移位電路LS3的電源切換裝置200可適用於更多電位變化的寫入電壓VPP。類似電源切換裝置100的輸出,當電源切換裝置200在寫入模式時,最終會輸出與寫入電壓VPP同電位的輸出電壓VPPIN。當電源切換裝置200在讀取模式時,最終會輸出與工作電壓VDD同電位的輸出電壓VPPIN。
第3圖為第2圖之電源切換裝置200中,第三位準移位電路LS3的架構圖。應當理解的是,本發明的第三位準移位電路LS3的架構可為任何合理的位準移位電路硬體,因此第3圖所揭露的位準移位電路並不侷限本發明的揭露範圍。在第3圖中,第三位準移位電路LS3包含第七電晶體T7、第八電晶體T8、第九電晶體T9、第十電晶體T10、以及第十一電晶體T11。第七電晶體T7包含耦接於第三電晶體T3之第一端的第一端、控制端、以及耦接於第三電晶體T3之控制端的第二端。第八電晶體T8包含耦接於第七電晶體T7之第一端的第一端、耦接於第七電晶體T7之第二端的控制端、以及耦接於第七電晶體T7之控制端的第二端。第九電晶體T9包含耦接於第七電晶體T7之第二端的第一端、用以接收第二控制電壓IN2的反向電壓IN2b的控制端、以及耦接於接地端的第二端。第十電晶體T10包含耦接於第八電晶體T8之第二端的第一端、用以接收第二控制電壓IN2的控制端、以及耦接於第九電晶體T9之第二端的第二端。第十一電晶體T11包含耦接於第八電晶體T8之第一端的第一端、耦接於第七電晶體T7之第二端的控制端、以及耦接於第八電晶體T8之第一端的第二端。其中該第十一電晶體T11係為一電晶體式電容(MOSFET capacitor)。並且,第七電晶體T7、第八電晶體T8及第十一電晶體T11可為P型金屬氧化物半導體場效電晶體。第九電晶體T9及第十電晶體T10可為N型金屬氧化物半導體場效電晶體。第三位準移位電路LS3的驅動方式於下文說明。
當電源切換裝置200在寫入模式時,第二控制電壓IN2可為低電位的電壓。因此第二控制電壓IN2的反向電壓IN2b(之後直接稱為”反向電壓IN2b”)為高電位的電壓。因此,第九電晶體T9的控制端會接收到高電位的反向電壓IN2b,導致第九電晶體T9為導通。第十電晶體T10的控制端會接收到低電位的第二控制電壓IN2,導致第十電晶體T10為截止。因此,節點A的電壓會被壓降為接地電壓。由於第八電晶體T8的控制端會接收到趨近於接地電壓之節點A的電壓,因此第八電晶體T8為導通。因此,節點B的電壓會等於寫入電壓VPP。由於第七電晶體T7的控制端會接收到趨近於寫入電壓VPP之節點B的電壓,因此第七電晶體T7為截止。寫入電壓VPP無法透過第七電晶體T7傳至節點A,因此節點A將保持低電位。並且,由於節點A保持低電位,因此第三電晶體T3的控制端將接收到低電位,導致第三電晶體T3為導通。因此,寫入電壓VPP會透過第三電晶體T3傳至第四電晶體T4的第一端,導致端點電壓VPP_SW會保持在與寫入電壓VPP相同的電位。將上述的操作統整,當電源切換裝置200在寫入模式時,第二控制電壓IN2為低電位,第三位準移位電路LS3輸出的第三閘極電壓GV3(節點A的電壓)也為低電位(同向),且端點電壓VPP_SW會保持在與寫入電壓VPP相同的電位。因此,電源切換裝置200在寫入模式時,將可依據前述實施例的運作模式,最終輸出與寫入電壓VPP同電位的輸出電壓VPPIN。
當電源切換裝置200在讀取模式時,第二控制電壓IN2可為高電位的電壓。因此第二控制電壓IN2的反向電壓IN2b(之後直接稱為”反向電壓IN2b”)為低電位的電壓。因此,第九電晶體T9的控制端會接收到低電位的反向電壓IN2b,導致第九電晶體T9為截止。第十電晶體T10的控制端會接收到高電位的第二控制電壓IN2,導致第十電晶體T10為導通。因此,節點B的電壓會被壓降為接地電壓。由於第七電晶體T7的控制端會接收到趨近於接地電壓之節點B的電壓,因此第七電晶體T7為導通。因此,節點A的電壓會等於寫入電壓VPP。由於第八電晶體T8的控制端會接收到趨近於寫入電壓VPP之節點A的電壓,因此第八電晶體T8為截止。寫入電壓VPP無法透過第八電晶體T8傳至節點B,因此節點B將保持低電位。並且,由於節點A為寫入電壓VPP的電位,因此第三電晶體T3的控制端將接收到電壓VPP的電位,導致第三電晶體T3為截止。因此,端點電壓VPP_SW會依據第四電晶體T4的漏電路徑而壓降為接地電壓。將上述的操作統整,當電源切換裝置200在讀取模式時,第二控制電壓IN2為高電位,第三位準移位電路LS3輸出的第三閘極電壓GV3(節點A的電壓)也為與寫入電壓VPP相同的電位(例如9伏特,同向),端點電壓VPP_SW會壓降為接地電壓。因此,電源切換裝置200在讀取模式時,將可依據前述實施例的運作模式,最終輸出與工作電壓VDD同電位的輸出電壓VPPIN。
並且,引入第3圖之第三位準移位電路LS3架構之電源切換裝置200,還具備了電壓保護的功能。舉例而言,當第九電晶體T9以及第十電晶體T10在截止的初始化狀態,且寫入電壓VPP比第二控制電壓IN2提前升壓時,因第十一電晶體T11係為一電晶體式電容,此電容將導致節點A的電壓之升壓速率較節點B的電壓為快。當節點A的電壓升壓至第八電晶體T8的電壓門檻值時,第八電晶體T8將會被截止。此時,節點B的電壓將無法繼續透過第八電晶體T8升壓,因此其電壓會維持在約莫(VPP/2)的電位。由於節點B的電壓不夠大,因此第七電晶體T7會維持導通。節點A的電壓會維持在寫入電壓VPP的電位。因此,第三電晶體T3的控制端會接收到寫入電壓VPP之電位,而導致第三電晶體T3為截止。換句話說,在寫入電壓VPP比第二控制電壓IN2提前升壓時,異常的寫入電壓VPP不會透過第三電晶體T3去改變端點電壓VPP_SW的電位。因此,電源切換裝置200不會有異常的輸出。
第4圖為電源切換裝置100及200中,第一位準移位電路LS1的架構圖。應當理解的是,本發明的第一位準移位電路LS1的架構可為任何合理的位準移位電路硬體,因此第4圖所揭露的位準移位電路並不侷限本發明的揭露範圍。第一位準移位電路LS1包含第十二電晶體T12、第十三電晶體T13、第十四電晶體T14、以及第十五電晶體T15。第十二電晶體T12包含用以接收驅動電壓VV的第一端、控制端、以及耦接於第一電晶體T1之控制端的第二端。第十三電晶體T13包含耦接於第十二電晶體T12之第一端的第一端、耦接於第十二電晶體T12之第二端的控制端、以及耦接於第十二電晶體T12之控制端的第二端。第十四電晶體T14包含耦接於第十二電晶體T12之第二端的第一端、用以接收第一控制電壓IN1的反向電壓IN1b的控制端、以及耦接於接地端的第二端。第十五電晶體T15包含耦接於第十三電晶體T13之第二端的第一端、用以接收第一控制電壓IN1的控制端、以及耦接於第十四電晶體T14之第二端的第二端。並且,第十二電晶體T12及第十三電晶體T13可為P型金屬氧化物半導體場效電晶體。第十四電晶體T14及第十五電晶體T15可為N型金屬氧化物半導體場效電晶體。第一位準移位電路LS1的驅動方式於下文說明。
如前述提及,第一位準移位電路LS1可為任何形式的位準移位電路,但控制電壓與輸出的閘極電壓必須要有同向的特性。當電源切換裝置100及200在寫入模式時,第一控制電壓IN1可為高電位的電壓。因此第一控制電壓IN1的反向電壓IN1b(之後直接稱為”反向電壓IN1b”)為低電位的電壓。因此,第十五電晶體T15的控制端會接收到高電位的第一控制電壓IN1,導致第十五電晶體T15為導通。第十四電晶體T14的控制端會接收到低電位的反向電壓IN1b,導致第十四電晶體T14為截止。因此,第十二電晶體T12之控制端的電壓會被降壓為接地電壓,導致第十二電晶體T12為導通。由於第十二電晶體T12為導通,因此第十三電晶體T13的控制端將會透過第十二電晶體T12,接收到與驅動電壓VV相同電位的電壓,而導致第十三電晶體T13為截止。因此,第十二電晶體T12之控制端的電壓會保持接地電壓,而第十三電晶體T13之控制端的電壓會保持與驅動電壓VV相同電位的電壓。換句話說,在寫入模式時,第一位準移位電路LS1將會輸出與第一控制電壓IN1同向,且電位約等於驅動電壓VV的第一閘極電壓GV1至第一電晶體T1的控制端。
當電源切換裝置100及200在讀取模式時,第一控制電壓IN1可為低電位的電壓。因此第一控制電壓IN1的反向電壓IN1b(之後直接稱為”反向電壓IN1b”)為高電位的電壓。因此,第十五電晶體T15的控制端會接收到低電位的第一控制電壓IN1,導致第十五電晶體T15為截止。第十四電晶體T14的控制端會接收到高電位的反向電壓IN1b,導致第十四電晶體T14為導通。因此,第十三電晶體T13之控制端的電壓會被降壓為接地電壓,導致第十三電晶體T13為導通。由於第十三電晶體T13為導通,因此第十二電晶體T12的控制端將會透過第十三電晶體T13,接收到與驅動電壓VV相同電位的電壓,而導致第十二電晶體T12為截止。因此,第十三電晶體T13之控制端的電壓會保持接地電壓,而第十二電晶體T12之控制端的電壓會保持與驅動電壓VV相同電位的電壓。換句話說,在讀取模式時,第一位準移位電路LS1將會輸出與第一控制電壓IN1同向,且電位約等於接地電壓的第一閘極電壓GV1至第一電晶體T1的控制端。
第5圖為電源切換裝置100及200中,第二位準移位電路LS2的架構圖。第二位準移位電路LS2的架構以及操作方式類似於第一位準移位電路LS1,也是具有控制電壓與輸出的閘極電壓同向的特性。然而,為了描述完整性,以下仍將第二位準移位電路LS2的架構以及操作方式進行說明。應當理解的是,本發明的第二位準移位電路LS2的架構可為任何合理的位準移位電路硬體,因此第5圖所揭露的位準移位電路並不侷限本發明的揭露範圍。第二位準移位電路LS2包含第十六電晶體T16、第十七電晶體T17、第十八電晶體T18、以及第十九電晶體T19。第十六電晶體T16包含用以接收驅動電壓VV的第一端、控制端、以及耦接於第二電晶體T2之控制端的第二端。第十七電晶體T17包含耦接於第十六電晶體T16之第一端的第一端、耦接於第十六電晶體T16之第二端的控制端、以及耦接於第十六電晶體T16之控制端的第二端。第十八電晶體T18包含耦接於第十六電晶體T16之第二端的第一端、用以接收第二控制電壓IN2的反向電壓IN2b的控制端、以及耦接於接地端的第二端。第十九電晶體T19包含耦接於第十七電晶體T17之第二端的第一端、用以接收第二控制電壓IN2的控制端、以及耦接於第十八電晶體T18之第二端的第二端。並且,第十六電晶體T16及第十七電晶體T17可為P型金屬氧化物半導體場效電晶體。第十八電晶體T18及第十九電晶體T19可為N型金屬氧化物半導體場效電晶體。第二位準移位電路LS2的驅動方式於下文說明。
當電源切換裝置100及200在寫入模式時,第二控制電壓IN2可為低電位的電壓。因此第二控制電壓IN2的反向電壓IN2b(之後直接稱為”反向電壓IN2b”)為高電位的電壓。因此,第十九電晶體T19的控制端會接收到低電位的第二控制電壓IN2,導致第十九電晶體T19為截止。第十八電晶體T18的控制端會接收到高電位的反向電壓IN2b,導致第十八電晶體T18為導通。因此,第十七電晶體T17之控制端的電壓會被降壓為接地電壓,導致第十七電晶體T17為導通。由於第十七電晶體T17為導通,因此第十六電晶體T16的控制端將會透過第十七電晶體T17,接收到與驅動電壓VV相同電位的電壓,而導致第十六電晶體T16為截止。因此,第十七電晶體T17之控制端的電壓會保持接地電壓,而第十六電晶體T16之控制端的電壓會保持與驅動電壓VV相同電位的電壓。換句話說,在讀取模式時,第二位準移位電路LS2將會輸出與第二控制電壓IN2同向,且電位約等於接地電壓的第二閘極電壓GV2至第二電晶體T2的控制端。
當電源切換裝置100及200在讀取模式時,第二控制電壓IN2可為高電位的電壓。因此第二控制電壓IN2的反向電壓IN2b(之後直接稱為”反向電壓IN2b”)為低電位的電壓。因此,第十九電晶體T19的控制端會接收到高電位的第二控制電壓IN2,導致第十九電晶體T19為導通。第十八電晶體T18的控制端會接收到低電位的反向電壓IN2b,導致第十八電晶體T18為截止。因此,第十六電晶體T16之控制端的電壓會被降壓為接地電壓,導致第十六電晶體T16為導通。由於第十六電晶體T16為導通,因此第十七電晶體T17的控制端將會透過第十六電晶體T16,接收到與驅動電壓VV相同電位的電壓,而導致第十七電晶體T17為截止。因此,第十六電晶體T16之控制端的電壓會保持接地電壓,而第十七電晶體T17之控制端的電壓會保持與驅動電壓VV相同電位的電壓。換句話說,在讀取模式時,第二位準移位電路LS2將會輸出與第二控制電壓IN2同向,且電位約等於驅動電壓VV的第二閘極電壓GV2至第二電晶體T2的控制端。
綜上所述,本發明揭露了一種電源切換裝置。由於電源切換裝置內的電壓選擇器(如前述之第五電晶體以及第六電晶體組成)有經過適當設計,使一邊的電晶體所接收到的端點電壓在寫入模式時恆為寫入電壓,而在讀取模式時恆為接地電壓。因此,電壓選擇器另一邊的電晶體所接收到的電壓(工作電壓)必與寫入電壓或接地電壓不同,解決了傳統電壓選擇器在寫入電壓與工作電壓接近,且兩者相差值小於電晶體門檻值時所造成的誤輸出問題。換句話說,本發明的電源切換裝置在寫入模式與讀取模式下,無論在何種電壓條件下,都可以執行正常的電壓輸出。並且,當電源切換裝置中的位準移位電路經過適當設計後,也可以防止寫入電壓提前異常升壓的情況,因此也增加了系統的可靠度。 以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
100‧‧‧電源切換裝置
LS1至‧‧‧位準移位電路
T1至T19‧‧‧電晶體
IN1及IN2‧‧‧控制電壓
GV1至GV3‧‧‧閘極電壓
VV‧‧‧ 驅動電壓
VDD‧‧‧工作電壓
VPP‧‧‧寫入電壓
VPP_SW‧‧‧端點電壓
VPPIN‧‧‧輸出電壓
IN1b以及IN2b‧‧‧反向電壓
A及B‧‧‧節點
LS1至‧‧‧位準移位電路
T1至T19‧‧‧電晶體
IN1及IN2‧‧‧控制電壓
GV1至GV3‧‧‧閘極電壓
VV‧‧‧ 驅動電壓
VDD‧‧‧工作電壓
VPP‧‧‧寫入電壓
VPP_SW‧‧‧端點電壓
VPPIN‧‧‧輸出電壓
IN1b以及IN2b‧‧‧反向電壓
A及B‧‧‧節點
第1圖係為本發明之電源切換裝置之第一實施例的架構圖。 第2圖係為本發明之電源切換裝置之第二實施例的架構圖。 第3圖係為第2圖之電源切換裝置中,第三位準移位電路的架構圖。 第4圖係為第1圖及第2圖之電源切換裝置中,第一位準移位電路的架構圖。 第5圖係為第1圖及第2圖之電源切換裝置中,第二位準移位電路的架構圖。
Claims (13)
- 一種電源切換裝置,包含: 一第一位準移位電路(Level Shift Circuit),用以根據一驅動電壓調整一第一控制電壓的位準,以產生一第一閘極電壓; 一第一電晶體,包含: 一第一端,用以接收一工作電壓; 一控制端,耦接於該第一位準移位電路,用以接收該第一閘極電壓;及 一第二端,用以輸出一輸出電壓; 一第二電晶體,包含: 一第一端; 一控制端;及 一第二端,耦接於該第一電晶體之該第二端; 一第二位準移位電路,耦接於該第二電晶體之該控制端,用以根據該驅動電壓調整一第二控制電壓的位準,以產生一第二閘極電壓至該第二電晶體之該控制端; 一第三電晶體,包含: 一第一端,用以接收一寫入電壓; 一控制端,用以接收一第三閘極電壓;及 一第二端,耦接於該第二電晶體之該第一端; 一第四電晶體,包含: 一第一端,耦接於該第三電晶體之該第二端; 一控制端,用以接收該第二控制電壓,及 一第二端,耦接於一接地端; 一第五電晶體,包含: 一第一端,用以接收該工作電壓; 一控制端,耦接於該第四電晶體之該第一端;及 一第二端,用以輸出該驅動電壓;及 一第六電晶體,包含: 一第一端,耦接於該第四電晶體之該第一端; 一控制端,耦接於該第五電晶體之該第一端;及 一第二端,耦接於該第五電晶體之該第二端。
- 如請求項1所述之電源切換裝置,其中該第一電晶體、該第二電晶體、該第三電晶體、該第五電晶體及該第六電晶體係為P型金屬氧化物半導體場效電晶體,且該第四電晶體係為N型金屬氧化物半導體場效電晶體。
- 如請求項1所述之電源切換裝置,其中當電源切換裝置在一寫入模式時,該寫入電壓大於該工作電壓,該第一控制電壓大於該第二控制電壓,該第三閘極電壓等於該第二控制電壓。
- 如請求項3所述之電源切換裝置,其中當電源切換裝置在該寫入模式時,該第四電晶體之該第一端的一電壓等於該寫入電壓,該驅動電壓等於該寫入電壓,且該輸出電壓等於該寫入電壓。
- 如請求項1所述之電源切換裝置,其中當電源切換裝置在一讀取模式時,該寫入電壓小於或等於該工作電壓,該第一控制電壓小於該第二控制電壓,該第三閘極電壓等於該第二控制電壓。
- 如請求項5所述之電源切換裝置,其中當電源切換裝置在該讀取模式時,該第四電晶體之該第一端的一電壓等於一接地電壓,該驅動電壓等於該工作電壓,且該輸出電壓等於該工作電壓。
- 如請求項1所述之電源切換裝置,另包含: 一第三位準移位電路,耦接於該第三電晶體之該控制端,用以根據該寫入電壓調整該第二控制電壓的位準,以產生該第三閘極電壓至該第三電晶體之該控制端。
- 如請求項7所述之電源切換裝置,其中該第三位準移位電路包含: 一第七電晶體,包含: 一第一端,耦接於該第三電晶體之該第一端; 一控制端;及 一第二端,耦接於該第三電晶體之該控制端; 一第八電晶體,包含: 一第一端,耦接於該第七電晶體之該第一端; 一控制端,耦接於該第七電晶體之該第二端;及 一第二端,耦接於該第七電晶體之該控制端; 一第九電晶體,包含: 一第一端,耦接於該第七電晶體之該第二端; 一控制端,用以接收該第二控制電壓的反向電壓;及 一第二端,耦接於該接地端;及 一第十電晶體,包含: 一第一端,耦接於該第八電晶體之該第二端; 一控制端,用以接收該第二控制電壓;及 一第二端,耦接於該第九電晶體之該第二端;及 一第十一電晶體,包含: 一第一端,耦接於該第八電晶體之該第一端; 一控制端,耦接於該第七電晶體之該第二端;及 一第二端,耦接於該第八電晶體之該第一端。
- 如請求項8所述之電源切換裝置,其中該第七電晶體、該第八電晶體及該第十一電晶體係為P型金屬氧化物半導體場效電晶體,且該第九電晶體及該第十電晶體係為N型金屬氧化物半導體場效電晶體。
- 如請求項1所述之電源切換裝置,其中該第一位準移位電路包含: 一第十二電晶體,包含: 一第一端,用以接收該驅動電壓; 一控制端;及 一第二端,耦接於該第一電晶體之該控制端; 一第十三電晶體,包含: 一第一端,耦接於該第十二電晶體之該第一端; 一控制端,耦接於該第十二電晶體之該第二端;及 一第二端,耦接於該第十二電晶體之該控制端; 一第十四電晶體,包含: 一第一端,耦接於該第十二電晶體之該第二端; 一控制端,用以接收該第一控制電壓的反向電壓;及 一第二端,耦接於該接地端;及 一第十五電晶體,包含: 一第一端,耦接於該第十三電晶體之該第二端; 一控制端,用以接收該第一控制電壓; 一第二端,耦接於該第十四電晶體之該第二端。
- 如請求項10所述之電源切換裝置,其中該第十二電晶體及該第十三電晶體係為P型金屬氧化物半導體場效電晶體,且該第十四電晶體及該第十五電晶體係為N型金屬氧化物半導體場效電晶體。
- 如請求項1所述之電源切換裝置,其中該第二位準移位電路包含: 一第十六電晶體,包含: 一第一端,用以接收該驅動電壓; 一控制端;及 一第二端,耦接於該第二電晶體之該控制端; 一第十七電晶體,包含: 一第一端,耦接於該第十六電晶體之該第一端; 一控制端,耦接於該第十六電晶體之該第二端;及 一第二端,耦接於該第十六電晶體之該控制端; 一第十八電晶體,包含: 一第一端,耦接於該第十六電晶體之該第二端; 一控制端,用以接收該第二控制電壓的反向電壓;及 一第二端,耦接於該接地端;及 一第十九電晶體,包含: 一第一端,耦接於該第十七電晶體之該第二端; 一控制端,用以接收該第二控制電壓; 一第二端,耦接於該第十八電晶體之該第二端。
- 如請求項12所述之電源切換裝置,其中該第十六電晶體及該第十七電晶體係為P型金屬氧化物半導體場效電晶體,且該第十八電晶體及該第十九電晶體係為N型金屬氧化物半導體場效電晶體。
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