CN107045463A - 具有纠错码的存储器架构以及其操作方法 - Google Patents

具有纠错码的存储器架构以及其操作方法 Download PDF

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CN107045463A
CN107045463A CN201710044102.7A CN201710044102A CN107045463A CN 107045463 A CN107045463 A CN 107045463A CN 201710044102 A CN201710044102 A CN 201710044102A CN 107045463 A CN107045463 A CN 107045463A
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circuit
phase
data
ecc
ecc circuit
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CN107045463B (zh
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黄柏豪
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eMemory Technology Inc
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Abstract

具有纠错码的存储器架构以及其操作方法。该架构用于在存储器装置中操作纠错码，包括控制电路及纠错码(ECC)电路。该纠错码电路与该控制电路耦接。该控制电路接收字节的第一数据，以将该数据反相成为反相数据。该纠错码电路接收该反相数据，以进行加密或解密以及输出第二数据。

Description

具有纠错码的存储器架构以及其操作方法
技术领域
本发明涉及一种存储器架构，且特别涉及一种具有纠错码功能的存储器架构。
背景技术
对于存储器装置的基本架构，其包含记忆胞阵列以及多种外围电路以存取记忆胞阵列的记忆胞。记忆胞阵列是存储数据的核心部分。然而，存储于记忆胞阵列中的数据可能有错误，其数据的一个位可能会从原本要写入的位被翻转。当数据对记忆胞阵列要被写入或是读出时，为了修正在记忆胞阵列中的错误位，纠错码(error-correcting code，ECC)电路会被使用，根据奇偶(parity)校验以检测错误位接着修正此错误位。
多种演算方法可以被使用在ECC电路。对于其中的一种演算方法，其是以校验例如32位的数据组中的“1”的数量为偶数为根据。然而当记忆胞阵列的记忆胞原始数据都是“1”，例如是FFFF-FFFF时，其中一个字是由四个位构成，一个“F”代表“1111”的四个位，则ECC电路可能会改变初始数据。
ECC电路对数据“FFFF-FFFF”所造成的错误如下。举一例，对于具有32位I/O的ECC电路，其会有六个修正码，或是位。当数据“FFFF-FFFF”的32位输入到ECC电路进行加密(encryption)时，经过ECC加密后的数据总共会具有38位，其中已包含“01 1000”的六位而得到“3F-FFFF-FFD8”，其会被存储到记忆胞阵列。然后，“3F-FFFF-FFD8”的数据从记忆胞阵列被读出。在实际输出前，“3F-FFFF-FFD8”的数据会进入ECC电路进行解密(decryption)，以移除ECC而得到32位的“FFFF-FFFF”的输出数据。然而，存储器刚出厂时，从记忆胞阵列被读出的数据是“3F-FFFF-FFFF”，而不是“3F-FFFF-FFD8”。这会造成第一次读出的是失败。这种情况特别可能存在于初始数据为“FFFF-FFFF”时。
如何有效解决上述的议题，对于ECC电路的设计是需要被考虑的。
发明内容
本发明提供具有ECC功能的存储器架构，其中ECC功能可以维持其功能，但是对于输入到ECC电路的数据会被反相，而从ECC电路输出的数据也会被反相。
在一实施例，本发明提供一种具有纠错码功能的存储器架构。该存储器架构包括记忆胞阵列，用以存储多位的数据。纠错码(ECC)电路，用以对具有纠错码的通过数据加密或解密。第一控制电路，连接于该ECC电路与该记忆胞阵列之间。第二控制电路，连接于该ECC电路与数据输入/输出(I/O)端之间。当该I/O端的输入数据要被写入到该记忆胞阵列时，该第二控制电路在该输入数据进入该ECC电路进行加密之前对该输入数据反相，以及该第一控制电路对该ECC电路的输出反相，而写入到该记忆胞阵列。当该记忆胞阵列的输出数据要被读出时，该输出数据在进入该ECC电路进行解密之前由该第一控制电路反相，以及该第二控制电路对该ECC电路的输出反相，而当作读出数据。
在一实施例，对于所述的存储器架构，该ECC电路是汉明码(Hamming code)ECC电路。
在另一实施例，对于所述的存储器架构，该输入数据包含一字节，以及该多个位被分成多个群，该多个群是两两相交，且该ECC电路提供多个奇偶位以对每一个该群修正使得具有“1”的位的总数量为偶数。
在另一实施例，对于所述的存储器架构，该ECC电路包含加密电路与解密电路，以分别构成加密路径与解密路径。
在另一实施例，对于所述的存储器架构，该第一控制电路在分别的该加密电路与该解密电路中包含第一反相器与第二反相器，其中该第一反相器对该ECC电路的该输出反相以写入到该记忆胞阵列，以及该第二反相器对从该记忆胞阵列的该输出数据反相以进入到该ECC电路进行解密。该第二控制电路在分别的该加密电路与该解密电路中包含第三反相器与第四反相器，其中该第三反相器对该输入数据反相以进入到该ECC电路进行加密，以及该第四反相器对经该ECC电路解密后的该输出反相以提供该读出数据。
在另一实施例，对于所述的存储器架构，该加密路径与该解密路径被多功处理，如此该第一到第四反相器的至少两个是共用相同的一个反相器。
在另一实施例，本发明提供一种存储器装置的操作方法，其中该存储器装置包含记忆胞阵列、纠错码(ECC)电路、第一控制电路及第二控制电路。该ECC电路用以对具有纠错码的通过数据加密或解密。该操作方法包括:连接该第一控制电路在该ECC电路与该记忆胞阵列之间；连接该第二控制电路在该ECC电路与数据输入/输出(I/O)端之间；当从该I/O端来的一字节的输入数据要被写入到该记忆胞阵列时进行程序模式，该第二控制电路在该输入数据进入该ECC电路进行加密之前对该输入数据反相，以及该第一控制电路对该ECC电路的输出反相，而写入到该记忆胞阵列；以及当该记忆胞阵列的输出数据要被读出时进行读出模式，对该输出数据在进入该ECC电路进行解密之前由该第一控制电路反相，以及该第二控制电路对该ECC电路的输出反相，而当作读出数据。
在另一实施例，对于所述的操作方法，该ECC电路是汉明码(Hamming code)ECC电路，以进行加密处理与解密处理。
在另一实施例，对于所述的操作方法，该输入数据包含一字节，以及该多个位被分成多个群，该多个群是两两相交，且该ECC电路提供多个奇偶位以对每一个该群修正使得具有“1”的位的总数量为偶数。
在另一实施例，对于所述的操作方法，其还包括提供具有加密电路与解密电路的该ECC电路，以分别构成加密路径与解密路径。
在另一实施例，对于所述的操作方法，其还包括提供在该加密电路与该解密电路中分别具有第一反相器与第二反相器的该第一控制电路，其中该第一反相器对该ECC电路的该输出反相以写入到该记忆胞阵列，以及该第二反相器对从该记忆胞阵列的该输出数据反相以进入到该ECC电路进行解密；更提供在该加密电路与该解密电路中分别具有第三反相器与第四反相器的该第二控制电路，其中该第三反相器对该输入数据反相以进入到该ECC电路进行加密，以及该第四反相器对经该ECC电路解密后的该输出反相以提供该读出数据。
在另一实施例，对于所述的操作方法，其还包括对该加密路径与该解密路径进行多功处理，如此该第一到第四反相器的至少两个是共用相同的一个反相器。
在另一实施例，本发明提供一种操作存储器装置的方法。此方法包括:在程序模式下接收输入数据；藉由控制电路对该输入数据反相，成为第一反相数据；提供纠错码(ECC)电路，以接收该第一反相数据以进行加密与输出加密数据；藉由该控制电路对该加密数据反相及写入到记忆胞阵列；在读出模式下使用该控制电路，以对从该记忆胞阵列读出的输出数据反相成第二反相数据；藉由该ECC电路对该第二反相数据解密；以及藉由该控制电路，对该解密数据反相成为读出数据。
在另一实施例，对于所述的方法，该控制电路对应加密与解密包含多个反相器，以对通过数据反相。
在另一实施例，对于所述的方法，其还包括对该加密路径与该解密路径进行多功处理，如此该第一到第四反相器的至少两个是共用相同的一个反相器。
在另一实施例，对于所述的方法，其中该输入数据包含一字节，以及该多个位被分成多个群，该多个群是两两相交，且该ECC电路提供多个奇偶位以对每一个该群修正使得具有“1”的位的总数量为偶数。
附图说明
包含附图是以进一步理解本发明，且附图并入本说明书中并且构成本说明书的一部分。附图说明本发明的实施例，并且与描述一起用于解释本发明的原理。
图1依据本发明一实施例，绘示存储器架构示意图。
图2依据本发明一实施例，绘示操作ECC的电路架构示意图。
图3依据本发明一实施例，绘示ECC产生奇偶位的机制示意图。
图4依据本发明一实施例，绘示ECC修正错误位的机制示意图。
图5依据本发明一实施例，绘示ECC操作加密的机制示意图。
图6依据本发明一实施例，绘示ECC操作解密的机制示意图。
附图标号说明
50:存储器装置
100：记忆胞阵列
102：驱动器
104:Y电路/感应放大器
106:感应放大器控制电路
108:控制器
110:ECC电路
112:ECC电路
112a:加密路径
112b:解密路径
113:模拟电路
114:控制电路
114a、114b:反相器
115:电源开关
116:控制电路
116a、116b:反相器
117:高电压系统(电荷泵)
具体实施方式
以下举一些实施例配合附图来较详细说明本发明。在附图中相同的构件符号代表相同或相似的构件。
本发明提出一种ECC操作，其可以避免ECC的错误，其特别可能发生于存取存储在记忆胞阵列的初始数据。此ECC可以维持其功能，但是对于输入到ECC电路的数据会被反相，而从ECC电路输出的数据也会被反相。
提供的多个实施例是用来描述本发明，但是不是用来限制本发明。
图1依据本发明一实施例，绘示存储器架构示意图。参阅图1，存储器装置50一般包括记忆胞阵列100及多种外围元件来控制与存取记忆胞阵列100。这些外围元件于一实施例可以包括驱动器102、Y电路/感应放大器104、感应放大器控制电路(SACTL)106、控制器(CTL)108、ECC电路110、模拟电路113、电源开关115以及高电压系统117。多个终端点例如控制总线、地址总线及输入/输出(I/O)总线等，也被提供来与外部的主机互通以存取记忆胞阵列100。存储器装置50的基本架构与操作是本技术领域一般可知的技术，于此不予详细描述。
然而，本发明是关于ECC电路110的操作。以下的描述将针对本发明提出的ECC电路110的功能进行描述。
要被写入记忆胞阵列100而存储的输入数据DIN，会先通过ECC电路110以ECC来加密，其中ECC电路110可以产生修正码，其在之后的数据有发生错误位时就可以修正此错误位。ECC电路110于是输出此数据DATA，其是实际被写入记忆胞阵列100而存储。另一方面，当输出数据OUT从记忆胞阵列100要被外部主机读出时，输出数据OUT也会进入ECC电路110进行解密，接着输出当作读取数据PDOUT。
本发明所提出具有修改结构的ECC电路110，可以避免当数据的值是FFFF-FFFF时所可能发生的错误。图2依据本发明一实施例，绘示操作ECC的电路架构示意图。
参阅图2，ECC电路110是在I/O端与记忆胞阵列100之间的中间元件。本发明不需要修改原始的ECC电路112。然而，本发明加入控制电路，其在一范例中为了方便配置可以包括第一控制电路114与第二控制电路116。ECC电路112可以被分为加密路径(En)112a与解密路径(De)112b。如此，如本发明所提出的ECC电路110具有第一控制电路114连接于ECC电路112与记忆胞阵列100之间，且第二控制电路116连接于ECC电路112与数据I/O端。
当从数据I/O端来的输入数据DIN要被写入到记忆胞阵列100，第二控制电路116在输入数据DIN要通过加密路径112a进入ECC电路112进行加密之前，将输入数据DIN反相，而第一控制电路114对从ECC电路112的输出反相成为数据，标示为DATA，而通过在Y电路/感应放大器104中的写入电路而写入到记忆胞阵列100。当如标示为OUT的输出数据从记忆胞阵列100被在Y电路/感应放大器104中的感应放大器读出。输出数据OUT在通过解密路径112b进入ECC电路112进行解密之前被第一控制电路114反相，并且第二控制电路116对从ECC电路112的输出反相而视为读出数据，如PDOUT的标示。
更详细地，第一控制电路114包括第一反相器114a与第二反相器114b分别在加密路径112a与解密路径112b中，其中第一反相器114a对从ECC电路112的输出反相以写入到记忆胞阵列100，以及第二反相器114b对从记忆胞阵列100读出的输出数据反相以进入到ECC电路112进行解密。另一方面，第二控制电路116包含第三反相器116a与第四反相器116b，分别在加密路径112a与解密路径112b中，其中第三反相器116a对输入数据DIN反相，以进入ECC电路112进行解密，且第四反相器116b对从ECC电路112经解密后的输出反相，以提供读出数据PDOUT。
在描述本发明所提出的ECC电路110的效果之前，先提供ECC的操作范例。图3依据本发明一实施例，绘示ECC产生奇偶位的机制示意图。参阅图3，以传送由四个位所构成的字节为例，例如是1101，以及三个位被加入当作奇偶位。总共7个位被传送，其中这7个位被编号成1到7的码号。此7个位例如被分成三群A、B、C。这些群是两两相交，其关系如左上所示。其结果，码号1-7的码值是1101010，其中前面四个位代表数据。在ECC加密中，每一个群有四个位且需要符合“1”的总数量为偶数。
图4依据本发明一实施例，绘示ECC修正错误位的机制示意图。参阅图4，要被传送的数据需要是1101010，如左上所示。然而，存储在记忆胞阵列100的数据可能是1101000。ECC电路112，例如是(7，4)汉明码(Hamming code)电路，可以将1101000的数据解密为1101010。这是因为群B有奇数个位是“1”，因此在码号6的奇偶位会被修正为“1”。于此，依照在(7，4)汉明码(Ha电路的操作，位的总数量为7，但是仅有四个位是原始要被传送。
接着描述本发明提出的ECC电路110的操作机制。图5依据本发明一实施例，绘示ECC操作加密的机制示意图。参阅图5，对于要加密的一个特殊情形，其输入数据DIN的所有位刚好全都是“1”，例如32位的FFFF-FFFF。反相器116a将数据反相成反相数据DINB，其是0000-0000，于是进入到ECC电路112的加密路径112a。因为数据是“0”，其仍符合位为“1”的数量是偶数的条件。奇偶位会维持“0”，而不必加入“1”的位。于是，38个位都是“0”的数据被再次被反相器114a反相成为3F-FFF-FFF的数据DATA，其要被写入记忆胞阵列100。
图6依据本发明一实施例，绘示ECC操作解密的机制示意图。参阅图6，数据从记忆胞阵列100被读出以进行解密。于是，由记忆胞阵列100读出的输出数据OUT的所有38位都是“1”，如3F-FFFF-FFFF。再一次，反相器114b将数据OUT反相成数据OUTB，其接着进入到ECC电路112的解密路径112b。于此，数据OUTB的所有位都是“0”，如此ECC电路112不会改变数据而将为“0”的所有位输出。再一次，反相器116b将“0”的所有位反相成“1”，当作读出数据PDOUT，其在移除ECC后会维持原始的FFFF-FFFF的形式。
需要注意的是，多个反相器被用来描述其机制。然而，因为反相器都是相同的功能，如此这些反相器可以共用相同的一个反相器。换句话说，通过路径的安排以及使用多功器，第一与第三反相器可以共用相同的一个反相器，而第二与第四反相器可以共用相同的一个反相器。甚至，第一到第四反相器也可以共用相同的一个反相器，其中路径的选择机制需要被加入。换句话说，加密路径112a与解密路径112b的每一个会涉及两次的反相操作，其中的硬件的安排不必限制于前面所举的实施例。
此ECC电路可以避免当初始数据的位被设为“1”时，其数据被写入与读出时的不一致。ECC电路可以与其他类型的ECC电路相容，这是因为两次的反相处理不会改变其他类型的ECC电路的结果。
虽然本发明已以实施例公开如上，然其并非用以限定本发明，本领域技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视所附权利要求书界定范围为准。

Claims (16)

1.一种具有纠错码功能的存储器架构，该存储器架构包括：
记忆胞阵列，用以存储多个位的数据；
纠错码ECC电路，用以对具有纠错码的通过数据加密或解密；
第一控制电路，连接于该ECC电路与该记忆胞阵列之间；以及
第二控制电路，连接于该ECC电路与数据输入/输出I/O端之间，
其中当该I/O端的输入数据要被写入到该记忆胞阵列时，该第二控制电路在该输入数据进入该ECC电路进行加密之前对该输入数据反相，以及该第一控制电路对该ECC电路的输出反相，而写入到该记忆胞阵列，
其中当该记忆胞阵列的输出数据要被读出时，该输出数据在进入该ECC电路进行解密之前由该第一控制电路反相，以及该第二控制电路对该ECC电路的输出反相，而当作读出数据。
2.根据权利要求1所述的存储器架构，其中该ECC电路是汉明码(Hamming code)ECC电路。
3.根据权利要求1所述的存储器架构，其中该输入数据包含一字节，以及该多个位被分成多个群，该多个群是两两相交，且该ECC电路提供多个奇偶位以对每一个该群修正使得具有“1”的位的总数量为偶数。
4.根据权利要求1所述的存储器架构，其中该ECC电路包含加密电路与解密电路，以分别构成加密路径与解密路径。
5.根据权利要求4所述的存储器架构，
其中该第一控制电路在分别的该加密电路与该解密电路中包含第一反相器与第二反相器，其中该第一反相器对该ECC电路的该输出反相以写入到该记忆胞阵列，以及该第二反相器对从该记忆胞阵列的该输出数据反相以进入到该ECC电路进行解密，其中该第二控制电路在分别的该加密电路与该解密电路中包含第三反相器与第四反相器，其中该第三反相器对该输入数据反相以进入到该ECC电路进行加密，以及该第四反相器对经该ECC电路解密后的该输出反相以提供该读出数据。
6.根据权利要求5所述的存储器架构，其中该加密路径与该解密路径被多功处理，如此该第一到第四反相器的至少两个是共用相同的一个反相器。
7.一种存储器装置的操作方法，其中该存储器装置包含记忆胞阵列、纠错码ECC电路、第一控制电路及第二控制电路，该ECC电路用以对具有纠错码的通过数据加密或解密，该操作方法包括:
连接该第一控制电路在该ECC电路与该记忆胞阵列之间；
连接该第二控制电路在该ECC电路与数据输入/输出I/O端之间；
当从该I/O端来的一字节的输入数据要被写入到该记忆胞阵列时进行程序模式，该第二控制电路在该输入数据进入该ECC电路进行加密之前对该输入数据反相，以及该第一控制电路对该ECC电路的输出反相，而写入到该记忆胞阵列；以及
当该记忆胞阵列的输出数据要被读出时进行读出模式，对该输出数据在进入该ECC电路进行解密之前由该第一控制电路反相，以及该第二控制电路对该ECC电路的输出反相，而当作读出数据。
8.根据权利要求7所述的存储器装置的操作方法，其中该ECC电路是汉明码(Hammingcode)ECC电路，以进行加密处理与解密处理。
9.根据权利要求7所述的存储器装置的操作方法，其中该输入数据包含一字节，以及该多个位被分成多个群，该多个群是两两相交，且该ECC电路提供多个奇偶位以对每一个该群修正使得具有“1”的位的总数量为偶数。
10.根据权利要求7所述的存储器装置的操作方法，还包括提供具有加密电路与解密电路的该ECC电路，以分别构成加密路径与解密路径。
11.根据权利要求10所述的存储器装置的操作方法，还包括:
提供在该加密电路与该解密电路中分别具有第一反相器与第二反相器的该第一控制电路，其中该第一反相器对该ECC电路的该输出反相以写入到该记忆胞阵列，以及该第二反相器对从该记忆胞阵列的该输出数据反相以进入到该ECC电路进行解密；以及
提供在该加密电路与该解密电路中分别具有第三反相器与第四反相器的该第二控制电路，其中该第三反相器对该输入数据反相以进入到该ECC电路进行加密，以及该第四反相器对经该ECC电路解密后的该输出反相以提供该读出数据。
12.根据权利要求11所述的存储器装置的操作方法，还包括对该加密路径与该解密路径进行多功处理，如此该第一到第四反相器的至少两个是共用相同的一个反相器。
13.一种操作存储器装置的方法，包括:
在程序模式下，接收输入数据；
藉由控制电路对该输入数据反相，成为第一反相数据；
提供纠错码(ECC)电路，以接收该第一反相数据以进行加密与输出加密数据；
藉由该控制电路对该加密数据反相及写入到记忆胞阵列；
在读出模式下使用该控制电路，以对从该记忆胞阵列读出的输出数据反相成第二反相数据；
藉由该ECC电路对该第二反相数据解密；以及
藉由该控制电路，对该解密数据反相成为读出数据。
14.根据权利要求13所述的操作存储器装置的方法，其中该控制电路对应加密与解密包含多个反相器，以对通过数据反相。
15.根据权利要求14所述的操作存储器装置的方法，还包括对该加密路径与该解密路径进行多功处理，如此该第一到第四反相器的至少两个是共用相同的一个反相器。
16.根据权利要求13所述的操作存储器装置的方法，其中该输入数据包含一字节，以及该多个位被分成多个群，该多个群是两两相交，且该ECC电路提供多个奇偶位以对每一个该群修正使得具有“1”的位的总数量为偶数。
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