TWI344152B - Memory circuits and malfunction protection methods thereof - Google Patents

Description

1344152 _ Patent Specification No. 96135125 Revision of the revised page of April 19, 1995. IX. Description of the Invention: [Technical Field] The present invention relates to a memory circuit, and more particularly to a memory circuit capable of avoiding The false programming caused by the power-up sequence. [Prior Art] Fuse elements are widely used in semiconductor devices for recording wafer numbers or serial numbers. In general, in order to disconnect a fuse element from other elements in a semiconductor φ device, each fuse element will contain a fuse that can be blown (i.e., broken). For example, the fuse can be illuminated by a laser until it is broken, or it is blown by an overcurrent that is capable of dissipating sufficient heat. Breaking the fuse by overcurrent is different from using a laser, which can even be performed after the semiconductor device is packaged, commonly referred to as an electrically programmed fuse. In addition, the fuses that allow this type of programming are called electrically burnable fuses or electrically programmable fuses, or simply e-fuse, and most of the fuses can only be burned once, with In order to provide state 0 and state 1 corresponding to the high and low impedance states, the reverse is also true. SUMMARY OF THE INVENTION The present invention provides a memory circuit including a burn-in unit, a switching element, and a level adjuster. The programmable unit includes a plurality of combinable components; and a power bus bar coupled between an external programming voltage and the recordable component; and a switching component connected to the external programming power 0758-A32551TWFl (20110221) 6 1344152 】April of the following year]9曰Revision and replacement page No. 96135125 Patent Specification Amendment between the power supply bus and the power supply bus, and the voltage level of a quasi-adjustable energy signal is adjusted by a second power supply voltage to a first a power supply voltage, wherein the second power supply voltage is lower than the external programming money, and when the power supply starting process t the second power supply is not ready, the level adjustment: setting the control end of the switching element to a predetermined logic level, so that the switch The device is turned off and the power bus is disconnected from the external programming voltage to avoid false programming (fa). The present invention also provides a memory circuit comprising: a power supply unit for providing an external programming voltage; and a programmable unit coupled to the power supply unit, including a plurality of programmable elements, - the power sink row 'and the power bus bar to connect to the external burning electric castle; and - burning, heart _ can burn components, and the programming circuit includes the complex drive "connected to the burnable component" and - the first The level adjustment cry is powered by at least the -th power supply voltage. The first power supply voltage is lower than; the part, the recording, the pressure 'when the first power supply ink is not ready during the power-on process, the younger-level regulator system Setting the output terminal to a certain level enables the driver in the programming circuit to be disabled, so as to avoid erroneous burning. The present invention also provides a method for protecting a memory circuit from malfunction. The memory circuit includes a plurality of burnable components, a programming circuit, and a sensing circuit. The malfunction protection method includes setting a switching element between the component and an external programming voltage; setting a first bit: Ίcoupled to The closing element - a control terminal; and when the power supply is activated through two private brother in the power supply voltage is not ready, the control terminal of the switching element

0758-Α32551TWF1 (2011 〇221) 7 S 1344152 Patent Specification No. 96135125 Revised this April 19th, 19th, the correction replacement page is set to a first logic level, so that the switching element is turned off, and the power bus will be external The programming voltage is disconnected. The above and other objects, features, and advantages of the present invention will become more apparent and understood. An embodiment of a memory circuit. As shown, the memory circuit 100 includes an electrical burnable unit 110 (e.g., e-fuse % bank), a sensing circuit 112, and a programming circuit 114. The electrically recordable unit 110 includes a plurality of fuse elements, and each of the fuse elements has a fuse to be blown (ie, Rf 〇, Rfl 〜 Rfn) and an NMOS transistor (ie, TO, used as a current source). T1 ~ Τη). The fuses RfO~Rfn may be salicide polysilicon resistors, and the MOS transistors TO~Τn may be thin gate devices or thick gate devices (thick gate devices) Gate device). The reference wire Rref is also coupled to the sensing circuit 112 for distinguishing the unblowed fuse from the burnt fuse. The sensing circuit 112 starts the reading operation and outputs the compared data DATA<0:n> by the address ADD<0:n> to be sensed and a read enable signal RE. The programming circuit 114 burns the corresponding fuse in the electric burnable unit 110 by the bit ±_1b ADD<0:n> to be burned and a burn-in enable signal PE. The fuses RfO~Rfn are respectively connected to an external programming voltage EPS by a power bus bar 111 and a resistor RP, for example, a wire power supply (fuse 0758-A32551TWFl (20110221) 8 1344152 _- • No. 96135125 The patent specification amends the revised replacement page 'source' or a power supply voltage on April 19, 100. Since a stable and stable J state current is required during the programming process, the resistance value of the current path from the external programming voltage EPS to the power bus bar 111 is kept as low as possible. If the current source (ie, NMOS transistors TO~Τη) is implemented by a voltage input/output device (ie, a thick gate device), the sensing circuit 112 and the programming circuit 114 may need to use multiple power supply voltages and A complex level regulator that converts the core power level signal into an input/input power level signal. Figure 2 is an embodiment of a sensing circuit. As shown, sensing circuit 112 includes a plurality of level adjusters (collectively LS12), complex and gates AG00~AGOn, and complex sensors SA0~SAn. The level adjuster LS12 is coupled to a core power supply voltage VDD_CORE and an input/output (I/O) power supply voltage VDD_IO for using the address to be sensed ADD<0:n> and reading enable Signal RE, a signal that is adjusted to the I/O supply voltage level by a signal at the core supply voltage level. The sensors SA0~SAn are each coupled to a corresponding fuse and a reference fuse Rref, and the gates AG00~AGOn are used to drive the sensors SA0~San according to the address ADD<0:n> Output the compared data. Figure 3 is an embodiment of a programming circuit. As shown, the programming circuit 114 includes a plurality of level adjusters (collectively referred to as LS14) and a complex AND gate AGIO~AGln. The level adjuster LS14 is coupled to a core power supply voltage VDD_CORE and an input/output (I/O) power supply voltage VDD_IO for enabling the address to be burned ADD<0:n> and programming enable The signal PE is a signal that is adjusted to a level of the I/O power supply voltage by a signal of the core power supply voltage level. Each gate AGIO~AGln is used as a drive.

S 0758-A32551TWFK20110221) 9 1344152 Revision of the patent specification No. 96135125 Revision of the replacement page on April 19 of the following year ---- and connection of a corresponding fuse and reference fuse Rref. When receiving the burn-in enable signal PE from the level adjuster LS14, the gates AGIO~AGln blow the fuse according to the address ADD<Om>. However, if a serial power regulator is used, it will most likely produce a power-up sequence as shown in Figure 4. For example, the I/O supply voltage VDD_IO (eg, 3.3 V) is ahead of the external programming voltage EPS (eg, 2.5V) and the core supply voltage VDD_CORE (eg, 1.0V). Therefore, when the I/O power supply voltage VOD_IO is ready, the core power supply voltage VDD_CORE is still invalid (not yet ready), at this time | the external programming voltage EPS can be any value, so that the power is in the period T1 The burnable unit 110 is in an unknown state. This condition may result in an unexpected or erroneous burning action. In some embodiments, the NMOS transistors (ie, T0~Τη) in the programmable cell 110 are implemented by a thin gate device, so the sensing circuit 112 and the programming circuit 114 only need the core power supply voltage VDD_CORE, so Its level adjuster can be omitted. However, these embodiments still need to maintain the power_start sequence of the external programming voltage EPS and the core power supply voltage VDD_CORE so that the core power supply voltage VDD_CORE must be ready earlier than the external programming voltage EPS to avoid Unexpected or incorrectly burned action. In order to avoid these situations, the present invention further provides some embodiments of memory circuits that are capable of avoiding unexpected or erroneous programming. Figure 5 is another embodiment of a memory circuit. As shown in the figure, the 'memory circuit 100' includes an electric burn-in unit 110", a sensing 0758-A3255ITWFK20I1022I) 10 1344152 Patent Specification No. 96135125, and a revised replacement circuit on April 19, 2010. 112", a programming circuit] M,, a switching element 116, a quasi-adjusted state LS16, an electrostatic discharge (ESD) protection circuit 118, a power supply unit 120, and a resistor Rp, for example, The memory circuit 1〇〇,, • can be a non-volatile memory, an electrically programmable memory (eiectrical, Pr〇grammable memory), a single-time read-only memory (〇nce time programmable read only memory; 0Tp R0M), but is not limited thereto. The power supply unit 120 is configured to provide an external programming voltage Eps (for example, a fuse power supply or a power supply voltage) to the electrically recordable unit. _Electrically recordable unit 11"" includes a plurality of fuse elements, each fuse element including a fuse for being blown (for example, Rf 〇, Rfl 〜 Rfn) and an NMOS transistor as a current source ( For example, TO, T1~Τη). For example, the Rf〇~Rfn system of the wire can be a salicide polysilicon resistor, and the MOS transistor T0~Τη can be a thin gate. A (thin gate device) or a thick gate device. The reference fuse Rref is also coupled to the sensing circuit in" for distinguishing between an unblowed fuse and a blown fuse, and a fuse Rf0~Rfn^ and Rref are connected to an external programming voltage EPS through a power busbar 111" and a resistor RP". The electrically recordable unit 110" can be a non-volatile and electrically recordable unit, such as an e-fuse bank, a flash memory, a once-burning type memory unit, but is not limited thereto. The 112" and the programming circuit 114" are similar to the sensing circuit 112 shown in FIGS. 2 and 3, and the programming circuit 112 is similar in that the core power supply voltage VDD_CORE is not ready when the power is turned on. The regulators LSI7 and LS] 8 can set their output terminals to a 0758-A32551TWFK2OI1O221) 1344152 _ Patent No. 96135125 Patent Revision Amendment April 19, 1995 Correction Replacement Page 'A given logic level, so that the sensing circuit 112" The driver in the sensor SAO~SAn and the programming circuit 114" is disabled. For example, the level adjuster LS17 is coupled to the read enable signal RE and the sensing circuit 112. Between the gates AG00 and AGOn, when the core power supply voltage VDD_CORE is not ready during power-on, the input terminals of the AND gates AG00~AGOn are all set to a predetermined logic level, so that the sensing circuit 112 "The sensors SA0~SAn will be banned." In order to avoid the erroneous read operation caused by the power supply start sequence. Similarly, the level adjuster LS18 is coupled between the burn enable signal PE and the burn circuit 114" and the gate AGIO~AGln for When the core power supply voltage VDD_CORE is not ready during power-on, the input terminals of the AND gates AG 10~AG 1 η are all set to a predetermined logic level, so that the programming circuit 114" is disabled, so as to avoid power supply. The initial sequence causes an incorrect programming operation. Conversely, when both the I/O power supply voltage VDD_IO and the core power supply voltage VDD_CORE are ready, the level adjusters LS16 to LS18 are used to externally program the voltage enable signal EPS_EN, The read enable signal RE and the burn enable signal PE are adjusted by a signal of the core power supply voltage level to a signal for inputting the output power supply voltage level to respectively control the sensing in the switching element 116 and the sensing circuit 112" The gates AG0~SAn and the gates AGIO~AGln (ie, drivers) in the programming circuit 114". It should be noted that the NMOS transistors T0~Τn in the electrically burnable memory cell 10" are thick gates. Device (I/O device) A set of level adjusters LS17 is needed to adjust the address (signal) 00 <0:11> in the sensing circuit 112" and the read enable signal RE. Similarly, a set of bits 0758-A32551TWFl is required. (20110221) 1344152 _ Patent Specification No. 96135125 Revision of the revised page alignment adjuster LS1 8 of April 19, 100 for adjusting the address (letter 'number) ADD<0:n> in the programming circuit 114" And burn the enable signal PE. The switching element 116 is coupled between the external programming voltage EPS and the resistor RP" to selectively disconnect the external programming voltage EPS from the power bus 111" according to the output of the level adjuster LS16. For example, the switching element Π 6 may be an active device such as a MOS transistor, a bipolar transistor (BJT), or a junction field effect transistor (JFET), but is not limited thereto. The level regulator LS16 is coupled between the external programming voltage enable signal EPS_EN and the control terminal of the switching element 116 for selectively disconnecting the external power supply voltage EPS from the electrically recordable unit 110". In this case, when the I/O power supply voltage VDD_IO and the core power supply voltage VDD_CORE are ready, the level adjuster LS16 is used to adjust the external programming voltage enable signal EPS_EN from the core power supply voltage level to Input and output power supply voltage level signals, in order to control the switching element 116 to connect the external programming voltage EPS to the electrically combable unit 110", to burn or sense (read) the electric burner unit 110" Conversely, when the core power supply voltage VDD_CORE is not ready during power-on, the level regulator LSI 6 sets the control terminal of the switching element 116 to a predetermined logic level, so that the switching element 116 is turned off, so The power bus bar 111" in the programmable unit 110" is disconnected from the external programming voltage EPS to avoid erroneous programming. For example, the level adjusters LS16 to LSI 8 can be coupled by AC. AC coupling, a control signal from an external circuit, by way of a patent specification of 0758-A3255ITWFl (20110221) 13 1344152 No. 96135125, the method of correcting the replacement page-resistive element discharge or a combination thereof on April 19, 100 The output is set to a predetermined logic level. The ESD protection circuit 117 is connected to the switching element 117 and the resistor RP" to avoid damage from the electrostatic discharge event. Figure 6 is an embodiment of a quasi-regulator. As shown, the level adjuster 21A generates an output according to an input signal IN_CORE, signals OUT_I0 and OUTB_IO, and the level adjuster 21A includes a first logic unit -6, a second logic unit 18, and two drivers. 23 and 25, and an inverter INV1. The first logic unit 16 is powered by the I/O supply voltage VDD_IO, while the second logic unit 18 is powered by the core_power supply voltage VDD_CORE. For example, the first logic unit 16 includes a latch unit 12 and a differential pair 14, and the second logic unit 18 includes an inverter INVO, wherein the latch unit 12 includes a cross-coupled PMOS transistor MPO. And MP1, and the differential pair 14 includes two NMOS transistors MNO and MN1. In some embodiments, the latch unit 12 can also include two cross-faced inverters. The inverter INVO powered by the core supply voltage VDD_CORE is used to convert the input signal IN_CORE into an inverted signal INB_CORE. In some embodiments, the transistors in the latch unit 12 are implemented by a thin gate device, while the other transistors in the level adjuster 21A are implemented by a thick gate device. If the input signal TN_CORE is high, the inverted signal INB_CORE will be low, so the NMOS transistors MNO and MN1 will be turned on and off, respectively. When the NMOS transistor MN0 is turned on, the gate of the PMOS transistor MP1 is pulled down to the ground voltage GND, at 0758-A32551TWF1 (20110221) 14 1344152 -- 'Patent Specification No. 96135125 Revised on April 19, 100 Correction Replacement Page 1 is that PMOS transistor MP1 will then turn on. Therefore, the input signals OUT_IO and QUTB_IO will be high and low, respectively. At this time, the nodes N1 and N2 can be regarded as outputs for outputting the output signals OUT_IO and OUTB_IO. The first driver 23 is coupled between the I/O power supply voltage VDD_IO and the node N1 for matching the voltage on the node N1 with the I/O power supply voltage VDD_IO when the core power supply voltage VDD_CORE is not ready. The second driver 25 is coupled between the node N2 and the ground voltage GND • to lower the voltage on the node N2 when the core power supply voltage VDD_CORE is not ready (or maintain the voltage on the node N2 at a low level). quasi). The first driver 23 is realized by the PMOS transistor MP2 and the NMOS transistors MN2 and MN3, and the second driver 25 is realized by the NMOS transistors MN4 and MN5. The PMOS transistor MP2 includes a drain and a source coupled to the I/O power supply voltage VDD_IO and a gate coupled to the node N1, that is, the PMOS transistor MP2 is connected as a capacitor. The NMOS transistor MN2 includes a drain coupled to the node N1, a gate coupled to the I/O supply voltage VDD-IO, and a source terminal. In some embodiments, the level adjuster 21A may include only the first driver 23 and not the second driver 25.

The NMOS transistor MN3 includes a source terminal connected to the NMOS transistor Μ N 2 and a gate terminal coupled to a source terminal GND to the ground voltage GND. The NMOS transistor ΜΝ4 includes a gate coupled to the node N2 and a 汲 terminal coupled to a ground terminal GND, i.e., the NMOS transistor MN4 is coupled to form a capacitor. NMOS 0758-A32551TWF1 (20110221) 15 1344152 _ Patent Specification No. 96135125 Revised on April 19, 2014 Revision Replacement Page 'Transistor MN5 includes one pole connected to node N2 and one gate terminal together with one source terminal It is coupled to the ground voltage GND. In other words, the NMOS transistors MN4 and MN5 can be shown as decoupling capacitors. Due to the parasitic capacitance Cgd and or Cgb, the voltage level on the node N1 will follow the I/O supply voltage VDD_I0, and due to the decoupling capacitor. (ie, NM0S transistors MN4 and MN5) The voltage level at node N2 will remain at a low level. Therefore, when the core power supply VDD_C0RE is not ready during power-on, the output signals OUT_IO and OUTB_I0 φ are set to the high and low levels, respectively. In other words, when the core power supply voltage VDD_C0RE is not ready during power-on, since the output of the level adjuster 21A can be set to a predetermined logic level, the level adjuster 21A can be used to achieve the level adjustment in FIG. LS16, LS17 and LS18. For example, when the core power supply voltage VDD_CORE is not ready during power-on, the level adjuster LS16 outputs an output signal 〇UTB_IO having a high level and/or an output signal having a low level, 0UT_I0 to the switching element 116. So that the electrically burnable recording unit 110" is disconnected from the external programming voltage EPS to avoid an unexpected or erroneous programming operation. Similarly, when the core power supply voltage VDD_CORE is ready during power-on, the level adjustment is performed. The LS17 outputs a low level output signal OUT_I0 to the AND gates AG00~AGOn in the sensing circuit 112", so that the sensors SA0~SAn in the sensing circuit 112" are disabled. During the process, the core power supply voltage is 0758-A32551TWFl (20110221). 16 1344152 Correction of the replacement page, page 96135125, revised on April 19, 2014. When the VDD-CORE is not ready, the level adjuster LS18 will output a low level output. The signal 丁U丁_1〇 to the sensing circuit 丨12, and the gate AGIO~AGln, so that the programming circuit 114” is disabled. In some embodiments, the first driver 23 can also include transistors MN2 and MN3, but does not include the PM〇s transistor Mp2. In some embodiments, the first driver 23 may also include a pm〇S transistor MP2, but does not include NMOS transistors MN2 and MN3. In some implementations, the second driver 25 can also include an NMOS transistor MK14, but does not include an NMOS transistor ΜΝ5. In some embodiments, the second driver 25 can also include an NMOS transistor ΜΝ5, but does not include an Nm 〇s transistor MN4. Figure 7A is an embodiment of a switching element. As shown, the switching element 116 includes a PM〇s transistor ρι coupled between the external programming voltage EPS and the resistor RP", and an NM 〇s transistor m coupled to the resistor RP" and the ground. Between the voltages GND, wherein the control terminals of the M?s transistors P1 and N1 are coupled to the wheel terminal of the level adjuster LS16. When the core power supply voltage Vdd_CORE is not ready and the output signal OUTB~1〇 is high logic level, the pM〇S transistor will be blocked and the NMOS transistor N1 will be turned on. Therefore, the external programming voltage EPS will be disconnected from the electrically combustible unit 11, the middle power supply bus m, will be disconnected, and will be discharged to the ground. In other words, during the power-on process, regardless of the external programming voltage EpS, the level adjuster LS16 outputs an output signal OUTB-1 to turn off the switching element 1-6. When the core power supply voltage VDD_CORE is not ready during power-on, the external 0758-A32551TWF) (20110221) 1344152 The revised specification of the replacement page No. 96135125 of April 19, 100, is disconnected, so the voltage can be avoided. The EPS and the electrical burnable unit 110" are free from unexpected or erroneous programming. When the core power supply voltage VDD_CORE and the I/O power supply voltage are ready, the LS16 will activate the signal according to the external programming voltage EPS_EN. The output-output signals OUTB_I0 and OUT_IO control the switching element 1 16. In other words, after the power supply is completed, the switching element 116 selectively connects the external programming voltage EPS according to the external programming voltage enable signal EPS_EN. For example, when the output signal 〇UTB_IO is low, the PMOS transistor Ρ1 φ will be turned on, and the NMOS transistor N1 will be turned off. Therefore, the external programming voltage EPS It will be connected to the power bus bar 111" of the electric burner unit 110" for the burning or sensing action of the electric burner unit Π 0". If the sensing circuit 112" does not require the output potential of the switching element 116 to be grounded when the PMOS transistor P1 is in the off state, the NMOS transistor N1 is not an essential component. That is, in some embodiments, implementation is not required. The NMOS transistor N1 can be satisfied only by implementing the PMOS transistor P1. Lu 7B is another embodiment of the switching element. As shown, the switching element 116" is connected to the switch shown in Fig. 7A. The component 116 is similar, the difference is that the NMOS transistor N2 is coupled between the external programming voltage EPS and the resistor RP". When the core power supply voltage VDD_CORE is not ready when the power is turned on, if the output signals OUTB_IO and OUT The PMOS transistor P1 and the NMOS transistor N2 are loaded, and the NMOS transistor N1 0758-A32551 TWF1 (20110221) 18 1344152 __ Patent Specification No. 96135125 The correction replacement page will be turned on on April 19, 100. Therefore, the external programming voltage EPS will be disconnected from the power busbar 111'' of the electrically recordable unit ΠΟ"' and discharged to the ground. When the core power supply voltage VDD_CORE is not ready during power-on, the external programming voltage EPS will be disconnected from the electrical burn-in unit 1 0", thus avoiding unpredicted or erroneous burning operations. When the PMOS transistor P1 and the NMOS transistor N2 are in the off state, the sensing circuit 112" does not require the output potential of the switching element Π6 to be grounded, and the NMOS transistor N1 is not an essential element. That is, in some embodiments, it is not necessary to implement the NMOS transistor N1, but only the PMOS transistor P1 and the NMOS transistor N2 need to be implemented. Figure 8 is a simulation result of the memory circuit in Figure 5. As shown in the figure, since the core power supply voltage VDD_CORE is not ready during power-on, the output signal 〇UTB_IO will follow the I/O power supply voltage VDD-IO to disconnect the external programming voltage EPS from the power busbar 111. On, so before the core power supply voltage VDD_CORE is ready, the voltage level on the power bus bar 111" in the electrical burn-in unit 110" is maintained at a low level, so that unexpected or erroneous programming can be avoided. Fig. 9 is another embodiment of the level adjuster. As shown, the level adjuster 21B is similar to the level adjuster 21A shown in Fig. 6, with the difference that the first driver is removed. 23 and the second driver 25 is implemented by a switching element 60. In some embodiments, the transistor in the inverter INV0 is implemented by a thin gate device, while the other transistors in the level adjuster 21B The method is implemented by a thick gate device. The switching element 60 is coupled between the node N2 and the ground voltage GND, and is subjected to a

S 0758-A32551TWF1 (20110221) 19 1344152 _ Patent Specification No. 96135125 Revision of the revised page of April 19, 100. Control of an external power supply start reset circuit 70. When the core power supply voltage VDD_CORE is not ready during power-on, the external power supply start reset circuit 70 generates a control signal SR to control the switching element 60 such that the voltage level at the node N2 is pulled low. When the bit on node N2 is pulled low by switching element 60, PMOS transistor ΜΡ0 turns on, and node N1 is also pulled high to I/O supply voltage VDD_IO. In other words, when the core power supply voltage VDD_CORE is not ready, the output signals ◦UTB_IO and OUT_IO are set to the high level and the low level, respectively. When the core power supply voltage VDD_CORE is ready, the power supply restarting circuit 70 will load the switching element 60 by the control signal SR, so that the inverter INV0 using the core power supply voltage VDD_CORE will generate an inverted signal and take The control right of the level adjuster 21B is returned. In some embodiments, switching element 60 can be implemented by an active element, such as a MOS transistor, a bipolar transistor, a junction field effect transistor, or a combination thereof. Figure 10 is another embodiment of a level adjuster. As shown, the level adjuster 21C is similar to the level adjuster 21A shown in Fig. 6, with the difference that the second driver 25 is realized by the switching element 60. In some embodiments, the transistors in inverter INV0 are implemented by thin gate devices, while the other transistors in level adjuster 21C are implemented by thick gate devices. When the core power supply voltage VDD_CORE is not ready during power-on, the voltage level on node N1 will follow due to the AC coupling caused by the parasitic capacitance Cgd or Cbg of MOS transistor MP2, MN2 or MN3. The I/O power supply voltage VDDJO, and the voltage level on the node N2 will be destroyed by the switching element 60 0758-A32551TWF1 (20110221) 20 1344152 - Patent specification No. 96135125 revised this April 19th revised replacement page

Pull down to ground. In other words, when the core power supply voltage VDD_CORE is not ready during power-on, the output signals OUTB_IO and OUT_IO are set to the high and low levels, respectively. When the core power supply voltage VDD_CORE is ready, the external power supply start reset circuit 70 will turn off the switching element 60 by the control signal SR, so that the inverter INV0 using the core power supply voltage VDD_CORE will be inverted. The signal is retrieved and the control of the level adjuster 21C is retrieved. The second diagram is another embodiment of a level adjuster. As shown, the reference level adjuster 21D is similar to the level adjuster 21A shown in FIG. 6, with the difference that the second driver 25 is implemented by a resistive element 62 for slowly pulling The voltage level on the low node N 2 . When the core power supply voltage VDD__CORE is not ready during power-on, the voltage level on node N1 will follow due to the AC coupling caused by the parasitic capacitance Cgd or Cbg of MOS transistor MP2, MN2 or MN3. The I/O supply voltage VDD_IO, and the voltage level on node N2 is slowly pulled low by the resistive element 62. In other words, when the core power supply voltage VDD__CORE is not ready during power-on, the output signals OUTB_IO and OUT_IO are set to the high and low levels, respectively. For example, if the resistive element 62 has sufficient resistance, it will be considered a high impedance when the core supply voltage VDD-CORE is ready. Therefore, when the core power supply voltage VDD_CORE is ready, the inverter INV0 using the core power supply voltage VDD_CORE generates an inverted signal and retrieves control of the level adjuster 21D. Figure 12A is an embodiment of a resistive element. As shown in the figure, 0758-A3255]TWFl(20110221) 1344152 _ No. 135125 patent specification amendment inn # e R m ^ April 19, 100 revised replacement page resistive element 62A is lightly connected to node N2 and The ground voltage GND is between the ground and includes N series connected pm 〇 transistors MPA1 〜 MPAN, and one NMOS transistor MNB is coupled between the ground voltages of the PMOS transistors MPAN. Each of the pm〇s transistors MPA1~MPAN is connected in the form of a diode, that is, the gate is coupled to its source. When the core power supply voltage VDD_CORE is not damaged during power-on, the NMOS transistor MNB turns on, causing the voltage level at node N2 to be slowly pulled low. Therefore, when the I/O power supply voltage VDD_I〇 is earlier than the core power supply voltage VDD_CORE, the output signal OUTB-10 is pulled high by the first driver 23, and the output signal OUTJ0 is slowly pulled by the resistive element 62A. low. Figure 12B is another embodiment of a resistive element. As shown, the resistive element 62B is similar to the resistive element 62A shown in FIG. 12A. The difference is that the PMOS transistors MPA1 to MPAN are replaced by bi-carrier transistors (BJTs) BTAl to BTAN. The action of the element 62 is similar to the resistive element 62A shown in Fig. 12A and will not be described again. The Brother 12 C diagram is another embodiment of a resistive element. As shown in Fig., the resistive element 62C is similar to the resistive element 62A shown in Fig. 12A, and the difference is that the PMOS transistors MPA1 to MPAN are replaced by NMOS transistors MNA1 to MNAN, each NMOS transistor. MNA1~MNAN are all connected in the form of a diode, that is, the gate is coupled to the drain. The operation of the resistive element 62C is similar to that of the resistive element 62A shown in Fig. 12A and will not be described again. 0758-A32551TWFl (20110221) 22 1344152 Patent Specification Revision No. 96135125 This is a further embodiment of a resistive element. As shown in the figure, the resistive element 62C is similar to the resistive element shown in the figure. The difference is that the NM〇s transistor m-system is depleted in the p-electrode MPAO and MPA1~MpAN. The f-action is similar to the resistive element shown in the figure. 1 = No longer described. It seems that this is implemented in a certain place, and the level adjuster is removed. For example, when the electrically programmable unit I: system is implemented by thin-film, the sensing circuit; "丨14 only needs the core power supply voltage VDD CORE, the whole device LS17 can be removed. Or, say, when In the realization of the day f = nG", the 05-electrode system is composed of the thick gate device S and the circuit 12] and the programming circuit 114, and the level adjusters 21B ... 10 and 11 are shown in the figure. Level adjuster 21A,

Burning the thunder /? 1D to 'now. In other words, the leveling regulators in the sensing circuit 12, and the map: _ 14 can be implemented by the level adjusters 21Α, 21β, 2ic of the sixth, ninth, and ninth, "Excluding the switching element 116 and the level adjuster (4). The power supply (10) body f path can be used to avoid the external programming voltage and the electrically combustable unit when the core is in the process of 1 source startup. Unexpected or erroneous burning operation caused by the sequence of operations. Although the invention has been described in its preferred embodiment to limit the invention to any of the well-known skilled artisan, the invention is not deviated from the present invention = 0758-A3255fTWFl (2〇H〇22I 23 Patent Specification No. 96335125 amends the scope of this God and the scope, when the scope of the -___________ protection is attached to the movement and retouching, therefore the scope of the patent of the invention is 7

The scope is defined. [Simple description of the diagram] The following is an example of a memory circuit. The :2 diagram is an embodiment of the sensing circuit. : 3 is a recording circuit - an embodiment. Figure 4 is the first! The memory in the figure is shown in Fig. 5. A 々 立 触 而 岭 岭 岭 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕. The figure 6 is an embodiment of a level adjuster. Figure 7 is an embodiment of a switching element. The seventh diagram is another embodiment of the switching element. The f8 diagram is the simulation result of the memory circuit in Fig. 5: Fig. 9 is another embodiment of the level adjuster. Figure 10 is another embodiment of a level adjuster. Figure 11 is an alternative embodiment of a level adjuster. Figure 12A is an embodiment of a resistive element. The second diagram is an alternative embodiment of a resistive element. Figure 12C is an alternative embodiment of a resistive element. Figure 12D is an alternative embodiment of a resistive element. [Main component symbol description] 12: latch unit; I differential pair; 16, 18: logic unit; 23, 25: driver; 62, 62A to 62D: resistive element;

24 07 58-Λ325 51T W1 (20110221) S 1344152 - 'Patent Specification No. 96135125 Revised 100 April 19曰 Correction Replacement Page 70: Power Start Reset Circuit; 100, 100": Memory Circuit; 110 , 110": electric burnable unit; • Π 1, 111 '': power bus; 112, 1 12": sensing circuit; 114, 114": programming circuit; 116, 60 · switching element, 118. Electrostatic discharge protection circuit, 120: power supply unit; RP, RP": resistance;

RfO, Rfl~Rfn: fuse; INV0~INV1: inverter; • SA0~SAn: sensor; AG00~AGOn, AGIO~AGln: and gate;

Cgd, Cgb: parasitic capacitance; PE: programming enable signal; RE: read enable signal; EPS_EN: external programming voltage enable signal; VDD_CORE: core supply voltage; VDD-10: input/output (I/O Power supply voltage; IN_CORE: input signal; • OUT_IO, OUTB_IO: output signal; INB_CORE: inverted signal; GND: ground voltage;

Nl, N2: node; SR: control signal; VBUS: voltage level; LS12, LS14, LS16, LS17, LS18, 21A~21D: level adjuster; TO, T1~Tn, Ph Ν1~Ν2, ΜΡ0~ΜΡ2 , ΜΝ0~ΜΝ5, MPA1~MPAN, MNB, MTA1~MTAN, BTB,

S 0758-A32551TWFl (20110221) 1344152 Patent Specification Revision No. 96135125 Revision No. M191 to MNAN: Transistor.

0758-A32551TWFl(20J10221) 26

Claims (1)

1344152 --- • Patent Specification No. 96135125 Revised on April 19, 2011 Revision Correction Page • ' X. Patent Application Range: - 1. A memory circuit comprising: a programmable unit, The method includes: a plurality of combinable components; and a power bus bar coupled between an external programming voltage and the flammable component; a switching component coupled to the external programming voltage and the power bus The switching element includes a control terminal; and a φ level shifter is configured to adjust a voltage level of the coincidence signal from a second power voltage to a first power voltage, wherein the second The power supply voltage is lower than the external programming voltage, and when the second power supply voltage is not ready during power-on, the level adjuster sets the control end of the switching element to a predetermined logic level. So that the above switching element is turned off, and the above power busbar is disconnected from the above external programming voltage to avoid erroneous burning (false program The memory circuit of claim 1, wherein the flammable elements each comprise a dissolved wire. 3. The memory circuit of claim 1, wherein the memory circuit is a nonvolatile memory. 4. The memory circuit according to claim 1 The memory circuit is an electronic programmable memory (〇0758-A32551TWF1 (2011022)) 27 L52 100 years 4th 9th revised replacement page 96135丨25 patent specification amendment The memory circuit of the first aspect of the invention, wherein the flashable memory unit is a flash memory. , the memory circuit described in the "Patent Enclosure" item, wherein the power supply voltage of the system is higher than the external programming voltage. :,: The memory circuit described in the i-th patent scope, wherein ―When the second power supply voltage is ready, the leveling device adjusts the voltage level of the enable signal from the second power 4: to the first power supply voltage. 4、如申% The memory circuit of the first aspect of the invention, wherein the second power supply voltage is not ready in the power source startup (four) ready), wherein the level regulator adjusts the switching element by AC ac (10) The control terminal is set at the above-mentioned predetermined logic level. 9· The memory circuit described in the Japanese Patent Application No. 7, wherein the above-mentioned level regulator is not ready when the power source is started. The control circuit of the switching element is set to the predetermined logic level according to a control signal from the external circuit. 10. The memory circuit according to claim 7, wherein the power supply is activated. When the power supply voltage is not ready, the above-mentioned level adjuster sets the control end of the above-mentioned switching element to the above-mentioned predetermined logic level by means of AC M (AC _pling) and control No. 4 from an external circuit. π. The memory circuit includes: a power supply unit for providing an external programming voltage; and a programmable unit coupled to the power supply unit, including: S 0758-A32551TWF1 (20110221) 1344152 The patent specification of No. 96135125 and the power source of the above-mentioned programming and the first plurality of flammable components are coupled to a power busbar and coupled to the external programming voltage; and a programming circuit The circuit for burning the above-mentioned flammable component includes a plurality of drivers coupled to the flammable component. The two-level regulator is powered by at least a “first power supply”, and a power supply voltage of the upper middle is lower than the external one. In the middle of the process, the first _:===! The power-on device is set to the output of the right---the position adjustment driver is crying ~ Λ "After the level" makes the above mouth "is not (dlsab〗 ed) 'In order to avoid erroneous burning. Included in the memory circuit described in Item 11 of the patent, including: circuit - for sensing the above two sensing circuits including complex sensing transfer to In the above-mentioned second-level quasi-m power supply startup, the above-mentioned -1st-second and second-in-fourth (four) are provided with an output terminal: the above-mentioned sensing circuit is included in the above-mentioned sensing circuit:]3. The memory circuit described in item 12 is more confluent. Γ 十 'connected to the above external programming power and the above power supply t 'the above-mentioned open I-piece includes - control terminal; and the second two-level regulator, with the source voltage has not been prepared for I shi, knee μ, +, power start The first electric % ^ is only; the control end of the 圯 switching element is set at a first 一 one 疋 logic level, and the 电压 recording voltage is broken, and the above-mentioned pen source bus is disconnected from the external sinter 'In order to avoid erroneous burning. 虼29 〇758-A32551TWF|(2〇11〇22I) Patent Specification No. 96135125 modifies the memory circuit described in item 13 of the above From the mortal parts including - fuse and a singer S sing ^ connect the above electric (four) flow line and - ground voltage / _ 'series voltage and - _:, the second level adjuster is from the above - the first power supply Le-% source voltage is supplied, i medium voltage system is higher than the above external 焯a, and when the above-mentioned first--supply voltage is ready, the upper second and the second power supply are enabled-enable signals 4;: 2, the third level regulator is used to describe the second power voltage. The above-mentioned first power supply voltage The erroneous memory circuit of the whole 16-memory memory circuit includes a plurality of red-burnable parts, and the upper-and-high-circuit circuit includes a fault protection method including: W and - sensing pressure = setting 1 component in the above The programming component and the external programming device are coupled to one of the switching elements 2.11⁄4, wherein the first level regulator is composed of a first and a first: a power supply voltage Powered by, the second power voltage is lower than the first voltage; and the first power voltage is higher than the external programming power. When the second power source (four) is not ready during the power source startup process, the component is The control terminal is disposed at the -first logic level such that the late switching element is worn, and the power bus bar is disconnected from the external programming voltage. 〃 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The method further includes: setting a second level adjuster between the plurality of drivers of the programming circuit and a programming enable signal; and - when the second power voltage is not ready during power startup, The output of the two-position regulator is set at a second predetermined logic level, so that the above-mentioned driver in the above-mentioned programming circuit is disabled. 18. The method for protecting a memory circuit as described in claim 17 further includes: setting a third level adjuster to the plurality of sensors and a read enable signal of the sensing circuit And setting the output end of the third level adjuster to a third predetermined logic level when the second power supply voltage is not ready during power startup, so that the sensor in the sensing circuit is Will be banned. 19. The method for protecting a memory circuit according to claim 18, wherein the first, second, and third level adjusters are controlled by an AC coupling or from an external circuit. The output end is set to the first, second, and third predetermined logic levels. S 0758-A32551TWF1 (20110221) 1344152 _ __ Patent Specification Revision No. 96135125 Revision of the revised page on April 19, 100 'VII. Designation of representative drawings: a) The representative representative of the case is: Figure 5. b) A brief description of the component symbols of this representative diagram: electrical burn-in unit; sensing circuit; switching component; 100": memory circuit; 110' 111": power bus; 112' I 14": programming circuit; 116 II 8 : Electrostatic discharge protection circuit; Resistance; Burning enable signal; 120: Power supply unit; RP” RfO, Rfl~Rfn: fuse; PE: RE: read enable signal; EPS EN: external programming voltage enable signal; LS16, LS17, LS18: level adjuster; TO, T1~Τη: transistor. 8. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention: 0758-A32551TWFl(201l022l) 5