CN101149975A - Memory circuit and its error action protecting method - Google Patents
Memory circuit and its error action protecting method Download PDFInfo
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- CN101149975A CN101149975A CNA2007101535460A CN200710153546A CN101149975A CN 101149975 A CN101149975 A CN 101149975A CN A2007101535460 A CNA2007101535460 A CN A2007101535460A CN 200710153546 A CN200710153546 A CN 200710153546A CN 101149975 A CN101149975 A CN 101149975A
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Abstract
The invention relates to a memory electric circuit, which includes one capable burning unit including complex capable burning elements; one power supply bus coupling with the interval of one external burning voltage and capable burning element; one switching element connecting to the interval of the external burning voltage and the power supply bus; and one quasi regulator used for regulating one voltage position quasi from one second power supply voltage to one first power supply voltage, wherein, when the second power supply voltage is lower than the external burning voltage and not prepared well in the procedure of the power supply starting, the control terminal of the switching element is disposed on one fixed logical position quasi by the quasi regulator to cut off the switching element and disconnect the power bus and the external burning voltage to avoid fault burning.
Description
Technical field
The present invention is relevant for a kind of memory circuitry, and relevant especially a kind of memory circuitry can be avoided because the wrong burning (false programming) that power supply startup sequence (power-up sequence) causes.
Background technology
Fuse element is used in the semiconductor device widely, in order to record chip number or sequence number.Generally speaking, for other element in fuse element and the semiconductor device is disconnected, each fuse element all can comprise a fuse that can be blown (promptly opening circuit).For example, fuse can shine up to it by laser and be opened circuit, perhaps by the excess current that can distribute enough temperatures with its fusing.Fuse opened circuit and use laser different by excess current, itself in addition can after semiconductor device is packed, just carry out, be commonly referred to as electric burning (or electric sequencing; Electrically programming) fuse.In addition, allow that the fuse of this burning mode is called electric writable fuse or electric programmable fuse, or abbreviate e-fuse as, and most fuse can only be by burning once, in order to the state 0 and state 1 corresponding to high low impedance state to be provided, anti-person is also anti-.
Summary of the invention
The invention provides a kind of memory circuitry, comprise a writable unit (programmable unit), the accurate adjuster of an on-off element and position.Writable unit comprises plural burning elements; And a power bus, be coupled between external burning voltage and the burning elements; One on-off element is connected between external burning voltage and the power bus; An and accurate adjuster (level shifter), in order to an activation voltage of signals position standard is adjusted to one first supply voltage by a second source voltage, wherein second source voltage is lower than external burning voltage, and when second source voltage in the power initiation process is not ready for (not ready) as yet, the accurate adjuster in position is arranged at a set logic level with the control end of on-off element, make on-off element be cut off, and power bus can disconnect with external burning voltage, so that avoid wrong burning (falseprogramming).
The present invention also provides a kind of memory circuitry, comprises a power-supply unit, in order to an external burning voltage to be provided; And a writable unit, comprise plural burning elements, be coupled to a power bus; And a burning circuit, in order to the burning burning elements, and the burning circuit comprises that plural driver is coupled to burning elements, and one first accurate adjuster is powered by at least one first supply voltage.First supply voltage is lower than external burning voltage, when first supply voltage is not ready for as yet in the power initiation process, first accurate adjuster is arranged at one first set logic level with its output terminal, makes that the driver in the burning circuit can be by forbidden energy (disabled), so that avoid wrong burning.
The present invention also provides a kind of error action protecting method of memory circuitry, wherein memory circuitry comprises plural burning elements, a burning circuit and a sensing circuit (sensing circuit), and error action protecting method comprises and an on-off element is set between burning elements and an external burning voltage; One first accurate adjuster is set in order to be coupled to a control end of on-off element; And when second source voltage is not ready for as yet in the power initiation process, the control end of on-off element is arranged at one first logic level, make on-off element be cut off, and power bus can disconnect with external burning voltage.
The present invention also provides a kind of error action protecting method, and it comprises when a core voltage is not ready for as yet, cuts off the external burning voltage from burning elements.And when above-mentioned core voltage is ready for, according to the binding between activation signal controlling said external burning voltage and above-mentioned burning elements.
Description of drawings
Fig. 1 is an embodiment of a memory circuitry.
Fig. 2 is an embodiment of a sensing circuit.
Fig. 3 is an embodiment of a burning circuit.
Fig. 4 is the analog result of memory circuitry among Fig. 1
Fig. 5 is another embodiment of a memory circuitry.
Fig. 6 is an embodiment of an accurate adjuster.
Fig. 7 A is an embodiment of on-off element.
Fig. 7 B is another embodiment of on-off element.
Fig. 8 is the analog result of memory circuitry among Fig. 5.
Fig. 9 is another embodiment of the accurate adjuster in position.
Figure 10 is another embodiment of the accurate adjuster in position.
Figure 11 is another embodiment of the accurate adjuster in position.
Figure 12 A is an embodiment of resistance element.
Figure 12 B is another embodiment of resistance element.
Figure 12 C is another embodiment of resistance element.
Figure 12 D is another embodiment of resistance element.
Drawing reference numeral:
12: the bolt-lock unit; 14: differential right;
16,18: logical block; 23,25: driver;
62,62A～62D: resistance element;
70: power-on reset circuits;
100,100 ": memory circuitry;
110,110 ": electric writable unit;
111,111 ": power bus;
112,112 ": sensing circuit;
114,114 ": the burning circuit;
116,60: on-off element;
118: ESD protection circuit;
120: power-supply unit;
RP, RP ": resistance;
Rf0, Rf1～Rfn: fuse;
INV0～INV1: phase inverter;
SA0～SAn: sensor;
AG00～AG0n, AG10～AG1n: with door;
Cgd, Cgb: stray capacitance;
PE: burning enable signal;
RE: read enable signal;
EPS_EN: external burning voltage enable signal;
VDD_CORE: core power supply voltage;
VDD_IO: I/O (I/O) supply voltage;
IN_CORE: input signal;
OUT_IO, OUTB_IO: output signal;
INB_CORE: inversion signal;
GND: ground voltage;
N1, N2: node;
SR: control signal;
VBUS: voltage level;
LS12, LS14, LS16, LS17, LS18,21A～21D: the accurate adjuster in position;
T0, T1～Tn, P1, N1～N2, MP0～MP2, MN0～MN5, MPA1～MPAN, MNB, MTA1～MTAN, BTB, MNA1～MNAN: transistor.
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Fig. 1 is an embodiment of a memory circuitry.As shown in the figure, memory circuitry 100 comprises an electric writable unit 110 (for example e-fuse bank), a sensing circuit 112 and a burning circuit 114.The writable unit 110 of electricity comprises plural fuse element, and each fuse element to have in order to the fuse that is blown (be Rf0, Rf1～Rfn) and in order to (being T0, T1～Tn) as the nmos pass transistor of current source.Fuse Rf0～Rfn can be the brilliant resistance of covering of self-aligned silicide (salicide polysilicon resistor), and MOS transistor T0～Tn can be thin gate devices (thin gate device) or thick gate devices (thick gatedevice).Also be coupled to sensing circuit 112 with reference to fuse Rref, in order to difference fuse that does not blow and the fuse that blows.Sensing circuit 112 is by desiring the address AD D＜0:n of sensing〉and one read enable signal RE, start the action of reading and the data DATA＜0:n after the output relatively 〉.
Fig. 2 is an embodiment of a sensing circuit.As shown in the figure, sensing circuit 112 comprises the accurate adjuster in a plurality of positions (general designation LS12), plural number and door AG00～AG0n and plural sensor SA0～SAn.The accurate adjuster LS12 in position is coupled to a core power supply voltage VDD_CORE and an I/O (I/O) supply voltage VDD_IO, in order to the address AD D＜0:n that will desire sensing〉and read enable signal RE, be adjusted to the signal of I/O supply voltage position standard by the signal of core power supply voltage position standard.Sensor SA0～SAn respectively is coupled to the fuse of a correspondence and with reference to fuse Rref, and with door AG00～AG0n in order to according to address ADD＜0:n, drive sensor SA0～San, use the data after the output relatively.
Fig. 3 is an embodiment of a burning circuit.As shown in the figure, burning circuit 114 comprises the accurate adjuster in a plurality of positions (general designation LS14) and plural number and door AG10～AG1n.The accurate adjuster LS14 in position is coupled to a core power supply voltage VDD_CORE and an I/O (I/O) supply voltage VDD_IO, in order to the address AD D＜0:n that will desire burning〉and burning enable signal PE, be adjusted to the signal of I/O supply voltage position standard by the signal of core power supply voltage position standard.Each with door AG10～AG1n as a driver, and connect the fuse of a correspondence and with reference to fuse Rref.When receiving the burning enable signal PE of the accurate adjuster LS14 of self-alignment, with door AG10～AG1n according to address ADD＜0:n with fuse opening.
Yet, if use the feed regulator isolator (regulator) of serial connection, with the power supply startup sequence that probably produces as shown in Figure 4.For example, I/O supply voltage VDD_IO (for example 3.3V) is ahead of external burning voltage EPS (for example 2.5V) and core power supply voltage VDD_CORE (for example 1.0V).Therefore, when I/O supply voltage VDD_IO is ready for (ready), core power supply voltage VDD_CORE still is invalid (not being ready for as yet), and this moment, external burning voltage EPS can be any value, makes in period T 1 electric writable unit 110 be in the state an of the unknown.This situation may cause inexpectancy or wrong burning action.
In some embodiment, and the nmos pass transistor in the writable unit 110 (be T0～Tn) realized by thin gate devices, thus sensing circuit 112 and 114 needs core power supply voltages of burning circuit VDD_CORE, so its accurate adjuster all can slightly remove.Yet, the power supply that these embodiment still need to keep external burning voltage EPS and core power supply voltage VDD_CORE opens the beginning order, make that core power supply voltage VDD_CORE must be than more Zao be ready for (ready) of external burning voltage EPS, to avoid the action of inexpectancy or wrong burning.
For fear of these situations, the present invention also provides the embodiment of the memory circuitry of some actions that can avoid inexpectancy or wrong burning.
Fig. 5 is another embodiment of a memory circuitry.As shown in the figure, memory circuitry 100 " comprise an electric writable unit 110 ", a sensing circuit 112 ", a burning circuit 114 ", an on-off element 116, accurate adjuster LS16, an Electrostatic Discharge holding circuit 118, a power-supply unit 120 and a resistance R P ".For example, memory circuitry 100 " can be nonvolatile memory (nonvolatilememoty), electric writable storer (electrical programmable memory), a burning ROM (read-only memory) (once time programmable read only memory; But be not limited to this OTP ROM).Power-supply unit 120 is in order to provide external burning voltage EPS (for example a fuse power supply or a supply voltage) to electric writable unit 110 ".
The writable unit 110 of electricity " comprise that plural fuse element, each fuse element comprise one in order to the fuse that is blown (Rf0, Rf1～Rfn) and nmos pass transistor as current source (for example T0, T1～Tn) for example.For example, fuse Rf0～Rfn can be the brilliant resistance of covering of self-aligned silicide (salicidepolysilicon resistor), and MOS transistor T0～Tn can be thin gate devices (thin gate device) or thick gate devices (thick gate device).Also be coupled to sensing circuit 112 with reference to fuse Rref ", in order to the fuse that do not blow of difference and the fuse that blows, and fuse Rf0～Rfn and Rref see through a power bus 111 " and resistance R P " be connected to an external burning voltage EPS.The writable unit 110 of electricity " can be a non-volatile and electric writable unit, for example e-fuse bank, flash memory, a burning type mnemon, but be not limited to this.
For example, the accurate adjuster LS17 in position is coupled to and reads enable signal RE and sensing circuit 112 " and door AG00～AG0n between; in order to when core power supply voltage VDD_CORE is not ready for as yet in the power initiation process; will all be set to a set logic level; make sensing circuit 112 with the input end of door AG00～AG0n " sensor SA0～SAn all can be by forbidden energy so that avoid power supply to open the action of reading that the beginning leads to errors in proper order.Similarly, the accurate adjuster LS18 in position is coupled to burning enable signal PE and burning circuit 114 " and door AG10～AG1n between; in order to when core power supply voltage VDD_CORE is not ready for as yet in the power initiation process; will all be set to a set logic level; make burning circuit 114 with the input end of door AG10～AG1n " understand by forbidden energy move so that avoid power supply to open the burning that the beginning leads to errors in proper order.
Anti-speech, when I/O supply voltage VDD_IO and core power supply voltage VDD_CORE all are ready for, the accurate adjuster LS16～LS18 in position in order to external burning voltage enable signal EPS_EN, read enable signal RE and burning enable signal PE and be adjusted to the signal of input and output supply voltage position standard, so that gauge tap element 116, sensing circuit 112 respectively by the signal of core power supply voltage position standard " in sensor SA0～SAn and burning circuit 114 " in door AG10～AG1n (being driver).
Be noted that, when the writable unit 110 of electricity " in nmos pass transistor T0～Tn when being realized by thick gate devices (I/O device); then need one group of accurate adjuster LS17 in position, in order to adjust sensing circuit 112 " in address (signal) ADD＜0:n with read enable signal RE.Similarly, need one group of accurate adjuster LS18 in position, in order to adjust burning circuit 114 " middle address (signal) ADD＜0:n〉and burning enable signal PE.
On-off element 116 is coupled to external burning voltage EPS and resistance R P " between, in order to output, optionally with external burning voltage EPS and power bus 111 according to the accurate adjuster LS16 in position " disconnect.For example, on-off element 116 can be active member, for example MOS transistor, two-carrier transistor (BJT), connect the face field and imitate transistor npn npn (JFET), but be not limited to this.
The accurate adjuster LS16 in position is coupled between the control end of external burning voltage enable signal EPS_EN and on-off element 116, in order to optionally with outer power voltage EPS and electric writable unit 110 " disconnection.For example, when I/O supply voltage VDD_IO and core power supply voltage VDD_CORE all are ready for (ready), the accurate adjuster LS16 in position is in order to be adjusted to external burning voltage enable signal EPS_EN the signal of input and output supply voltage position standard by the signal of core power supply voltage position standard, so that gauge tap element 116 connects external burning voltage EPS to electric writable unit 110 ", with to the writable unit 110 of electricity " carry out burning or sensing (reading).Anti-speech, when core power supply voltage VDD_CORE is not ready for as yet in the power initiation process, the accurate adjuster LS16 in position can be arranged to the control end of on-off element 116 a set logic level, make on-off element 116 to end, so electric writable unit 110 " in power bus 111 " can and external burning voltage EPS disconnect, use the burning action of avoiding wrong.
For example, the accurate adjuster LS16～LS18 in position can be by AC coupling (AC coupling), from a control signal of an external circuit, discharge or the mode of its combination comes its output terminal to be arranged at a set logic level by a resistance element.ESD protection circuit 118 connects on-off element 116 and resistance R P ", in order to avoid the infringement of electrostatic discharge event.
Fig. 6 is an embodiment of an accurate adjuster.As shown in the figure, the accurate adjuster 21A in position is according to an input signal IN_CORE, produce output signal OUT_IO and OUTB_IO, and the accurate adjuster 21A in position comprises one first logical block 16, one second logical block 18, two drivers 23 and 25, and a phase inverter INV1.First logical block 16 is powered by I/O supply voltage VDD_IO, and second logical block 18 is powered by core power supply voltage VDD_CORE.For example, first logical block 16 comprises a bolt-lock unit 12 and differential to 14, and second logical block 18 comprises a phase inverter INV0, and wherein bolt-lock unit 12 comprises cross-coupled to PMOS transistor MP0 and MP1, and differentially comprises two nmos pass transistor MN0 and MN1 to 14.In some embodiment, bolt-lock unit 12 also can comprise that two cross-coupled are to phase inverter.By the phase inverter INV0 of core power supply voltage VDD_CORE power supply in order to input signal IN_CORE is converted to an inversion signal INB_CORE.In certain embodiments, the transistor in the bolt-lock unit 12 is implemented by thin gate devices, and the transistor among the accurate adjuster 21A in position is implemented by thick gate devices.
If when input signal IN_CORE was high levels, inversion signal INB_CORE can be low level, so nmos pass transistor MN0 and MN1 can be respectively conducting and end.When nmos pass transistor MN0 conducting, the grid of PMOS transistor MP1 can be pulled low to ground voltage GND, so PMOS transistor MP1 can follow conducting.Therefore, input signal OUT_IO and OUTB_IO can be respectively high levels and low level.At this moment, node N1 and N2 can be considered the output terminal in order to output signal output OUT_IO and OUTB_IO.
PMOS transistor MP2 comprises that drain electrode and source electrode are coupled to I/O supply voltage VDD_IO and a grid is coupled to node N1, and meaning is that PMOS transistor MP2 connects into a capacitor.Nmos pass transistor MN2 comprises that a drain electrode is coupled to node N1, a grid is coupled to I/O supply voltage VDD_IO, and the one source pole end.In certain embodiments, the accurate adjuster 21A in position can only comprise first driver 23 and not comprise second driver 25.
Nmos pass transistor MN3 comprises that a source terminal and a gate terminal that a drain electrode end is coupled to nmos pass transistor MN2 are coupled to ground voltage GND with the one source pole end.Nmos pass transistor MN4 comprises that a grid is coupled to node N2 and a drain electrode end is coupled to ground voltage GND with the one source pole end, and promptly nmos pass transistor MN4 connects into a capacitor.Nmos pass transistor MN5 comprises that a drain electrode end is coupled to node N2 and a gate terminal is coupled to ground voltage GND with the one source pole end.In other words, nmos pass transistor MN4 and MN5 can be shown decoupling capacitance device (decouplingcapacitors).
Because stray capacitance Cgd and/or Cgb, the voltage level on the node N1 can followed I/O supply voltage VDD_IO, simultaneously because the voltage level on decoupling capacitance (being nmos pass transistor MN4 and MN5) the node N2 can maintain low level.Therefore, when core power supply voltage VDD_CORE was not ready in the power initiation process, output signal OUT_IO and OUTB_IO can be set at high levels and low level respectively.In other words, when core power supply voltage VDD_CORE is not ready in the power initiation process, because the output terminal of the accurate adjuster 21A in position can be set at set logic level, therefore the accurate adjuster 21A in position can be in order to realize position accurate adjuster LS16, LS17 and the LS18 among Fig. 5.
For example, when core power supply voltage VDD_CORE is not ready in the power initiation process, the accurate adjuster LS16 in position can export the output signal OUTB_IO and/or with high levels and have the output signal OUT_IO of low level to on-off element 116, make electric writable unit 110 " disconnect with external burning voltage EPS, use the burning action of avoiding unexpected or wrong.Similarly, when core power supply voltage VDD_CORE is not ready in the power initiation process, the accurate adjuster LS17 in position can export have low level output signal OUT_IO to sensing circuit 112 " in door AG00～AG0n, make sensing circuit 112 " in sensor SA0～SAn can be by forbidden energy.Moreover, when core power supply voltage VDD_CORE is not ready in the power initiation process, the accurate adjuster LS18 in position can export have low level output signal OUT_IO to sensing circuit 112 " in door AG10～AG1n, make burning circuit 114 " can be by forbidden energy.
In some embodiment, first driver 23 also can comprise nmos pass transistor MN2 and MN3, but does not comprise PMOS transistor MP2.In some embodiment, first driver 23 also can comprise PMOS transistor MP2, but does not comprise nmos pass transistor MN2 and MN3.In some embodiment, second driver 25 also can comprise nmos pass transistor MN4, but does not comprise nmos pass transistor MN5.In some embodiment, second driver 25 also can comprise nmos pass transistor MN5, but does not comprise nmos pass transistor MN4.
Fig. 7 A is an embodiment of on-off element.As shown in the figure, on-off element 116 comprises that a PMOS transistor P1 is coupled to external burning voltage EPS and resistance R P " between; and a nmos pass transistor N1 is coupled to resistance R P " and ground voltage GND between, wherein MOS transistor P1 is coupled to the output terminal of the accurate adjuster LS16 in position with the control end of N1.When core power supply voltage VDD_CORE in the power initiation process is not ready for and output signal OUTB_IO when being high logic level, the PMOS transistor can be cut off, and nmos pass transistor N1 can conducting.Therefore, external burning voltage EPS can with the writable unit 110 of electricity " in power bus 111 " disconnect, and can be discharged to earth terminal.In other words, in the power initiation process, no matter external burning voltage EPS why, and the accurate adjuster LS16 in position can close (ending) with on-off element 116 by output signal output OUTB_IO.When core power supply voltage VDD_CORE is not ready in the power initiation process, external burning voltage EPS can with the writable unit 110 of electricity " disconnect, therefore can avoid unexpected or wrong burning action.
When core power supply voltage VDD_CORE and I/O supply voltage all were ready for, LS16 can be according to external burning voltage enable signal EPS_EN, and output signal output OUTB_IO and OUT_IO come gauge tap element 116.In other words, after power initiation was finished, on-off element 116 optionally was connected to electric writable unit 110 with external burning voltage EPS according to external burning voltage enable signal EPS_EN " power bus 111 ".For example, when output signal OUTB_IO is low level, PMOS transistor P1 meeting conducting, nmos pass transistor N1 can end.Therefore, external burning voltage EPS can be connected to electric writable unit 110 " power bus 111 ", so that carry out electric writable unit 110 " burning or sensor operation.
If as PMOS transistor P1 during, sensing circuit 112 in cut-off state " do not need the output potential ground connection of on-off element 116, then nmos pass transistor N1 and inessential element.That is to say, in certain embodiments, do not need to implement nmos pass transistor N1, can satisfy and only need to implement PMOS transistor P1.
Fig. 7 B is another embodiment of on-off element.As shown in the figure, on-off element 116 " similar to the on-off element 116 shown in Fig. 7 A, its difference is that nmos pass transistor N2 is coupled to external burning voltage EPS and resistance R P " between.When core power supply voltage VDD_CORE was not ready in the power initiation process, if output signal OUTB_IO and OUT_IO are being arranged at high levels and low level respectively, PMOS transistor P1 and nmos pass transistor N2 can be cut off, and nmos pass transistor N1 can conducting.Therefore, external burning voltage EPS can with the writable unit 110 of electricity " power bus 111 " disconnect, and be discharged to earth terminal.When core power supply voltage VDD_CORE is not ready in the power initiation process, external burning voltage EPS can with the writable unit 110 of electricity " disconnect, therefore can avoid unexpected or wrong burning action.If as PMOS transistor P1 and nmos pass transistor N2 during, sensing circuit 112 in cut-off state " do not need the output potential ground connection of on-off element 116, then nmos pass transistor N1 and inessential element.That is to say, in certain embodiments, do not need to implement nmos pass transistor N1, and only need to implement PMOS transistor P1 and nmos pass transistor N2 can satisfy.
Fig. 8 is the analog result of memory circuitry among Fig. 5.As shown in the figure, because when core power supply voltage VDD_CORE is not ready in the power initiation process, output signal OUTB_IO can follow I/O supply voltage VDD_IO in order to external burning voltage EPS and power bus 111 " disconnect; so before core power supply voltage VDD_CORE is ready for; electric writable unit 110 " in power bus 111 " on voltage level VBUS remain on low level, so can avoid unexpected or wrong burning to move.
Fig. 9 is another embodiment of the accurate adjuster in position.As shown in the figure, the accurate adjuster 21B in position is similar to the accurate adjuster 21A in position shown in Fig. 6, and its difference is to remove first driver 23 and second driver 25 is realized by an on-off element 60.In certain embodiments, the transistor among the phase inverter INV0 is implemented by thin gate devices, and other transistor among the accurate adjuster 21B in position is implemented by thick gate devices.On-off element 60 is coupled between node N2 and the ground voltage GND, and is subjected to the control of the power-on reset circuits 70 of an outside.When core power supply voltage VDD_CORE was not ready in the power initiation process, outside power-on reset circuits 70 can produce a control signal SR and come gauge tap element 60, makes that the voltage level on the node N2 can be dragged down.When the position standard on the node N2 is dragged down by on-off element 60, PMOS transistor MP0 meeting conducting, and node N1 also can be drawn high to I/O supply voltage VDD_IO.In other words, when core power supply voltage VDD_CORE was not ready for, output signal OUTB_IO and OUT_IO can be arranged at high levels and low level respectively.
When core power supply voltage VDD_CORE is ready for, power-on reset circuits 70 can end on-off element 60 by control signal SR, the control that the phase inverter INV0 of feasible use core power supply voltage VDD_CORE can produce inversion signal and fetch the accurate adjuster 21B of contraposition.In some embodiment, on-off element 60 can be realized by an active member, for example MOS transistor, two-carrier transistor, connect the face field and imitate transistor npn npn or its combination.
Figure 10 is another embodiment of the accurate adjuster in position.As shown in the figure, the accurate adjuster 21C in position is similar with shown in Figure 6 accurate adjuster 21A, and its difference is that second driver 25 realized by on-off element 60.In certain embodiments, the transistor among the phase inverter INV0 is implemented by thin gate devices, and other transistor among the accurate adjuster 21C in position is implemented by thick gate devices.When core power supply voltage VDD_CORE is not ready in the power initiation process, because the AC coupling that stray capacitance Cgd or Cbg caused (AC coupling) of MOS transistor MP2, MN2 or MN3, voltage level on the node N1 can followed I/O supply voltage VDD_IO, and the voltage level on the node N2 can be pulled low to earth terminal by on-off element 60.In other words, when core power supply voltage VDD_CORE was not ready in the power initiation process, output signal OUTB_IO and OUT_IO can be set at high levels and low level respectively.When core power supply voltage VDD_CORE is ready for, outside power-on reset circuits 70 can end on-off element 60 by control signal SR, the control that the phase inverter INV0 of feasible use core power supply voltage VDD_CORE can produce inversion signal and fetch the accurate adjuster 21C of contraposition.
Figure 11 is another embodiment of the accurate adjuster in position.As shown in the figure, the accurate adjuster 21D in position is similar to the accurate adjuster 21A in position shown in Fig. 6, and its difference is that second driver 25 is realized by a resistance element 62, in order to drag down the voltage level on the node N2 at leisure.When core power supply voltage VDD_CORE is not ready in the power initiation process, because the AC coupling that stray capacitance Cgd or Cbg caused (AC coupling) of MOS transistor MP2, MN2 or MN3, voltage level on the node N1 can followed I/O supply voltage VDD_IO, and the voltage level on the node N2 can be dragged down at leisure by resistance element 62.In other words, when core power supply voltage VDD_CORE was not ready in the power initiation process, output signal OUTB_IO and OUT_IO can be set at high levels and low level respectively.For example, if resistance element 62 has enough resistances, when core power supply voltage VDD_CORE is ready for, it will can be considered a high impedance.Therefore, when core power supply voltage VDD_CORE is ready for, uses the phase inverter INV0 of core power supply voltage VDD_CORE can produce inversion signal, and fetch the control of the accurate adjuster 21D of contraposition.
Figure 12 A is an embodiment of resistance element.As shown in the figure, resistance element 62A is coupled between node N2 and the ground voltage GND, and comprises N PMOS transistor MPA1～MPAN that is connected in series, and a nmos pass transistor MNB is coupled between the ground voltage of PMOS transistor MPAN.Each PMOS transistor MPA1～MPAN all connects into the diode form, and promptly grid couples its source electrode.When core power supply voltage VDD_CORE was not ready in the power initiation process, nmos pass transistor MNB meeting conducting made that the voltage level on the node N2 can be dragged down at leisure.Therefore, when I/O supply voltage VDD_IO was ready for than core power supply voltage VDD_CORE is early, output signal OUTB_IO can be drawn high by first driver 23, and output signal OUT_IO can be dragged down at leisure by resistance element 62A.
Figure 12 B is another embodiment of resistance element.As shown in the figure, resistance element 62B is similar to the resistance element 62A shown in Figure 12 A, its difference is replaced by two-carrier transistor (BJTs) BTA1～BTAN at PMOS transistor MPA1～MPAN, the action of resistance element 62B is similar to the resistance element 62A shown in Figure 12 A, is not repeated in this.
Figure 12 C is another embodiment of resistance element.As shown in the figure, resistance element 62C is similar to the resistance element 62A shown in Figure 12 A, its difference is replaced by nmos pass transistor MNA1～MNAN at PMOS transistor MPA1～MPAN, and each nmos pass transistor MNA1～MNAN all connects into the diode form, and promptly grid couples its drain electrode.The action of resistance element 62C is similar to the resistance element 62A shown in Figure 12 A, is not repeated in this.
Figure 12 D is another embodiment of resistance element.As shown in the figure, resistance element 62D is similar to the resistance element 62A shown in Figure 12 A, its difference is coupled between PMOS transistor MPA0 and the MPA1～MPAN at nmos pass transistor MNB, and the action of resistance element 62D is similar to the resistance element 62A shown in Figure 12 A, is not repeated in this.
In certain this embodiment, position accurate adjuster LS16, LS17 and LS18 optionally remove.For example, when the writable unit 110 of electricity " in nmos pass transistor when being realized by thin gate devices, sensing circuit 112 " with burning circuit 114 " only need core power supply voltage VDD_CORE, therefore accurate adjuster LS17 in position and LS18 can be removed.Or say, when the writable unit 110 of electricity " in nmos pass transistor when being realized by thick gate devices, sensing circuit 112 " with burning circuit 114 " in the accurate adjuster in position can all realize by an accurate adjuster 21A, 21B, 21C or the 21D shown in Fig. 6, Fig. 9, Figure 10 and Figure 11.Also or say sensing circuit 112 " with burning circuit 114 " in the accurate adjuster in position can be all realize by the accurate adjuster 21A in position, 21B, 21C or the 21D shown in Fig. 6, Fig. 9, Figure 10 and Figure 11, but remove an on-off element 116 and an accurate adjuster LS16.
Owing to when memory circuitry of the present invention can core power supply voltage be ready in the power initiation process, external burning voltage and electric writable unit are disconnected, therefore can avoid because power supply startup sequence causes unexpected or wrong burning to move.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly knows the operator, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim scope person of defining.
Claims (22)
1. memory circuitry comprises:
One writable unit comprises:
The plural number burning elements; And
One power bus is coupled between external burning voltage and the above-mentioned burning elements;
One on-off element is coupled between said external burning voltage and the above-mentioned power bus, and above-mentioned on-off element comprises a control end; And
An accurate adjuster, in order to an activation voltage of signals position standard is adjusted to one first supply voltage by a second source voltage, wherein above-mentioned second source voltage is lower than said external burning voltage, and when above-mentioned second source voltage is not ready for as yet in the power initiation process, the accurate adjuster of last rheme is arranged at a set logic level with the control end of above-mentioned on-off element, make above-mentioned on-off element be cut off, and above-mentioned power bus can disconnect with said external burning voltage, so that avoid wrong burning.
2. memory circuitry as claimed in claim 1 is characterized in that above-mentioned burning elements respectively comprises a fuse.
3. memory circuitry as claimed in claim 1 is characterized in that, above-mentioned memory circuitry is a nonvolatile memory.
4. memory circuitry as claimed in claim 1 is characterized in that, above-mentioned memory circuitry is an electric writable storer.
5. memory circuitry as claimed in claim 1 is characterized in that, above-mentioned writable unit is a flash memory.
6. memory circuitry as claimed in claim 1 is characterized in that, above-mentioned first supply voltage is higher than said external burning voltage.
7. memory circuitry as claimed in claim 1 is characterized in that, when above-mentioned first, second supply voltage was ready for, the accurate adjuster of last rheme was adjusted to above-mentioned first supply voltage with the voltage level of above-mentioned enable signal by above-mentioned second source voltage.
8. memory circuitry as claimed in claim 1 is characterized in that, when above-mentioned second source voltage was not ready for as yet in power initiation, the accurate adjuster of last rheme was arranged at above-mentioned set logic level by AC coupling with the control end of above-mentioned on-off element.
9. memory circuitry as claimed in claim 7, it is characterized in that, when above-mentioned second source voltage is not ready for as yet in power initiation, when the accurate adjuster of last rheme according to a control signal from an external circuit, the control end of above-mentioned on-off element is arranged at above-mentioned set logic level.
10. memory circuitry as claimed in claim 7, it is characterized in that, when above-mentioned second source voltage is not ready for as yet in power initiation, when the accurate adjuster of last rheme by AC coupling and from a control signal of an external circuit, the control end of above-mentioned on-off element is arranged at above-mentioned set logic level.
11. a memory circuitry comprises:
One power-supply unit is in order to provide an external burning voltage; And
One writable unit comprises:
The plural number burning elements is coupled to a power bus; And
One burning circuit, in order to the above-mentioned burning elements of burning, above-mentioned burning circuit comprises that plural driver is coupled to above-mentioned burning elements, and one first accurate adjuster is powered by at least one first supply voltage, wherein above-mentioned first supply voltage is lower than said external burning voltage, when above-mentioned first supply voltage is not ready for as yet in the power initiation process, above-mentioned first accurate adjuster is arranged at one first set logic level with its output terminal, make that above-mentioned driver can be by forbidden energy, so that avoid wrong burning.
12. memory circuitry as claimed in claim 1, comprise that also a sensing circuit is in order to the above-mentioned burning elements of sensing, above-mentioned sensing circuit comprises that plural sensor is coupled to above-mentioned burning elements and one second accurate adjuster, when above-mentioned first supply voltage is not ready for as yet in the power initiation, above-mentioned second accurate adjuster is arranged at one second set logic level with its output terminal, makes that the above-mentioned sensor in the above-mentioned sensing circuit can be by forbidden energy.
13. memory circuitry as claimed in claim 12 also comprises:
One on-off element is connected between said external burning voltage and the above-mentioned power bus, and above-mentioned on-off element comprises a control end; And
One the 3rd accurate adjuster, in order to when above-mentioned first supply voltage is not ready for as yet in the power initiation, the control end of above-mentioned on-off element is arranged at one the 3rd set logic level, makes above-mentioned power bus and said external burning voltage disconnect, so that avoid wrong burning.
14. memory circuitry as claimed in claim 13 is characterized in that, above-mentioned each burning elements comprises a fuse and a transistor, is connected in series between an above-mentioned power bus and the ground voltage.
15. memory circuitry as claimed in claim 13, it is characterized in that, above-mentioned first, second, third accurate adjuster powered by above-mentioned first supply voltage and a second source voltage, wherein above-mentioned second source voltage is higher than said external burning voltage, when above-mentioned first, second supply voltage all was ready for, above-mentioned first, second, third accurate adjuster was in order to be adjusted to above-mentioned second source voltage with an activation voltage of signals position standard by above-mentioned first supply voltage.
16. the error action protecting method of a memory circuitry is characterized in that, above-mentioned memory circuitry comprises plural burning elements, a burning circuit and a sensing circuit, and above-mentioned error action protecting method comprises:
One on-off element is set between above-mentioned burning elements and an external burning voltage;
One first accurate adjuster is set in order to be coupled to a control end of above-mentioned on-off element, wherein above-mentioned first accurate adjuster powered by one first and one second source voltage, above-mentioned second source voltage is lower than above-mentioned first supply voltage, and above-mentioned first supply voltage is higher than said external burning voltage; And
When above-mentioned second source voltage is not ready for as yet in the power initiation process, the control end of above-mentioned on-off element is arranged at one first logic level, make above-mentioned on-off element be cut off, and above-mentioned power bus can disconnect with said external burning voltage.
17. error action protecting method as claimed in claim 16 also comprises:
One second accurate adjuster is set between the plural driver and a burning enable signal of above-mentioned burning circuit; And
When above-mentioned second source voltage is not ready for as yet in power initiation, above-mentioned second accurate regulator output is arranged at one second set logic level, makes that the above-mentioned driver in the above-mentioned burning circuit can be by forbidden energy.
18. error action protecting method as claimed in claim 17 also comprises:
One the 3rd accurate adjuster is set to be read between the enable signal in the plural sensor and of above-mentioned sensing circuit; And
When above-mentioned second source voltage is not ready for as yet in power initiation, above-mentioned the 3rd accurate regulator output is arranged at one the 3rd set logic level, makes that the above-mentioned sensor in the above-mentioned sensing circuit can be by forbidden energy.
19. error action protecting method as claimed in claim 18; it is characterized in that; above-mentioned first, second, third accurate adjuster is arranged at above-mentioned first, second, third set logic level by AC coupling or from a control signal of an external circuit with its output terminal.
20. an error action protecting method, it comprises:
When a core voltage is not ready for as yet, cut off an external burning voltage from burning elements; And
When above-mentioned core voltage is ready for, according to the binding between activation signal controlling said external burning voltage and above-mentioned burning elements.
21. error action protecting method as claimed in claim 20 also comprises:
When above-mentioned core voltage was not ready for as yet, the control end that an on-off element is set made external burning voltage and above-mentioned burning elements disconnect in a set logic level.
22. error action protecting method as claimed in claim 21 also comprises:
The voltage level of adjusting above-mentioned enable signal is a supply voltage; And
When above-mentioned core voltage is ready for, provide the control end of above-mentioned supply voltage, in order to the binding between control said external burning voltage and above-mentioned burning elements to above-mentioned on-off element.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US82638506P | 2006-09-21 | 2006-09-21 | |
| US60/826,385 | 2006-09-21 |
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| CN101149975A true CN101149975A (en) | 2008-03-26 |
| CN101149975B CN101149975B (en) | 2011-07-13 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102158589A (en) * | 2011-01-19 | 2011-08-17 | 宁波舜宇光电信息有限公司 | High-pixel photographic module and burning method for chip |
| CN104616696A (en) * | 2015-02-06 | 2015-05-13 | 浪潮电子信息产业股份有限公司 | EFUSE control method |
| CN108572315A (en) * | 2018-05-30 | 2018-09-25 | 东莞赛微微电子有限公司 | A kind of fuse state detection device |
| CN113763898A (en) * | 2021-08-31 | 2021-12-07 | 惠科股份有限公司 | Control circuit, driving method thereof and display device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI484313B (en) * | 2013-08-05 | 2015-05-11 | Nuvoton Technology Corp | Reference voltage generating circuit and voltage adjusting device having negative charge protection mechanism of the same |
| US9613714B1 (en) * | 2016-01-19 | 2017-04-04 | Ememory Technology Inc. | One time programming memory cell and memory array for physically unclonable function technology and associated random code generating method |
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2007
- 2007-09-20 TW TW96135125A patent/TWI344152B/en active
- 2007-09-21 CN CN2007101535460A patent/CN101149975B/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102158589A (en) * | 2011-01-19 | 2011-08-17 | 宁波舜宇光电信息有限公司 | High-pixel photographic module and burning method for chip |
| CN102158589B (en) * | 2011-01-19 | 2014-02-19 | 宁波舜宇光电信息有限公司 | High-pixel photographic module and burning method for chip |
| CN104616696A (en) * | 2015-02-06 | 2015-05-13 | 浪潮电子信息产业股份有限公司 | EFUSE control method |
| CN108572315A (en) * | 2018-05-30 | 2018-09-25 | 东莞赛微微电子有限公司 | A kind of fuse state detection device |
| CN113763898A (en) * | 2021-08-31 | 2021-12-07 | 惠科股份有限公司 | Control circuit, driving method thereof and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI344152B (en) | 2011-06-21 |
| TW200816207A (en) | 2008-04-01 |
| CN101149975B (en) | 2011-07-13 |
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