CN113763898A

CN113763898A - Control circuit, driving method thereof and display device

Info

Publication number: CN113763898A
Application number: CN202111009096.4A
Authority: CN
Inventors: 刘星汉; 马静
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2021-08-31
Filing date: 2021-08-31
Publication date: 2021-12-07

Abstract

The application provides a control circuit, a driving method thereof and a display device, and relates to the technical field of display, wherein the control circuit comprises: a memory having a first terminal, a switch sub-circuit, and a first voltage terminal and a second voltage terminal; the first end is connected with the first voltage end, and the switch sub-circuit is respectively connected with the first end, the first voltage end and the second voltage end; when the first voltage end provides the first voltage, the switch sub-circuit is switched off, and the first voltage is input into the first end; when the first voltage end does not provide the first voltage, the switch sub-circuit is conducted, and the second voltage provided by the second voltage end is input to the first end. This application switches over between closing and switching on through switch sub-circuit, can make first voltage end and second voltage end separately provide voltage for the memory to short circuit when avoiding providing voltage simultaneously between first voltage end and the second voltage end burns out the problem of memory.

Description

Control circuit, driving method thereof and display device

Technical Field

The application belongs to the technical field of display, and particularly relates to a control circuit, a driving method thereof and a display device.

Background

A TFT-LCD (Thin Film Transistor Liquid Crystal Display) is one of the main varieties of the current Display panel, and has become an important Display platform in modern IT and video products.

When the memory in the TFT-LCD is burned, a power supply is required to be connected to work, but whether the memory is connected with an internal power supply in the TFT-LCD or not is generally unknown, so that a power supply is usually externally connected to provide power for the memory. However, if the memory is connected to an internal power source and an external power source is provided, the two power sources will be in a short circuit state, which will generate current, and in severe cases, may cause the memory to be burned out. Thus, a circuit is desired that avoids the shorting problem described above.

Disclosure of Invention

The embodiment of the application provides a control circuit, a driving method thereof and a display device, wherein a switch sub-circuit is added on the periphery of a memory, the switch sub-circuit is disconnected when a first voltage is input at a first voltage end, and is connected when the first voltage end is not input, so that a second voltage is input at a second voltage end, and the problems that the memory is burnt out due to short circuit when voltage is simultaneously provided between the first voltage end and the second voltage end are solved.

In order to achieve the purpose, the technical scheme is as follows:

in a first aspect, a control circuit is provided, including: a memory having a first terminal, a switch sub-circuit, and a first voltage terminal and a second voltage terminal; the first end is connected with the first voltage end, and the switch sub-circuit is respectively connected with the first end, the first voltage end and the second voltage end; when the first voltage end provides a first voltage, the switch sub-circuit is switched off, and the first voltage is input to the first end; when the first voltage end does not provide the first voltage, the switch sub-circuit is conducted, and the second voltage provided by the second voltage end is input to the first end.

The control circuit provided by the embodiment of the application, by adding the switch sub-circuit at the periphery of the memory, the switch sub-circuit is switched off when the first voltage end inputs the first voltage, and is switched on when the first voltage end does not input the first voltage, so that the second voltage end inputs the second voltage. Therefore, the switch sub-circuit is switched between off and on, so that the first voltage end and the second voltage end can separately provide voltage for the memory, and the problems that the memory is burnt due to short circuit when the voltage is provided between the first voltage end and the second voltage end at the same time are solved.

Optionally, as a possible implementation manner, the switch sub-circuit includes: a first transistor and a first resistor; the grid electrode and the source electrode of the first transistor are both connected with the first voltage end, and the drain electrode of the first transistor is connected with the second voltage end; one end of the first resistor is connected with the grid, and the other end of the first resistor is connected with a grounding end.

Optionally, as a possible implementation manner, the first transistor is a P-channel metal oxide semiconductor field effect transistor.

In a second aspect, a control circuit is provided, comprising: a memory having a first terminal, a second terminal, and a third terminal; the first end is connected with the second voltage end, the second end is connected with the first voltage end, and the third end is connected with the grounding sub-circuit; the memory also comprises a switch sub-circuit which is respectively connected with the first end, the second end and the third end; when the first voltage end provides a first voltage, the switch sub-circuit is switched off, and the first voltage is input to the second end; when the first voltage end does not provide the first voltage, the switch sub-circuit is conducted, and the second voltage is input to the first end.

The control circuit that this application embodiment provided, through increase the switch sub-circuit in the inside of memory, the switch sub-circuit breaks off when first voltage end input first voltage, and switches on when first voltage end does not input for second voltage end input second voltage. Therefore, the switch sub-circuit is switched between off and on, so that the first voltage end and the second voltage end can separately provide voltage for the memory, and the problems that the memory is burnt due to short circuit when the voltage is provided between the first voltage end and the second voltage end at the same time are solved.

Optionally, as a possible implementation manner, the switch sub-circuit includes: a first transistor;

the grid electrode and the source electrode of the first transistor are both connected with the first end, the drain electrode of the first transistor is connected with the second end, and the grid electrode of the first transistor is also connected with the third end.

Optionally, as a possible implementation manner, the ground sub-circuit includes: and one end of the first resistor is connected with the third end, and the other end of the first resistor is connected with a grounding end.

In a third aspect, a display device is provided, which includes a display panel and an internal power supply, and further includes the control circuit described in the first aspect or any possible implementation manner of the first aspect; the internal power supply is used for providing a first voltage for the first voltage end.

In a fourth aspect, a display device is provided, which includes a display panel and an internal power supply, and further includes the control circuit described in the second aspect or any possible implementation manner of the second aspect; the internal power supply is used for providing a first voltage for the first voltage end.

In a fifth aspect, a method for driving a control circuit according to the first aspect, includes: when the first voltage end provides a first voltage, the switch sub-circuit is switched off, and the first voltage is input to the first end; when the first voltage end does not provide the first voltage, the switch sub-circuit is conducted, and the second voltage provided by the second voltage end is input to the first end.

A sixth aspect provides a computer-readable storage medium having stored therein a computer program or instructions which, when read and executed by a computer, cause the computer to execute the driving method of the control circuit as described in the above first aspect.

The advantageous effects of the third aspect to the sixth aspect can refer to the advantageous effects of the first aspect and/or the second aspect, and are not described herein again.

Drawings

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present disclosure;

FIG. 2 is a circuit diagram of a first memory according to a second embodiment of the present disclosure;

FIG. 3 is a circuit diagram of a second memory according to a second embodiment of the present application;

fig. 4 is a circuit schematic diagram of a memory according to a third embodiment of the present application.

Reference numerals:

1-a display device; 10-a display panel; 20-a control circuit board; 21-a time schedule controller; 22-data driving chip; 23-a memory; 30-a switch sub-circuit; 31-a first transistor; 32-a first resistance; 40-ground subcircuit; IN 1-first end; IN 2-second end; VDD — first voltage terminal; VCC-a second voltage terminal; 100-control circuit.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

In the description of the embodiments of the present application, "/" means "or" unless otherwise specified, for example, a/B may mean a or B; "and/or" herein is merely an association describing an associated object, and means that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present embodiment, "a plurality" means two or more unless otherwise specified.

The word "comprising" or "comprises", and the like, means that the element or item preceding the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The directional terms "left", "right", "upper" and "lower" are defined relative to the orientation in which the display assembly is schematically positioned in the drawings, and it is to be understood that these directional terms are relative concepts that are used for descriptive and clarity relative to each other and that may vary accordingly depending on the orientation in which the display assembly is positioned.

The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Example one

Fig. 1 is a schematic structural diagram of a display device 1 according to an embodiment of the present disclosure. As shown in fig. 1, the display device 1 includes: a display panel 10 and a control circuit board 20.

The control circuit board 20 includes: a Timing Controller (TCON) 21, a data Driver IC (Source Driver IC)22 connected to the timing controller 21, and a memory 23 connected to the timing controller 21.

The control circuit board 20 connects the data driving chip 22 in the control circuit board 20 to the display panel 10 by using a printed circuit board (FPC) through a bonding technique. The memory 23 and the timing controller 21 are connected via an Integrated Circuit bus (I2C/IIC, Inter-Integrated Circuit).

It should be understood that the input signal is inputted into the control circuit board 20, processed by the timing controller 21 and converted into a signal format recognizable by the data driving chip 22, and then processed by the data driving chip 22 and provided to the display panel 10 for display.

Here, the memory 23 is used to store codes (codes) in advance, and the timing controller 21 is used to read the codes from the memory 23 by referring to addresses and to run corresponding settings, as needed. The Memory 23 is a charged Erasable Programmable read only Memory 23 (EEPROM) or a Flash Memory (Flash EEPROM). Of course, the memory 23 may also be other kinds of devices, and may be specifically selected and configured according to needs, which is not limited in any way by the embodiment of the present application.

It should be noted that the code stored in the memory 23 is written into the memory 23 in advance by using software through a connector or a burning tool. However, during the burning, the memory 23 is powered on to operate.

Taking an EEPROM as an example, the first type: the EEPROM may be supplied with an operating voltage using an internal power supply in the TFT-LCD that supplies a voltage to the display panel. And the second method comprises the following steps: an external power supply can be directly connected to the EEPROM without using an internal power supply in the TFT-LCD. Illustratively, the operating voltage provided by the two modes for the EEPROM is 3.3V.

If the EEPROM is connected with an internal power supply in the TFT-LCD and an external power supply, two power supplies are simultaneously connected to the first end of the EEPROM, and the two power supplies are in a short-circuit state. Based on this, the two inconsistent voltages may cause current to flow inside the EEPROM, which may cause the circuit and the EEPROM to be burned down in severe cases.

In order to solve the problem, the application provides a control circuit, through the external MOS transistor of the first end at memory 23, perhaps, be connected with internal power supply and external power supply respectively through two first ends to through at two first end internal connection MOS transistors, thereby can make control circuit switch on, make only have the power of the same way to supply power, thereby prevent that two power shorts from being in the same place, avoid appearing the problem of short circuit.

The control circuit provided by the embodiment of the present application is described in detail below with reference to fig. 2 to 4.

Example two

Fig. 2 to fig. 3 respectively show structural schematic diagrams of a control circuit 100 according to an embodiment of the present application.

As shown in fig. 2, an embodiment of the present application provides a control circuit 100, where the control circuit 100 includes: a memory 23 having a first terminal IN1, a switch sub-circuit 30, and a first voltage terminal VDD and a second voltage terminal VCC.

The first terminal IN1 of the memory 23 is connected to the first voltage terminal VDD, and the switch sub-circuit 30 is respectively connected to the first terminal IN1, the first voltage terminal VDD, and the second voltage terminal VCC.

When the first voltage terminal VDD provides the first voltage, the switch sub-circuit 30 is turned off, and the first voltage is inputted to the first terminal IN 1. That is, only the first voltage terminal VDD supplies power to the first terminal IN1 of the memory 23, and the power is the first voltage.

When the first voltage terminal VDD does not provide the first voltage, the switch sub-circuit 30 is turned on, and the second voltage provided by the second voltage terminal VCC is input to the first terminal IN 1. That is, only the second voltage terminal VCC supplies power to the first terminal IN1 of the memory 23, and the power is the second voltage.

It should be understood that the magnitudes of the first voltage and the second voltage can be set and changed as required, and the embodiment of the present application does not set any limitation.

The first voltage and the second voltage may be the same or different. For example, the first voltage level is 3.3V, and the second voltage level is also 3.3V.

The embodiment of the application provides a control circuit, and by adding a switch sub-circuit at the periphery of a memory, the switch sub-circuit is switched off when a first voltage is input at a first voltage end, and is switched on when the first voltage end is not input, so that a second voltage is input at a second voltage end. Therefore, the switch sub-circuit is switched between off and on, so that the first voltage end and the second voltage end can separately provide voltage for the memory, and the problems that the memory is burnt due to short circuit when the voltage is provided between the first voltage end and the second voltage end at the same time are solved.

Alternatively, as a possible implementation, as shown in fig. 3, the switch sub-circuit 30 includes: a first transistor 31 and a first resistor 32.

The gate and the source of the first transistor 31 are both connected to a first voltage terminal VDD, and the drain of the first transistor 31 is connected to a second voltage terminal VCC.

One end of the first resistor 32 is connected to the gate, and the other end is connected to the ground GND.

It should be noted that the switch sub-circuit 30 may further include a plurality of switch transistors connected in parallel with the first transistor 31, and/or a plurality of resistors connected in parallel with the first resistor 32. The above is merely an illustration of the switch sub-circuit 30, and other structures having the same functions as the switch sub-circuit 30 are not described in detail herein, but all should fall within the scope of the present invention.

Optionally, as a possible implementation, the first transistor 31 is a P-channel metal oxide semiconductor field effect transistor.

Based on this structure, when the first voltage terminal VDD provides the first voltage, the first voltage terminal VDD provides the first voltage to both the first terminal IN1 of the memory 23 and the gate of the first transistor 31, and the gate of the first transistor 31 is at a high level, at this time, the first transistor 31 is turned off, and thus the second voltage terminal VCC cannot provide the second voltage to the memory 23.

When the first voltage terminal VDD does not provide the first voltage, the first voltage terminal VDD neither provides the first voltage to the first terminal IN1 of the memory 23 nor provides the first voltage to the gate of the first transistor 31, and the gate of the first transistor 31 is at a low level, at this time, the first transistor 31 is turned on, so that the second voltage terminal VCC can provide the second voltage to the memory 23.

It should be appreciated that, here, in order to protect the circuit, a first resistor 32 is added between the gate of the first transistor 31 and the ground terminal to maintain the high state at the gate to keep it off when the first voltage is provided at the first voltage terminal VDD.

EXAMPLE III

Fig. 4 shows a schematic structural diagram of another control circuit 100 provided in the embodiment of the present application.

As shown in fig. 4, an embodiment of the present application provides a control circuit 100, where the control circuit 100 includes: a memory 23 having a first terminal IN1, a second terminal IN2, and a third terminal OUT. The first terminal IN1 is connected to the second voltage terminal VCC, the second terminal IN2 is connected to the first voltage terminal VDD, and the third terminal OUT is connected to the ground sub-circuit 40.

The memory 23 further includes a switch sub-circuit 30, and the switch sub-circuit 30 is respectively connected to the first terminal IN1, the second terminal IN2, and the third terminal OUT.

When the first voltage terminal VDD provides the first voltage, the switch sub-circuit 30 is turned off, and the first voltage is inputted to the second terminal IN 2.

When the first voltage terminal VDD does not provide the first voltage, the switch sub-circuit 30 is turned on, and the second voltage provided by the second voltage terminal VCC is input to the first terminal IN 1.

When the first voltage terminal VDD provides the first voltage, the switch sub-circuit 30 is turned off, and the first voltage is inputted to the second terminal IN 2. That is, only the first voltage terminal VDD supplies power to the second terminal IN2 of the memory 23, and the power is the first voltage.

The embodiment of the application provides a control circuit, and by adding a switch sub-circuit in a memory, the switch sub-circuit is switched off when a first voltage is input at a first voltage end, and is switched on when the first voltage end is not input, so that a second voltage is input at a second voltage end. Therefore, the switch sub-circuit is switched between off and on, so that the first voltage end and the second voltage end can separately provide voltage for the memory, and the problems that the memory is burnt due to short circuit when the voltage is provided between the first voltage end and the second voltage end at the same time are solved.

Optionally, as a possible implementation manner, the switch sub-circuit 30 includes: a first transistor 31.

The gate and the source of the first transistor 31 are both connected to the first terminal IN1, the drain of the first transistor 31 is connected to the second terminal, and the gate of the first transistor 31 is further connected to the third terminal.

Optionally, as a possible implementation manner, the first transistor 31 is a P-channel metal oxide semiconductor field effect transistor.

It should be noted that the switch sub-circuit 30 may further include a plurality of switch transistors connected in parallel with the first transistor 31. The above is merely an illustration of the switch sub-circuit 30, and other structures having the same functions as the switch sub-circuit 30 are not described in detail herein, but all should fall within the scope of the present invention.

Optionally, as a possible implementation manner, the grounding sub-circuit 40 includes: and one end of the first resistor 32 is connected with the third end, and the other end of the first resistor 32 is connected with the ground terminal.

It should be noted that the ground sub-circuit 40 may further include a plurality of resistors connected in parallel with the first resistor 32. The above description is only an example of the grounding sub-circuit 40, and other structures having the same function as the grounding sub-circuit 40 are not described in detail herein, but all of them should fall within the scope of the present invention.

Example four

The embodiment of the present application further provides a display device, which includes a display panel and an internal power supply, and further includes a control circuit 100 as shown in fig. 2 or fig. 3.

The internal power supply is used for providing a first voltage for the first voltage terminal VDD. In addition, the external power supply is used for providing a second voltage for the second voltage terminal.

The display device provided by the embodiment of the application can prevent the risk of burning out a circuit caused by the short circuit of two power supplies when the display device uses the I2C to burn the codes for the time schedule controller 21 and simultaneously accesses the external power supply and the internal power supply under the condition that the I2C is used to burn the codes for the time schedule controller 21.

The embodiment of the present application further provides a display device, which includes a display panel and an internal power supply, and further includes a control circuit 100 as shown in fig. 4.

The internal power supply is used for providing a first voltage for the first voltage terminal VDD. In addition, the external power supply is used for providing a second voltage for the second voltage terminal VCC.

With reference to fig. 2, an embodiment of the present application further provides a driving method of a control circuit, including:

when the first voltage terminal VDD provides the first voltage, the switch sub-circuit 30 is turned off, and the first voltage is inputted to the first terminal IN 1.

The beneficial effects of the driving method of the control circuit provided by the embodiment of the application are the same as the corresponding beneficial effects of the control circuit, and are not repeated herein.

The embodiment of the present application further provides a computer-readable storage medium, in which a computer program or an instruction is stored, and when the computer program or the instruction is read and executed by a computer, the computer is enabled to execute the driving method of the control circuit.

The beneficial effects of the computer-readable storage medium provided by the embodiment of the application are the same as the beneficial effects corresponding to the control circuit, and are not described herein again.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not cause the essential features of the corresponding technical solutions to depart from the spirit scope of the technical solutions of the embodiments of the present application, and are intended to be included within the scope of the present application.

Claims

1. A control circuit, comprising: a memory having a first terminal, a switch sub-circuit, and a first voltage terminal and a second voltage terminal;

the first end is connected with the first voltage end, and the switch sub-circuit is respectively connected with the first end, the first voltage end and the second voltage end;

when the first voltage end provides a first voltage, the switch sub-circuit is switched off, and the first voltage is input to the first end; when the first voltage end does not provide the first voltage, the switch sub-circuit is conducted, and the second voltage provided by the second voltage end is input to the first end.

2. The control circuit of claim 1, wherein the switch sub-circuit comprises: a first transistor and a first resistor;

the grid electrode and the source electrode of the first transistor are both connected with the first voltage end, and the drain electrode of the first transistor is connected with the second voltage end;

one end of the first resistor is connected with the grid, and the other end of the first resistor is connected with a grounding end.

3. The control circuit of claim 2, wherein the first transistor is a P-channel metal oxide semiconductor field effect transistor (pmos).

4. A control circuit, comprising: a memory having a first terminal, a second terminal, and a third terminal; the first end is connected with the second voltage end, the second end is connected with the first voltage end, and the third end is connected with the grounding sub-circuit;

the memory also comprises a switch sub-circuit which is respectively connected with the first end, the second end and the third end;

when the first voltage end provides a first voltage, the switch sub-circuit is switched off, and the first voltage is input to the second end; when the first voltage end does not provide the first voltage, the switch sub-circuit is conducted, and the second voltage is input to the first end.

5. The control circuit of claim 4, wherein the switch sub-circuit comprises: a first transistor;

6. The control circuit of claim 4 or 5, wherein the ground sub-circuit comprises: and one end of the first resistor is connected with the third end, and the other end of the first resistor is connected with a grounding end.

7. The control circuit of claim 5, wherein the first transistor is a P-channel metal oxide semiconductor field effect transistor.

8. A display device comprising a display panel and an internal power supply, characterized by further comprising a control circuit according to any one of claims 1 to 3;

the internal power supply is used for providing a first voltage for the first voltage end.

9. A display device comprising a display panel and an internal power supply, characterized by further comprising a control circuit according to any one of claims 4 to 7;

10. A driving method of the control circuit according to any one of claims 1 to 3, comprising:

when the first voltage end provides a first voltage, the switch sub-circuit is switched off, and the first voltage is input to the first end;

when the first voltage end does not provide the first voltage, the switch sub-circuit is conducted, and the second voltage provided by the second voltage end is input to the first end.