CN110120196B - Level conversion control circuit and array substrate driving circuit - Google Patents
Level conversion control circuit and array substrate driving circuit Download PDFInfo
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- CN110120196B CN110120196B CN201910268931.2A CN201910268931A CN110120196B CN 110120196 B CN110120196 B CN 110120196B CN 201910268931 A CN201910268931 A CN 201910268931A CN 110120196 B CN110120196 B CN 110120196B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
A level shift control circuit and an array substrate driving circuit are provided. The level shift control circuit comprises a switch tube and a control circuit, is used for outputting a high level and a low level to a grid line of the array substrate and has a first reference level. The drain electrode of the switch tube is connected with the first reference level, and the source electrode of the switch tube is connected with the low level. The control circuit is connected with the grid electrode of the switch tube and is used for controlling the on and off of the switch tube. When the control circuit enables the switch tube to be conducted, the drain electrode of the switch tube is in short circuit with the source electrode of the switch tube, and the low level and the first reference level form a constant level. The array substrate provided by the invention can avoid latch-up effect caused by the fact that the level of a low-level signal is higher than a reference level.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel with a GOA unit.
Background
With the progress of display technology, in addition to the improvement of display quality of the display, in order to make the user have better visual experience, the frame of the display is gradually narrowed, and the display is developed toward a frameless display panel frame.
In the conventional Array substrate having thin film transistors arranged in an Array, a Gate On Array (GOA) display technology integrates and manufactures a GOA unit On the Array substrate, instead of the conventional Gate driving unit and source driving unit which are respectively located at the longitudinal and transverse sides of a display panel. In the GOA display technology, the GOA units have gate driving units corresponding to the number of data lines, the gate driving units are arranged on one side of the array substrate, and the gate driving units can send scanning signals to a plurality of gate lines arranged in parallel line by line to turn on the thin film transistors on the array substrate line by line, thereby driving the pixel units of the display to display gray scales. The GOA unit is integrated on the array substrate, so that the frame area occupied by the old gate driving unit is saved, and the design of the narrow-frame panel is realized.
In the GOA display technology, the progressive scanning process requires sequentially outputting high levels to the gate lines, and providing low levels to the gate lines except for the expected scanning time, so the GOA unit usually has a Level shift chip (Level shift IC) for switching the high and low levels to provide the levels required by the gate lines, so as to facilitate the correct scanning operation of the display panel.
In the manufacturing process of the chip, the lowest level is used as the substrate, and in the level shift circuit, there are two sets of negative voltages VGL and VSS, where VGL is a low level signal provided to the gate line, and VSS is a zero level reference signal of the level shift circuit. However, when the level shifter operates normally, the level of VGL is the lowest level in the level shifter, i.e., VSS is greater than or equal to VGL. However, during the Power on/off process of the display, when the Power management chip (PMIC) is not fully operated or stopped, the levels of VGL and VSS may be unstable, and the level of VGL may be higher than VSS. Since VGL as the substrate is no longer the lowest level, the parasitic diode in the level shifter circuit is turned on, so that the level shifter circuit may generate a Latch Up (Latch Up) effect, which may cause the chip to fail, or even cause the chip to be damaged, thereby affecting the operation of the display.
Therefore, it is desirable to provide a GOA unit, which can prevent the VSS level of the level shift circuit therein from being lower than VGL, so as to maintain the normal operation of the level shift circuit.
Disclosure of Invention
The invention aims to provide an array substrate and a level conversion control circuit, wherein a switch tube or a control circuit is used for controlling the connection between two negative level terminals for outputting a low level signal and a reference signal, so that a base signal in the level conversion circuit is kept at the lowest level, and the latch-up effect caused by the conduction of a parasitic diode in a chip is avoided.
The invention provides a level conversion control circuit, which comprises a switch tube and a control circuit, is used for outputting a high level and a low level to a grid line of an array substrate and has a first reference level. The drain electrode of the switch tube is connected with the first reference level, and the source electrode of the switch tube is connected with the low level. The control circuit is connected with the grid electrode of the switch tube and is used for controlling the on and off of the switch tube. When the control circuit enables the switch tube to be conducted, the drain electrode of the switch tube is in short circuit with the source electrode of the switch tube, and the low level and the first reference level form a constant level. .
Preferably, the control circuit includes a comparator having a positive input terminal and a negative input terminal, the positive input terminal is connected to the low level, the negative input terminal is connected to the first reference level, when the low level is higher than the first reference level, the control circuit turns on the switch tube, and when the low level is lower than the first reference level, the control circuit turns off the switch tube.
Preferably, the control circuit is a double-throw switch, the double-throw switch is used for connecting the low level or the ground level, the low level is lower than the ground level, and when the double-throw switch is connected with the ground level, the switch tube is conducted to enable the low level to be in short circuit with the first reference level to form a constant level.
Preferably, the control circuit includes a first comparator and a second comparator, the first comparator has a first positive input terminal and a first negative input terminal, the first positive input terminal is connected to the low level, the first negative input terminal is connected to the first reference level, when the low level is higher than the first reference level, the control circuit turns on the switching tube, and when the low level is lower than the first reference level, the control circuit turns off the switching tube.
Preferably, the second comparator has a second positive input terminal and a second negative input terminal, the second positive input terminal is connected to a second reference level, the second negative input terminal is connected to a detection result, when the second reference level is greater than the detection result, the control circuit turns on the switch tube, and when the second reference level is lower than the detection result and the low level is lower than the first reference level, the control circuit turns off the switch tube.
Preferably, the level shift control circuit is an integrated circuit.
The invention also provides an array substrate driving circuit which comprises the level conversion control circuit.
Preferably, the array substrate driving circuit includes a power management chip, and when the power management chip stops working, the switching tube is turned on to short-circuit the low level and the first reference level to form a constant level.
The invention further provides a level shift circuit comprising a switch tube, a first comparator and a second comparator, wherein the level shift circuit has a low level and a first reference level. The drain electrode of the switch tube is connected with the first reference level, and the source electrode of the switch tube is connected with the low level. The first comparator has a first positive input terminal and a first negative input terminal, the first positive input terminal is connected to the low level, the first negative input terminal is connected to the first reference level, when the low level is higher than the first reference level, the control circuit turns on the switch tube, and when the low level is lower than the first reference level, the control circuit turns off the switch tube. The second comparator has a second positive input terminal and a second negative input terminal, the second positive input terminal is connected to a second reference level, the second negative input terminal is connected to a detection result, when the second reference level is greater than the detection result, the control circuit turns on the switching tube, and when the second reference level is lower than the detection result and the low level is lower than the first reference level, the control circuit turns off the switching tube. .
Preferably, the level shift circuit is connected to a power management chip, and when the power management chip stops working, the switching tube is turned on to short-circuit the low level and the first reference level to form a constant level.
The invention has the advantages that the low level signal and the reference level provided by the level conversion control circuit are respectively connected with the source electrode and the drain electrode of the switch tube, the on-off of the switch tube is controlled by using a simple switch unit or a control circuit, and when the working voltage of the power management chip or the level conversion control circuit is abnormal, the on-off of the switch tube is switched on to ensure that the reference level and the low level signal are in short circuit to form an equal level so as to avoid the latch-up effect caused by the level of the low level signal being higher than the reference level. The array substrate and the level conversion control circuit provided by the invention can control the low level signal and the reference level by simple elements without additional control elements and control signals, and prevent the level conversion control circuit from being incapable of operating or even damaged due to latch-up effect generated when the display panel is turned on or turned off, thereby maintaining the normal operation of the GOA unit on the array substrate and the display panel.
Drawings
Fig. 1 is a schematic structural diagram of a GOA display panel according to the present invention.
Fig. 2 is a circuit diagram of a level shift control circuit according to a first embodiment of the invention.
FIG. 3 is a circuit diagram of a level shift control circuit according to a second embodiment of the present invention.
FIG. 4 is a circuit diagram of a level shift control circuit according to a third embodiment of the present invention.
FIG. 5 is a circuit diagram of a level shift control circuit according to a fourth embodiment of the present invention.
Detailed Description
The following describes the display panel and the display device provided by the present invention in detail with reference to the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic structural diagram of a GOA display panel according to the present invention. The display panel 10 of the present invention includes an array substrate 12, a plurality of gate lines 14, a gate driver on array (GOA) unit 16, and a Level Shift circuit 18. The GOA units 16 are integrally disposed on the array substrate 12 and are configured to provide scanning driving signals to the gate lines 14. The display panel 10 has n Gate lines 14 disposed in parallel on the array substrate 12, and the GOA unit 16 outputs scanning signals to the Gate lines Gate (1) to Gate (n). When the display panel 10 displays a picture, it is necessary to sequentially send scanning signals to the gate lines of each row, that is, the GOA units 16 need to sequentially send high level signals to the gate lines of each row to drive the thin film transistors on the array substrate 12, and only one row of thin film transistors is driven at the same time, that is, only the gate line of the row outputting the scanning signals receives a high level signal, and the other gate lines receive low level signals, so that the GOA units 16 need the level conversion circuit 18 to rapidly switch the high and low level signals. However, during the power-on and power-off of the display panel 10, the substrate level in the level shifter 18 (i.e. the signal with the lowest level in the chip) may be higher than other voltage signals in the level shifter 18 due to the power management chip 15 not operating, causing the level shifter to latch up and fail to operate normally, or even to overheat and cause damage. Therefore, in order to avoid latch-up of the electrical conversion chip 18, the present invention provides a control circuit for controlling the level shift circuit, so that the substrate level of the chip is kept at the lowest level.
Fig. 2 is a schematic diagram of a level shift control circuit according to a first embodiment of the invention.
As shown in fig. 2, the level shift control circuit 20 includes a level shift circuit 18 and a control circuit 200. The level shift circuit 18 can rapidly switch the gate signals VGL and VGH, where VGL is a low level signal (i.e., a negative voltage) and VGH is a high level signal (i.e., a positive voltage), and the VGL and VGH are provided to the gate lines 14 in the display panel 10, when the gate lines 14 receive VGH, the thin film transistors in the row are driven, and the other gate lines receive VGL signals. For example, at time t1, the Gate line Gate 1 receives the high level signal VGH, the Gate lines Gate 2 to Gate n receive the low level signal VGL, and at time t2, the Gate line Gate 2 receives the high level signal VGH, the signal received by the Gate 1 is converted from the high level signal VGH to the low level signal VGL, the Gate lines Gate 3 to Gate n continuously receive the low level signal VGL, and so on. Therefore, the level shifter 18 in the GOA unit 16 is used to rapidly switch the high level signal VGH and the low level signal VGL to scan the gate lines 14 row by row.
The level shift circuit 18 also provides a reference level VSS as a common reference potential. When the level shift circuit 18 normally operates, the level of the reference level VSS is higher than the low level signal VGL, however, when the display panel is turned on or off, the voltage of the level shift circuit 18 is unstable because the power management chip 15 may not operate yet or has stopped operating, so that the level shift circuit 18 may have a higher potential than the reference level VSS, and the level shift circuit 18 may generate a latch-up effect because the parasitic diode is turned on.
Therefore, in the first embodiment of the present invention, the control circuit 200 utilizes a switch 22 to prevent the low level signal VGL from being higher than the reference level VSS. Specifically, the drain of the switch 22 is connected to the reference level VSS, and the source of the switch 22 is connected to the low level signal VGL, when the power management chip 15 in the GOA unit 16 operates normally, the control terminal of the switch 22 (the gate of the switch 22) receives a low level to turn off the switch, so that the reference level VSS and the low level signal VGL operate independently without mutual influence. However, when the power management chip 15 in the GOA unit 16 stops operating, the control terminal of the switch 22 receives a high level to turn on, so that the two pins of the level shifter 18 for outputting the reference level VSS and the low level signal VGL are shorted, so that the reference level VSS and the low level signal VGL form equal levels. Therefore, it is avoided that the low level signal VGL is higher than the reference level VSS when the power management chip 15 stops operating. The control terminal can control the input level through a controller, a control circuit or a switch unit.
Fig. 3 is a schematic diagram of a level shift control circuit according to a second embodiment of the invention. As shown, the level shift control circuit 30 includes a level shift circuit 18 and a control circuit 300. The level shifter 18 also has a reference level VSS, a low level signal VGL, and a high level signal VGH. The control circuit 300 of the second embodiment has a comparator 34 in addition to the switch tube 32. The positive input terminal of the comparator 34 receives the low level signal VGL, and the negative input terminal of the comparator 34 is connected to the reference level VSS. The drain of the switch 32 is connected to the reference level VSS, and the source is connected to the low level signal VGL. Therefore, when the power management chip 15 in the GOA unit 16 operates normally, the voltage level of the low level signal VGL is lower than the reference level VSS, and the comparator 34 outputs a low level to the control terminal of the switch 32 to make the switch 32 turned off, so that the reference level VSS and the low level signal VGL operate independently without mutual influence. When the power management chip 15 in the GOA unit 16 does not operate normally and the voltage level of the low level signal VGL is higher than the reference level VSS, the comparator 34 outputs a high level to the control terminal of the switch 32 to turn on the switch 32, so that the two pins of the level shift circuit 18 for outputting the reference level VSS and the low level signal VGL are shorted, and the reference level VSS and the low level signal VGL form equal levels.
Fig. 4 is a schematic diagram of a level shift control circuit according to a third embodiment of the invention. The level shift control circuit 40 of the third embodiment includes a level shift circuit 18 and a control circuit 400. The level shifter 18 also provides three levels of the reference level VSS, the low level signal VGL and the high level signal VGH. The control circuit 400 of the third embodiment includes a switch 42 and a comparator 44, wherein the drain of the switch 42 is also connected to the reference level VSS, and the source is connected to the low level signal VGL. The positive input terminal of the comparator inputs a comparison reference voltage Vref, the negative input terminal of the comparator inputs a result voltage Vi, Vi is a result voltage of the detection input voltage Vin, Vin is an input voltage of the GOA unit 16 or a working voltage of the display panel 10 in the present embodiment, and Vref may be an Under-voltage-Lockout (UVLO) voltage for monitoring a working voltage of the GOA unit 16 or the display panel 10, when the working voltage of the GOA unit 16 or the display panel 10 is lower than the UVLO voltage, it indicates that the GOA unit 16 or the display panel 10 is not normally operated or is in a non-working state, and thus the input voltage Vin is lower than the UVLO voltage. Therefore, when the input voltage Vin is lower than the UVLO, which represents that the power management chip 15 is not in the operating state, the comparator 44 outputs a high level to the switch tube 42 because the comparison reference voltage Vref is greater than the result voltage Vi, and therefore the switch tube 42 is turned on, so that the two pins of the level shift circuit 18 for outputting the reference level VSS and the low level signal VGL are shorted, and the reference level VSS and the low level signal VGL form equal levels.
Fig. 5 shows a fourth embodiment of the level shift control circuit according to the present invention. The level shift control circuit 50 includes a level shift circuit 18 and a control circuit 500. The level shifter 18 also provides three levels of the reference level VSS, the low level signal VGL and the high level signal VGH. The control circuit 500 in the fourth embodiment includes a switching tube 52, a first comparator 54, a second comparator 56, and a switching unit 58. The switch unit 58 controls the signal input to the control terminal of the switch tube 52 according to the control signal EN. The control signal EN of the switching unit is generated according to the output signals of the first comparator 54 and the second comparator 56. Specifically, the first comparator 54 has a positive input terminal receiving the low level signal VGL and a negative input terminal connected to the reference level VSS. The positive input terminal of the second comparator 56 inputs the comparison reference voltage Vref, the negative input terminal inputs the result voltage Vi, Vi is the result voltage of the detection input voltage Vin, Vin in the fourth embodiment may also be the input voltage of the GOA unit 16 or the working voltage of the display panel 10, and Vin may also be the detection result of the detection circuit in the display panel 10 for monitoring the working voltage of the source driving unit of the display panel 10 or the detection result of the other detection circuit for the working voltage of other elements in the display panel 10. The reference voltage Vref may be an Under-voltage-Lockout (UVLO) voltage for monitoring an operating voltage of the GOA unit 16 or the display panel 10, or may also be a reference voltage for monitoring a source driving unit reference voltage of the display panel 10 or for monitoring an operating state of other elements operating in the display panel 10. Therefore, when the input voltage Vin is lower than Vref, it indicates that the display panel 10, the GOA unit 16 or a specific device therein is not in an operating state, and therefore the second comparator 56 outputs a high level. When the first comparator 54 or the second comparator 56 outputs a high level, the control signal EN of the switch unit 58 controls the switch unit 58 to be in an on state, and at this time, the switch unit 58 outputs a high level to the control terminal of the switch tube 52 to turn on the switch tube 52, so that two pins of the level shift circuit 18 for outputting the reference level VSS and the low level signal VGL are shorted, and the reference level VSS and the low level signal VGL form an equal potential. However, when the switch unit 58 does not receive the on command of the control signal EN, the switch unit 58 is in an off state, so that the control terminal of the switch tube 52 receives the low level and is in an off state, and the reference level VSS and the low level VGL operate independently without mutual influence.
In the fourth embodiment, the switch unit 58 can be a single-pole double-throw switch 580, one end of the single-pole double-throw switch 580 is the reference level GND, and the other end is the low level signal VGL. When the control signal EN of the switch unit 58 is at a low level, the single-pole double-throw switch 580 is connected to the low level signal VGL, so that the control terminal of the switch tube 52 is connected to the level signal VGL and is not turned on, and therefore the reference level VSS of the level shift circuit 18 and the low level signal VSS do not affect each other. When the control signal EN of the single-switch unit 58 is at a high level, the single-pole double-throw switch 580 is connected to the reference level GND, and the GND is at a high level with respect to the input signals (the reference level VSS and the low level VGL) of the two negative voltages of the switch tube, so that the switch tube 52 is turned on, and the two pins of the level shift circuit 18 for outputting the reference level VSS and the low level VGL are shorted, and the reference level VSS and the low level VGL form an equal potential. The GND may be a reference ground level of the display panel 10 or an external reference ground signal. The single-pole double-throw switch 580 is connected to a reference level GND or a low-level signal VGL to determine the level of the input switch tube 52, the low-level signal VGL is originally a level signal provided by the level conversion circuit 18, and the reference signal GND can also be a reference level of any element in the display panel 10, so that the switch unit 58 does not need to provide a control signal EN through an additional control circuit, and the level signal originally existing in the display panel 10 controls the on or off of the switch tube 52, thereby not only simplifying the circuit, but also preventing the level of the low-level signal VGL from being higher than the reference level VSS.
In the first to fourth embodiments of the present invention, the level shift control circuit may be integrated with the level shift circuit into one chip, that is, into a level shift chip used in the driving circuit. The Level Shift control circuit in the first to fourth embodiments can be used for a Level Shift chip (Level Shift IC) in a GOA driving circuit to avoid the chip latch caused by the low Level VGL being higher than the reference Level VSS, which may cause the chip to fail or be damaged.
Through the technical scheme provided by the embodiment of the invention, two pins of the level conversion chip for outputting the low level signal and the reference signal are connected by a switching tube, so that whether the switching tube is conducted or not can be controlled by a simple circuit and elements without providing an additional control signal, when the level of the low level signal which is the substrate level (namely the signal with the lowest level) in the level conversion circuit is higher than the reference signal, two terminals for outputting the low level signal and the reference signal are in short circuit, and the low level signal and the reference signal are in short circuit to form an equal level due to the short circuit of the ends, thereby avoiding the latch effect caused by the substrate level of the chip being higher than other signals and achieving the purposes of protecting the level conversion circuit and maintaining the normal operation of the level conversion circuit.
The foregoing is only a preferred embodiment of the present invention, and those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be construed as the protection scope of the present invention.
Claims (4)
1. A level shift control circuit for outputting a high level and a low level to a gate line of an array substrate, the level shift control circuit having a first reference level, the level shift control circuit comprising:
a level shift circuit which provides three potentials of the first reference level, the low level and the high level; and a control circuit comprising:
the drain electrode of the switching tube is connected with the first reference level, and the source electrode of the switching tube is connected with the low level;
the switch unit is connected with the control end of the switch tube and used for controlling a signal input to the control end of the switch tube according to a control signal;
a first comparator having an output terminal, a positive input terminal, and a negative input terminal, wherein the positive input terminal of the first comparator is connected to the low level, and the negative input terminal of the first comparator is connected to the first reference level; and
a second comparator having an output terminal, a positive input terminal and a negative input terminal, wherein the positive input terminal of the second comparator is connected to a comparison reference voltage, and the negative input terminal of the second comparator is connected to a result voltage, wherein the result voltage detects an input voltage of the level shift control circuit;
the output end of the first comparator is electrically connected with the output end of the second comparator and is used for providing the control signal for the switch unit, when the control signal is at a high level, the switch unit controls the switch tube to be conducted, and when the switch tube is conducted, the drain electrode of the switch tube is in short circuit with the source electrode of the switch tube, so that the low level and the first reference level form a constant level; when the control signal is at a low level, the switch unit controls the switch tube to be switched off.
2. The level shift control circuit as claimed in claim 1, wherein the switch unit of the control circuit is a double-throw switch, the double-throw switch is used to connect the low level or the ground level, the low level is lower than the ground level, when the double-throw switch is connected to the ground level, the switch tube is conducted to short-circuit the low level and the first reference level to form a constant level.
3. The level shift control circuit of claim 1, wherein the level shift control circuit is an integrated circuit.
4. An array substrate driving circuit, comprising a plurality of gate lines, a Gate On Array (GOA) unit, and the level shift control circuit of claim 3.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910268931.2A CN110120196B (en) | 2019-04-04 | 2019-04-04 | Level conversion control circuit and array substrate driving circuit |
| PCT/CN2019/111553 WO2020199553A1 (en) | 2019-04-04 | 2019-10-17 | Level shift control circuit and level shift circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910268931.2A CN110120196B (en) | 2019-04-04 | 2019-04-04 | Level conversion control circuit and array substrate driving circuit |
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| CN110120196A CN110120196A (en) | 2019-08-13 |
| CN110120196B true CN110120196B (en) | 2021-05-07 |
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| WO (1) | WO2020199553A1 (en) |
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| CN110120196B (en) * | 2019-04-04 | 2021-05-07 | 深圳市华星光电半导体显示技术有限公司 | Level conversion control circuit and array substrate driving circuit |
| CN113192450B (en) * | 2021-04-27 | 2023-10-31 | 京东方科技集团股份有限公司 | Display device and use method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100909964B1 (en) * | 2007-05-14 | 2009-07-29 | 삼성전자주식회사 | Voltage Generator Prevents Latch-Up |
| KR100879706B1 (en) * | 2007-06-29 | 2009-01-22 | 매그나칩 반도체 유한회사 | Operating circuit of Display |
| CN101399525B (en) * | 2007-09-25 | 2010-07-07 | 奕力科技股份有限公司 | Voltage level clamping circuit and comparator module |
| US20150301415A1 (en) * | 2012-11-05 | 2015-10-22 | Sharp Kabushiki Kaisha | Liquid crystal display device |
| TWI637367B (en) * | 2016-09-12 | 2018-10-01 | 瑞鼎科技股份有限公司 | Gate driver |
| CN106652947A (en) * | 2016-12-27 | 2017-05-10 | 深圳市华星光电技术有限公司 | Gate drive circuit and liquid crystal display device |
| CN107516502B (en) * | 2017-10-12 | 2020-05-29 | 深圳市华星光电技术有限公司 | Liquid crystal display panel driving circuit and driving method |
| CN207765146U (en) * | 2017-12-05 | 2018-08-24 | 深圳Tcl新技术有限公司 | GOA driving circuits and display device |
| CN108510932B (en) * | 2018-03-30 | 2021-08-10 | 京东方科技集团股份有限公司 | Level conversion chip, control method thereof and shutdown drive circuit |
| CN109166552A (en) * | 2018-10-17 | 2019-01-08 | 深圳市华星光电半导体显示技术有限公司 | Liquid crystal display panel and its driving circuit |
| CN110120196B (en) * | 2019-04-04 | 2021-05-07 | 深圳市华星光电半导体显示技术有限公司 | Level conversion control circuit and array substrate driving circuit |
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| CN110120196A (en) | 2019-08-13 |
| WO2020199553A1 (en) | 2020-10-08 |
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