CN113436587B - Regulating circuit - Google Patents
Regulating circuit Download PDFInfo
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- CN113436587B CN113436587B CN202110689506.8A CN202110689506A CN113436587B CN 113436587 B CN113436587 B CN 113436587B CN 202110689506 A CN202110689506 A CN 202110689506A CN 113436587 B CN113436587 B CN 113436587B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0257—Reduction of after-image effects
Abstract
The invention relates to the technical field of display, and discloses a regulating and controlling circuit for a display device. The regulating and controlling circuit can prolong the power-down time of the second driving signal, further prolong the power-down time of the discharging driving signal, prolong the starting driving time of the discharging driving signal on the thin film transistor of the pixel array, prolong the charge releasing time of the display panel corresponding to the pixel array and improve the improvement effect on shutdown ghost.
Description
Technical Field
The invention relates to the technical field of display, in particular to a regulating circuit.
Background
A conventional display module, such as a liquid crystal display, includes a display panel, a gate driving circuit and a source driving circuit. The display panel comprises a plurality of scanning lines, a plurality of data lines and a pixel array, wherein the pixel array is formed by arranging a plurality of pixel units, each pixel unit mainly comprises a thin film transistor, a storage capacitor and a liquid crystal unit, each thin film transistor comprises a grid electrode, a source electrode and a drain electrode, the grid electrode of each thin film transistor is connected with a grid electrode driving circuit through the corresponding scanning line, and the source electrode is connected with a source electrode driving circuit through the corresponding data line. The gate driving circuit turns on or off the plurality of thin film transistors connected to the scan lines by supplying a gate line scan signal to the plurality of scan lines. When the thin film transistors are turned on, the source driving circuit provides gray scale display voltage for the data lines by providing data signals for the data lines, so that an image signal is stored in each pixel unit. Since the lcd displays images by accumulating charges in the storage capacitor between two opposite electrodes (e.g., the common electrode and the pixel electrode), when the display panel of the lcd is powered off, the accumulated charges will cause the corresponding pixels to be at different gray levels, and thus some images will remain on the display screen.
The timing sequence of partial signals of the conventional liquid crystal display device during the shutdown of the system is shown IN fig. 1, the high state level of the driving signal CLK is synchronized with the first driving signal VGH-IN, at time T1, the system is shut down, the power supply voltage VIN is gradually decreased, the discharge control signal XON is inverted from the high level to the low level when the power supply voltage VIN is decreased to the threshold value, the level of the driving signal CLK is identical to the level of the first driving signal VGH-IN, the thin film transistor IN the display panel is continuously turned on until the level of the driving signal CLK is decreased to the on threshold voltage of the thin film transistor, the charges stored IN the liquid crystal capacitor IN the display panel are released through the data line, the discharge time of the first driving signal VGH-IN directly affects the charge release time IN the display panel, while the discharge speed of the first driving signal VGH-IN is fast, the charge release time is short, the incomplete charge release has insufficient effect of improving shutdown ghost.
Disclosure of Invention
In view of the foregoing, an object of the present invention is to provide a control circuit, so as to improve the charge discharging time of the display panel of the display device and improve the effect of improving the shutdown ghost.
According to an aspect of the present invention, there is provided a regulator circuit for charge discharge regulation of a display panel, including:
the driving signal transmission unit is used for providing a second driving signal according to the first driving signal;
a discharge control unit for supplying a discharge driving signal to a scan line of a pixel array of the display panel according to the second driving signal, a level characteristic of the discharge driving signal being synchronized with a level characteristic of the second driving signal, wherein,
the driving signal transfer unit takes the first driving signal as the second driving signal when the discharge control signal is in an inactive state,
the driving signal transfer unit includes a charge storage path for obtaining a stored charge from the first driving signal, and the driving signal transfer unit superimposes the stored charge with the first driving signal to obtain the second driving signal when the discharge control signal is active.
Optionally, the driving signal transfer unit further includes:
a first diode, an anode of the first diode receiving the first driving signal;
a first capacitor, a first end of the first capacitor is connected with a cathode of the first diode, a second end of the first capacitor is grounded, and an anode of the first diode to the first end of the first capacitor correspond to the charge storage path;
and the stored charge output path is connected with the first end of the first capacitor and the second driving signal output end of the driving signal transmission unit and is conducted when the discharging control signal is effective.
Optionally, the driving signal transfer unit further includes:
a first resistor and a first transistor sequentially connected in series between a first driving signal input terminal of the driving signal transfer unit and ground;
a second resistor and a second transistor which are sequentially connected in series between a first driving signal input terminal and a second driving signal output terminal of the driving signal transfer unit,
wherein a gate of the first transistor receives the discharge control signal, a gate of the second transistor is connected to an intermediate node of the first resistor and the first transistor,
when the discharge control signal is inactive, the first transistor and the second transistor are turned on, and when the discharge control signal is active, the first transistor and the second transistor are turned off.
Optionally, the second transistor is a PMOS transistor.
Optionally, a third transistor is connected in series to the stored charge discharging path, and the driving signal transfer unit further includes:
a second diode having an anode receiving the first driving signal and a cathode connected to a gate of the third transistor;
and the control path is connected between the grid electrode of the third transistor and the ground and controls the on and off of the control path according to the state of the discharge control signal.
Optionally, the driving signal transfer unit further includes:
a second capacitor having a first terminal connected to the gate of the third transistor and a second terminal connected to ground.
Optionally, the third transistor is a PMOS transistor, and the control path is turned on when the discharge control signal is in an active state.
Optionally, the control path comprises a fourth transistor and a third resistor connected in series between the gate of the third transistor and ground in that order.
Optionally, the discharge control unit further provides a second control signal according to the second driving signal;
a grid electrode of the fourth transistor receives the second control signal, and the fourth transistor is an NMOS transistor;
the level state of the second control signal is synchronized with the level state of the discharge driving signal.
Optionally, the fourth transistor is a PMOS transistor, and a gate of the fourth transistor receives the discharge control signal and is turned on when the discharge control signal is valid.
The invention provides a regulation and control circuit for regulating and controlling charge release of a pixel array, which comprises: a driving signal transfer unit supplying a second driving signal to the discharge control unit according to the first driving signal, the discharge control unit provides a discharge driving signal to the scanning lines of the pixel array according to the second driving signal, wherein the drive signal transfer unit comprises a charge storage path for obtaining a stored charge from the first drive signal, the drive signal transfer unit also superimposes the stored charge with the first drive signal when the discharge control signal is active to obtain a second drive signal, the level of the second driving signal can be raised after the system is shut down, the time for the level of the second driving signal to be reduced to the conduction threshold level of the thin film transistor is prolonged, and further, the time for reducing the level of the discharge driving signal to the conduction threshold level of the thin film transistor is prolonged, the charge release time of the display panel is prolonged, and the improvement effect on shutdown afterimage is improved.
The control signal for controlling the on and off of the storage charge release path is provided by the discharge control unit or is controlled by the discharge control signal, and a signal source of the control signal is not required to be newly added.
The grid electrode of the third transistor of the stored charge release path is connected with the first end of the second capacitor and the cathode of the second diode, the anode of the second diode receives the first driving signal, high level control of the grid electrode of the third transistor can be guaranteed, the grid electrode of the third transistor is grounded through the control path, low level control of the grid electrode of the third transistor is correspondingly guaranteed, influence of fluctuation of the level state of the first driving signal on the control can be reduced, control reliability of the stored charge release path is improved, false opening probability of the stored charge release path in the normal working stage of a system is reduced, the level state of the second driving signal is guaranteed, and reliability of the system in normal working is guaranteed to be improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a partial signal timing diagram of a liquid crystal display device according to the related art;
fig. 2 is a schematic view showing a partial structure of a display device according to an embodiment of the present invention;
FIG. 3 illustrates a timing diagram of a portion of signals of a display apparatus according to an embodiment of the present invention;
fig. 4 shows a schematic structural diagram of a driving signal transfer unit of a regulation circuit according to an embodiment of the present invention;
FIGS. 5A and 5B are schematic diagrams illustrating simulation tests comparing partial signals of a display device according to an embodiment of the present invention with those of a related art display device;
fig. 6A and 6B are schematic diagrams showing simulation tests comparing partial signals of a display device according to another embodiment of the present invention with those of a related art display device.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
Fig. 2 is a schematic view showing a partial structure of a display device according to an embodiment of the present invention, and fig. 3 is a timing diagram showing signals of a portion of the display device according to an embodiment of the present invention.
Referring to fig. 1, 2 and 3, IN the driving circuit of the display device according to the embodiment of the invention, a driving signal transfer unit 12 is disposed between the power management circuit 11 and the discharge control unit 13, the power management circuit 11 provides a first driving signal VGH-IN and a discharge control signal XON according to the power supply voltage VIN, the driving signal transfer unit 12 provides a second driving signal VGH-OUT to the discharge control unit 13 according to the control of the first driving signal VGH-IN and the discharge control signal XON, and the discharge control unit 13 provides a discharge driving signal CLK to the scan lines of the pixel array 14 according to the voltage of the second driving signal VGH-OUT. The driving signal transfer unit 12 and the discharge control unit 13 correspond to a regulation circuit of an embodiment of the present invention. The discharge control unit 13 is, for example, a level shift circuit or a gate driving circuit.
In this embodiment, the driving signal transmitting unit 12 includes two current paths for respectively providing the third driving signal VGH-ON and the fourth driving signal VGH-OFF, and the driving signal transmitting unit 12 outputs the third driving signal VGH-ON as the second driving signal VGH-OUT when the discharge control signal XON is inactive and outputs the fourth driving signal VGH-OFF as the second driving signal VGH-OUT when the discharge control signal XON is active. That is, the timing of the second driving signal VGH-OUT corresponds to the coupling timing of the timings of the solid line portions of the third driving signal VGH-ON and the fourth driving signal VGH-OFF.
In the present embodiment, the high state of the discharge control signal XON is an inactive state, and the low state is an active state.
The time when the third driving signal VGH-ON starts to be powered down is the same as the time when the first driving signal VGH-IN starts to be powered down (time T1), the time when the fourth driving signal VGH-OFF starts to be powered down is the same as the time when the discharge control signal XON is turned over to be active (time T2), and the highest voltage average of the third driving signal VGH-ON and the fourth driving signal VGH-OFF is the same as the highest level of the first driving signal VGH-IN.
The current highest level state of the discharge driving signal CLK is identical to the current level state of the second driving signal VGH-OUT, and follows the second driving signal VGH-OUT when the discharge control signal XON is active after being a square signal when the discharge control signal XON is inactive.
When the discharge control signal XON is turned over to be effective, the second driving signal VGH-OUT is the fourth driving signal VGH-OFF, the voltage of the fourth driving signal VGH-OFF is increased to the voltage of the fourth driving signal VGH-OFF, the power-down time of the second driving signal VGH-OUT is prolonged, the power-down time of the discharge driving signal CLK can be prolonged, the time from the power-down of the discharge driving signal CLK to the conduction threshold voltage of the thin film transistor is prolonged, the charge release time of the display panel is prolonged, and the improvement effect of shutdown ghost is improved.
In the present embodiment, the discharge control unit 13 further provides a second control signal VGLH to the driving signal transmission unit 12, and controls the on and off of each current path of the driving signal transmission unit 12 together with the discharge control signal XON, so as to control the output of the driving signal transmission unit 12.
Fig. 4 shows a schematic structural diagram of a driving signal transmitting unit of a regulation circuit according to an embodiment of the present invention.
As shown in fig. 4, the driving signal transmitting unit 12 of the regulating circuit according to the embodiment of the present invention includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a first resistor R1, a second resistor R2, a third resistor R3, a first diode D1, a second diode D2, a first capacitor C1, and a second capacitor C2, in this embodiment, the first transistor Q1 and the fourth transistor Q4 are NMOS (N-Metal-Oxide-Semiconductor) transistors, and the second transistor Q2 and the third transistor Q3 are PMOS (P-Metal-Oxide-Semiconductor) transistors.
The first resistor R1 and the first transistor Q1 are sequentially connected IN series between the first driving signal input terminal and the ground, the second resistor R2 and the second transistor Q2 are sequentially connected IN series between the first driving signal input terminal and the second driving signal output terminal, the gate of the first transistor Q1 receives the discharge control signal XON, the gate of the second transistor Q2 is connected to an intermediate node between the first resistor R1 and the first transistor Q1, when the discharge control signal XON is IN an inactive state, the first transistor Q1 is turned ON, the gate of the second transistor Q2 is grounded, the second transistor Q2 is turned ON, and the first driving signal VGH-IN is directly output to the second driving signal output terminal through the second resistor R2 and the second transistor Q2, that is, the third driving signal VGH-ON is supplied to the discharge control unit 13 as the second driving signal VGH-OUT.
When the discharge control signal XON is IN an active state, the first transistor Q1 is turned off, the gate of the second transistor Q2 receives the driving of the first driving signal VGH-IN, and the second transistor Q2 is turned off.
An anode of the first diode D1 is connected to the first driving signal input terminal to receive the first driving signal VGH-IN, a cathode thereof is connected to the first terminal of the first capacitor C1, a second terminal of the first capacitor C1 is grounded to charge the first terminal of the first capacitor C1 according to the first driving signal VGH-IN to store charges at the first terminal of the first capacitor C1, the first terminal of the first capacitor C1 is further connected to the second driving signal output terminal through the third transistor Q3, a stored charge discharging path is formed when the third transistor Q3 is turned on, the stored charges at the first terminal of the first capacitor C1 are superimposed with the first driving signal VGH-IN to form a fourth driving signal VGH-OFF to be output as the second driving signal VGH-OUT to turn on the stored charge discharging path to raise the level of the second driving signal VGH-OUT when the discharge control signal is IN an active state, and prolonging the power-down time of the second driving signal VGH-OUT.
IN this embodiment, after the system is turned off, the discharge control signal XON controls the first transistor Q1 to turn off, when the first driving signal VGH-IN is not completely powered down, the second transistor Q2 is turned off according to the driving of the first driving signal VGH-IN, and when the first driving signal VGH-IN is completely powered down, the low level state of the second transistor Q2 can be turned on, and the first driving signal VGH-IN can be quickly transmitted and output through the second transistor Q2 when the system is turned on next time.
IN this embodiment, the anode of the second diode D2 is connected to the first driving signal input terminal, the cathode is connected to the gate of the third transistor Q3, the turn-OFF of the third transistor Q3 is controlled according to the high level of the first driving signal VGH-IN, the gate of the third transistor Q3 is also grounded through a control path, the control path includes a fourth transistor Q4 and a third resistor R3 connected IN series between the gate of the third transistor Q3 and the ground IN sequence, the gate of the fourth transistor Q4 receives the second control signal VGLH, and after the discharge control signal XON is turned to an active state, the second control signal VGLH controls the fourth transistor Q4 to be turned on, the gate of the third transistor Q3 is grounded, and the third transistor Q3 is turned on to provide the fourth driving signal VGH-OFF superimposed with the stored charge of the first end of the first capacitor C1 and the first driving signal VGH-IN.
The second control signal VGLH is at a low level when the system normally operates, for example, after the system is turned off, the level characteristic of the second control signal VGLH is consistent with the level characteristic of the discharge driving signal CLK, and after the discharge driving signal CLK is powered down to the turn-on threshold voltage of the thin film transistor, the second control signal VGLH is also powered down to the turn-on threshold of the fourth transistor Q4, that is, the turn-off time of the fourth transistor Q4 is consistent with the charge release stop time of the display panel, so that the fourth transistor Q4 is prevented from being turned off before the expected charge release time is over, the turn-on control of the third transistor Q3 is ensured, and the charge release effect is ensured.
The third resistor R3 is used as a current limiting resistor to ensure that the first driving signal VGH-IN is mainly transmitted through the current path of the third transistor Q3.
IN this embodiment, the gate of the third transistor Q3 is further connected to the first end of the second capacitor C2, the second end of the second capacitor C2 is grounded, so that the high state of the gate of the third transistor Q3 is maintained by charging the second capacitor C2 with the first driving signal VGH-IN during normal operation of the system, and the turn-off of the third transistor Q3 ensures that the level of the second driving signal VGH-OUT is the level of the first driving signal VGH-IN during normal operation of the system, and ensures the reliability of the second driving signal VGH-OUT as the reference signal during normal operation of the system.
In an alternative embodiment, without the second capacitor C2, the fourth transistor Q4 may be further disposed between the cathode of the second diode D2 and the gate of the third transistor Q3, and the third resistor R3 is disposed between the fourth transistor Q4 and the second diode D2, so that the gate of the third transistor Q3 may be quickly pulled down to the ground level when the fourth transistor Q4 is turned on, and the third transistor Q3 may be quickly turned on.
In an alternative embodiment, the fourth transistor Q4 is a PMOS transistor, and its gate receives the discharge control signal XON.
IN this embodiment, the first end of the second capacitor C2 may be grounded for discharging by the conduction of the control path, after the system is completely turned off, the second control signal VGLH may be powered down, the fourth transistor Q4 may be turned off, the third transistor Q3 may be controlled to be IN a conducting state according to the potential of the first end of the discharged second capacitor C2, and when the system is turned on again, the first driving signal VGH-IN may also be output through the stored charge release path corresponding to the third transistor Q3.
That is, the drive signal transfer unit 12 of the present embodiment has little influence on the transfer speed of the first drive signal VGH-IN to the discharge control unit 13.
Fig. 5A and 5B are schematic diagrams showing simulation tests comparing partial signals of a display device according to an embodiment of the present invention with those of a related art display device. Fig. 5A corresponds to a display device in the prior art, fig. 5B corresponds to a display device using a control circuit according to an embodiment of the present invention, where a point corresponds to data at a time when the discharge control signal XON is turned to be valid, and B point corresponds to data at a time when the voltage of the discharge drive signal CLK is reduced to the turn-on threshold voltage (6V) of the thin film transistor.
As shown in fig. 5A and 5B, in the prior art, the voltage of the discharge driving signal CLK when the discharge control signal XON is turned to be valid is 12.20V and is reduced to 6V after 10.48 ms, and the voltage of the discharge driving signal CLK when the discharge control signal XON of the display device using the control circuit of the embodiment of the present invention is turned to be valid is 17.80V and is reduced to 6V after 51.60 ms, that is, the control circuit of the embodiment of the present invention can increase the charge release time of the display panel from 10.48 ms to 51.60 ms, so that the increase of the charge release time of the display panel is obvious, and the improvement effect of the shutdown ghost is obvious.
Fig. 6A and 6B are schematic diagrams showing simulation tests comparing partial signals of a display device according to another embodiment of the present invention with those of a related art display device. Fig. 6A corresponds to a display device in the prior art, fig. 6B corresponds to a display device using a control circuit according to an embodiment of the present invention, where a point corresponds to data at a time when the discharge control signal XON is turned over to be valid, and B point corresponds to data at a time when the voltage of the discharge drive signal CLK is reduced to the turn-on threshold voltage of the thin film transistor.
As shown in fig. 6A and 6B, in the prior art, the voltage of the discharge driving signal CLK when the discharge control signal XON is turned to be active is 12.00V and is reduced to 6V after 408.0 milliseconds, and the voltage of the discharge driving signal CLK when the discharge control signal XON of the display device using the control circuit of the embodiment of the present invention is turned to be active is 15.00V and is reduced to 6V after 596.0 milliseconds, that is, the control circuit of the embodiment of the present invention can increase the charge release time of the display panel from 408.0 milliseconds to 596.0 milliseconds, which obviously increases the charge release time of the display panel and obviously improves the effect of improving the shutdown ghost.
The control circuit is provided with a drive signal transmission unit between the power management circuit and the discharge control unit, and is used for transmitting a first drive signal to the discharge control unit, storing charges when the system works normally, superposing the stored charges and the first drive signal into a second drive signal according to the discharge control signal after the system is shut down and providing the second drive signal to the discharge control unit, wherein the discharge control unit provides the discharge drive signal to a scanning line of the pixel array according to the level characteristic of the second drive signal of which the potential is raised, so that the power-down time of the second drive signal can be prolonged, the power-down time of the discharge drive signal is prolonged, the starting time of the discharge drive signal on a thin film transistor of the pixel array is prolonged, the charge release time of a display panel is prolonged, and the improvement effect of shutdown afterimages is improved.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (9)
1. A regulation circuit for charge discharge regulation of a display panel, comprising:
the driving signal transmission unit is used for providing a second driving signal according to the first driving signal;
a discharge control unit for supplying a discharge driving signal to a scan line of a pixel array of the display panel according to the second driving signal, a level characteristic of the discharge driving signal being synchronized with a level characteristic of the second driving signal, wherein,
the drive signal transfer unit takes the first drive signal as the second drive signal when the discharge control signal is in an inactive state,
the driving signal transfer unit includes:
a first diode, an anode of the first diode receiving the first driving signal;
a first capacitor, a first end of the first capacitor is connected to a cathode of the first diode, a second end of the first capacitor is grounded, an anode of the first diode to the first end of the first capacitor is a charge storage path, and the charge storage path is used for obtaining a stored charge from the first driving signal, and the driving signal transfer unit superimposes the stored charge and the first driving signal when the discharge control signal is active to obtain the second driving signal; and
a stored charge release path connecting a first end of the first capacitor and a second driving signal output end of the driving signal transfer unit and being turned on when the discharge control signal is active; wherein a third transistor is connected in series on the stored charge releasing path.
2. The regulation circuit of claim 1, wherein the drive signal transfer unit further comprises:
a first resistor and a first transistor sequentially connected in series between a first driving signal input terminal of the driving signal transfer unit and ground;
a second resistor and a second transistor which are sequentially connected in series between a first driving signal input terminal and a second driving signal output terminal of the driving signal transfer unit,
wherein a gate of the first transistor receives the discharge control signal, a gate of the second transistor is connected to an intermediate node of the first resistor and the first transistor,
when the discharge control signal is inactive, the first transistor and the second transistor are turned on, and when the discharge control signal is active, the first transistor and the second transistor are turned off.
3. The regulation circuit of claim 2,
the second transistor is a PMOS transistor.
4. The regulation circuit of claim 1, wherein the drive signal transfer unit further comprises:
a second diode having an anode receiving the first driving signal and a cathode connected to a gate of the third transistor;
and a control path connected between the gate of the third transistor and ground, and controlling the on and off of the control path according to the state of the discharge control signal.
5. The regulator circuit according to claim 4, wherein the driving signal transfer unit further comprises:
a second capacitor having a first terminal connected to the gate of the third transistor and a second terminal connected to ground.
6. The regulation circuit of claim 4,
the third transistor is a PMOS transistor, and the control path is turned on when the discharge control signal is in an active state.
7. The regulation circuit of claim 4,
the control path includes a fourth transistor and a third resistor connected in series between a gate of the third transistor and ground in that order.
8. The regulation circuit of claim 7,
the discharge control unit also provides a second control signal according to the second driving signal;
a grid electrode of the fourth transistor receives the second control signal, and the fourth transistor is an NMOS transistor;
the level state of the second control signal is synchronized with the level state of the discharge driving signal.
9. The regulation circuit of claim 7,
the fourth transistor is a PMOS (P-channel metal oxide semiconductor) transistor, and the grid electrode of the fourth transistor receives the discharge control signal and is conducted when the discharge control signal is effective.
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