CN111312185B

CN111312185B - Display control circuit, control method thereof and display device

Info

Publication number: CN111312185B
Application number: CN202010121390.3A
Authority: CN
Inventors: 刘娜妮; 赖意强; 黄宇鹏; 翁彬
Original assignee: BOE Technology Group Co Ltd; Fuzhou BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Fuzhou BOE Optoelectronics Technology Co Ltd
Priority date: 2020-02-26
Filing date: 2020-02-26
Publication date: 2022-01-25
Anticipated expiration: 2040-02-26
Also published as: CN111312185A

Abstract

The application provides a display control circuit, a control method thereof and a display device, relates to the technical field of display, and can solve the problem that the display device has picture flicker. The display control circuit comprises a voltage conversion sub-circuit which is used for converting an input voltage into a first voltage and a second voltage. The system end control sub-circuit is used for outputting a third voltage from the first output end when the first voltage end outputs the first voltage; and when the voltage output by the first voltage end is less than the first voltage, outputting a fourth voltage by the first output end. The display terminal control sub-circuit is used for outputting a display control signal to the source driver and outputting a data voltage to a data line of the display screen under the control of the third voltage; outputting a first clock signal to a gate driver; the first clock signal is also used for outputting a second clock signal to the grid driver under the control of a fourth voltage; the second clock signal is used for controlling the gate driver to output a transistor starting signal to the grid line so as to release charges in the transistor.

Description

Display control circuit, control method thereof and display device

Technical Field

The invention relates to the technical field of display, in particular to a display control circuit, a control method thereof and a display device.

Background

Liquid Crystal Display (LCD) devices have the advantages of low cost and long service life. In a display panel of a liquid crystal display device, a plurality of transistors exist, and in the process of powering on and powering off the transistors, if charges which are not completely released before exist, the display device can have a picture flash problem, and the display effect of the display device is influenced.

Disclosure of Invention

The embodiment of the invention provides a display control circuit, a control method thereof and a display device, which can solve the problem that the display device has picture flicker when being turned on and turned off.

In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:

in one aspect, a display control circuit is provided, and is characterized in that the display control circuit is used for controlling a display screen to display.

The display control circuit includes:

a voltage conversion sub-circuit coupled to the first voltage terminal and the second voltage terminal; the voltage conversion sub-circuit is used for converting an input voltage into a first voltage and a second voltage, outputting the first voltage from the first voltage end and outputting the second voltage from the second voltage end; wherein the second voltage is less than the first voltage.

A system terminal control sub-circuit coupled to the first voltage terminal, the third voltage terminal, the fourth voltage terminal and the first output terminal; the system end control sub-circuit is used for outputting a third voltage provided by the third voltage end from the first output end when the first voltage end outputs the first voltage; the system end control sub-circuit is further used for outputting a fourth voltage provided by the fourth voltage end from the first output end when the voltage output by the first voltage end is smaller than the first voltage; wherein the fourth voltage is less than the third voltage.

A display terminal control sub-circuit coupled to the first output terminal, the second voltage terminal, and a gate driver and a source driver of the display screen; the display terminal control sub-circuit is used for outputting a display control signal to the source driver under the control of the third voltage, and the display control signal is used for controlling the source driver to output a data voltage to a data line of the display screen; the display terminal control sub-circuit is further used for outputting a first clock signal to the gate driver under the control of the third voltage; the first clock signal is used for controlling the grid driver to output a grid driving signal to a grid line of the display screen; the display terminal control sub-circuit is also used for outputting no output to the source driver under the control of the fourth voltage; the display terminal control sub-circuit is further used for outputting a second clock signal to the gate driver under the control of the fourth voltage; the second clock signal is used for controlling the gate driver to output a transistor starting signal to the gate line so as to release charges in the transistor.

Optionally, the system-side control sub-circuit includes: a first control unit and a second control unit.

The first control unit is coupled with the first voltage end and the fourth voltage end; the second control unit is coupled to the third voltage terminal and the fourth voltage terminal.

The first control unit is used for controlling the second control unit to output the third voltage provided by the third voltage end from the first output end when the first voltage end outputs the first voltage.

The first control unit is further configured to control the second control unit to output the fourth voltage provided by the fourth voltage terminal from the first output terminal when the voltage output by the first voltage terminal is smaller than the first voltage.

Optionally, the system terminal control sub-circuit is further coupled to a fifth voltage terminal.

The system-side control sub-circuit includes: a first control unit and a second control unit.

The first control unit is coupled with the first voltage end and the fifth voltage end; the second control unit is coupled to the third voltage terminal and the fourth voltage terminal.

Optionally, the first control unit includes: the circuit comprises a first resistor, a second resistor, a diode, a first capacitor and a first triode; the second control unit includes: a third resistor and a second triode.

One end of the first resistor is coupled with the first voltage end, and the other end of the first resistor is coupled with the base electrode of the first triode; one pole of the diode is coupled with the first voltage end, and the other pole of the diode is coupled with one end of the second resistor; the other end of the second resistor is coupled with an emitter of the first triode; the first end of the first capacitor is coupled with the fourth voltage end, and the other end of the first capacitor is coupled with the emitter of the first triode; the collecting electrode of the first triode is coupled with the base electrode of the second triode, the emitting electrode of the second triode is coupled with the fourth voltage signal end, the collecting electrode of the second triode is coupled with one end of the third resistor, and the other end of the third resistor is coupled with the third voltage end.

Optionally, the display terminal control sub-circuit includes a timing controller and a power manager.

The time schedule controller is coupled with the first output end, the second voltage end and the power manager; the time schedule controller is used for outputting a display control signal to the source driver and outputting a first control signal to the power manager when the first output end outputs the third voltage; the timing controller is further configured to output no output to the source driver and output a second control signal to the power manager when the first output terminal outputs the fourth voltage.

The power supply manager is coupled with the second voltage end; the power manager is used for outputting a first clock signal to the gate driver when receiving a first control signal, and outputting a second clock signal to the gate driver when receiving a second control signal.

Optionally, the voltage conversion sub-circuit includes a first transformer, a second transformer and a second capacitor.

The first transformer is coupled to the input voltage and the first voltage terminal, and is configured to convert the input voltage into the first voltage and output the first voltage from the first voltage terminal.

The second transformer is coupled to the first voltage terminal and the second voltage terminal, and is configured to convert the first voltage into the second voltage and output the second voltage from the second voltage terminal.

One end of the second capacitor is coupled with the first voltage end, and the other end of the second capacitor is coupled with the fourth voltage end.

In another aspect, a display device is provided, which includes the display control circuit as described above.

In another aspect, a method for controlling a display control circuit is provided, including:

the voltage conversion sub-circuit converts an input voltage into a first voltage and a second voltage, and outputs the first voltage from a first voltage terminal and the second voltage from a second voltage terminal.

And the system end control sub-circuit outputs a third voltage provided by a third voltage end from a first output end when receiving the first voltage output by the first voltage end.

And when receiving the voltage which is output by the first voltage end and is less than the first voltage, the system end control sub-circuit outputs a fourth voltage provided by a fourth voltage end from the first output end, wherein the fourth voltage is less than the third voltage.

When receiving the third voltage, the display terminal control sub-circuit outputs a display control signal to a source driver in a display screen, and the source driver outputs a data voltage to a data line in the display screen after receiving the display control signal; and outputting a first clock signal to a gate driver in the display screen, wherein the gate driver outputs a gate driving signal to a gate line in the display screen after receiving the first clock signal.

And the display terminal control sub-circuit outputs no output signal to the source driver and outputs a second clock signal to the gate driver when receiving a fourth voltage, and the gate driver controls the conduction of a transistor in the gate driver after receiving the second clock signal so as to release charges in the transistor.

Optionally, in a case that the system-side control sub-circuit includes a first control unit and a second control unit, and wherein the first control unit is coupled to the first voltage terminal and the fourth voltage terminal; the second control unit is coupled with the third voltage end and the fourth voltage end:

the control method of the system end control sub-circuit comprises the following steps:

when the first voltage end outputs a first voltage, the first control unit controls the second control unit to output the third voltage provided by the third voltage end from the first output end.

When the voltage output by the first voltage end is smaller than the first voltage, the first control unit controls the second control unit to output the fourth voltage provided by the fourth voltage end by the first output end.

One end of the first resistor is coupled with the first voltage end, and the other end of the first resistor is coupled with the base electrode of the first triode; one pole of the diode is coupled with the first voltage end, and the other pole of the diode is coupled with one end of the second resistor; the other end of the second resistor is coupled with an emitter of the first triode; the first end of the first capacitor is coupled with the fourth voltage end, and the other end of the first capacitor is coupled with the emitter of the first triode; the collecting electrode of the first triode is coupled with the base electrode of the second triode, the emitting electrode of the second triode is coupled with the fourth voltage signal end, the collecting electrode of the second triode is coupled with one end of the third resistor, and the other end of the third resistor is coupled with the third voltage end:

when the first voltage end outputs the first voltage, the first voltage is charged to the first capacitor through the diode and the second resistor, the base voltage of the first triode is larger than the emitter voltage of the first triode, the first triode is cut off, the second triode is cut off, and the third voltage end outputs a third voltage to the first output end.

When the first voltage end outputs a voltage smaller than the first voltage, the first capacitor discharges, so that the voltage of the emitting electrode of the first triode is larger than the base electrode voltage of the emitting electrode of the first triode, the first triode is started, after the first triode is started, the base electrode voltage of the second triode is higher than the emitter electrode voltage of the second triode, the second triode is started, and the fourth voltage provided by the fourth voltage end is transmitted to the first output end.

The application provides a display control circuit, a control method thereof and a display device. The display control circuit comprises a voltage conversion sub-circuit, a system end control sub-circuit and a display end control sub-circuit. When the display device is shut down, the system end control sub-circuit receives a voltage smaller than the first voltage, the display end control sub-circuit can stop outputting display control signals to the source driver, the load of the display control circuit is reduced, the power-down time of the first voltage is delayed, the longer the power-down time of the first voltage is, the longer the time that the second voltage can be maintained is, and the longer the time for subsequently starting the Xon function is; meanwhile, the display terminal control sub-circuit stops outputting the display control signal and simultaneously opens the Xon function, so that compared with the prior art, the Xon function can be started only when the second voltage is powered off to the threshold voltage, the Xon function is started earlier in the application, the time for outputting the second clock signal is longer, charges in the transistor can be fully released, and the probability that the display device is subjected to picture flashing during the startup and shutdown is lower.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display control circuit according to an embodiment of the present invention;

fig. 2a and fig. 2b are schematic structural diagrams of another display control circuit according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a system-side control sub-circuit according to an embodiment of the present invention;

fig. 4a and fig. 4b are schematic structural diagrams of another display control circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of another display control circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of another display control circuit according to an embodiment of the present invention;

fig. 7 is a flowchart illustrating a control method of a display control circuit according to an embodiment of the present invention.

Reference numerals:

1-a display control circuit; 11-a voltage conversion sub-circuit; 111-a first transformer; 112-a second transformer; 12-system side control sub-circuit; 121-a first control unit; 122-a second control unit; 13-display end control sub-circuit; 131-a time schedule controller; 132-a power manager; 133-a connector; 2-a gate driver; 3-source driver.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The application provides a display device, the display device for example includes a display screen and a system board electrically connected with the display screen, a display control circuit is arranged in the display screen and the system board, the display control circuit is used for controlling the display screen to display, the display control circuit for example includes a voltage conversion sub-circuit, a system end control sub-circuit and a display end control sub-circuit.

The display screen is, for example, a liquid crystal display screen, and the liquid crystal display screen includes, for example, a display terminal control sub-circuit, a data line, a Gate line, a source Driver and a Gate Driver in a display control circuit, wherein the Gate Driver is integrated in the liquid crystal display screen by a Gate Driver On Array (GOA) technology; the system board includes, for example, a voltage conversion sub-circuit and a system-side control sub-circuit in the display control circuit.

The liquid crystal display panel includes, for example, a plurality of sub-pixels arranged in an array, and a pixel driving circuit is provided in each sub-pixel, and the pixel driving circuit includes a plurality of transistors, such as Thin Film Transistors (TFTs); the same row of pixel driving circuits are electrically connected with the same grid line, and the grid line is used for receiving a grid driving signal; the same column of pixel driving circuits is electrically connected with the same data line, and the data line is used for receiving data voltage. After the pixel driving circuit receives the gate driving signal and the data voltage, the pixel driving circuit may control the sub-pixels to display different luminance according to the data voltage.

Each circuit in the display control circuit is explained in detail below:

as shown in fig. 1, the voltage converting sub-circuit 11 is coupled to the first voltage terminal V1 and the second voltage terminal V2. The voltage conversion sub-circuit 11 is configured to convert the input voltage into a first voltage and a second voltage, and output the first voltage from the first voltage terminal V1 and the second voltage from the second voltage terminal V2; wherein the second voltage is less than the first voltage.

Illustratively, the first voltage and the second voltage are both direct current voltages, for example.

Illustratively, the input voltage is, for example, 220V, the first voltage is, for example, 19V, and the second voltage is, for example, 12V.

For example, the input voltage may also be equal to the first voltage, for example, the input voltage is 19V.

The system-side control sub-circuit 12 is coupled to the first voltage terminal V1, the third voltage terminal V3, the fourth voltage terminal V4, and the first output terminal Out 1. The system terminal control sub-circuit 12 is configured to output a third voltage provided by the third voltage terminal V3 from the first output terminal Out1 when the first voltage terminal V1 outputs the first voltage.

For example, when the first voltage terminal V1 outputs the first voltage of 19V, the system-terminal control sub-circuit 12 outputs the third voltage from the first output terminal Out 1.

The system-side control sub-circuit 12 is further configured to output a fourth voltage provided by the fourth voltage terminal V4 from the first output terminal Out1 when the voltage output by the first voltage terminal V1 is less than the first voltage; wherein the fourth voltage is less than the third voltage.

Illustratively, the third voltage terminal V3 is, for example, 3.3V, and the third voltage is 3.3V; the fourth voltage terminal is, for example, a ground terminal, and the fourth voltage is 0V.

When the input voltage stops inputting signals to the voltage conversion sub-circuit 11 and the voltage conversion sub-circuit 11 starts to power down, the first voltage starts to decrease, so that the voltage output from the first voltage terminal V1 is smaller than the first voltage.

For example, when the voltage output from the first voltage terminal V1 is 18V, the system-terminal control sub-circuit 12 outputs the fourth voltage from the first output terminal Out 1.

And a display terminal control sub-circuit 13 coupled to the first output terminal Out1, the second voltage terminal V2, the gate driver 2 and the source driver 3 of the display screen. The display terminal control sub-circuit 13 is configured to output a display control signal to the source driver 3 under the control of the third voltage, where the display control signal is used to control the source driver 3 to output a data voltage to a data line of the display screen; the display terminal control sub-circuit 13 is further configured to output a first clock signal to the gate driver 2 under the control of the third voltage; the first clock signal is used to control the gate driver 2 to output a gate driving signal to gate lines of the display screen.

After receiving the display control signal, the source driver 3 outputs data voltages to all data lines in the display screen, the data voltages are written into the turned-on pixel driving circuits, and the pixel driving circuits can control the sub-pixels to display different brightness according to the data voltages after receiving the data voltages.

The first clock signal includes a high level and a low level, and the gate driver 2 outputs a gate driving signal to the gate lines after receiving the first clock signal, and in some embodiments, the level of the gate driving signal is the same as the level of the first clock signal; the gate driving signal may turn on the pixel driving circuit row by row so that the pixel driving circuit may receive the data voltage.

The display terminal control sub-circuit 13 is further configured to output no output to the source driver 3 under the control of the fourth voltage; the display terminal control sub-circuit 13 is further configured to output a second clock signal to the gate driver 2 under the control of the fourth voltage; the second clock signal is used to control the gate driver 2 to output a transistor-on signal to the gate line to discharge the charge in the transistor.

Since the gate line is electrically connected to the pixel driving circuit, the transistor turn-on signal output by the gate line is received by the pixel driving circuit, that is, the transistor turn-on signal output by the gate line can turn on the pixel driving circuit, so that the transistor in the pixel driving circuit can release charges.

When the transistor in the pixel driving circuit is an N-type transistor, the starting signal of the transistor is high level; when the transistor is a P-type transistor, the turn-on signal of the transistor is at a low level.

Illustratively, the level of the second clock signal is a high level, and in some embodiments, the level of the transistor turn-on signal is the same as the level of the second clock signal.

The display terminal control sub-circuit 13 does not output to the source driver 3 under the control of the fourth voltage, that is, the display terminal control sub-circuit 13 stops outputting the display control signal to the source driver 3 after receiving the fourth voltage; when the source driver 3 does not receive the display control signal, it stops outputting the data voltage to the data line. And the data line is used as the maximum load in the display screen, and when the display terminal control sub-circuit 13 stops outputting the display control signal to the source driver 3, the whole display control circuit 1 will be in a light load state.

In the related art, a display control circuit in a display device includes a voltage conversion module and a control module, wherein the voltage conversion module can convert an input voltage into a second voltage, for example, the input voltage is 220V, and the second voltage is 12V. The control module is used for providing a display control signal for the source driver and providing a grid driving signal for the grid driver. When the display device is shut down, the second voltage starts to be gradually reduced due to the existence of some capacitors in the display control circuit, and when the second voltage is powered down (reduced) to the threshold voltage (threshold voltage) of the control module, the control module starts the Xon function (shutdown ghost elimination function) to eliminate the charges in the transistors in the display screen. The starting of the Xon function can be performed at the moment of shutdown, so that the control module outputs an Xon signal to the gate driver, each shift register in the gate driver is triggered to output a transistor starting signal through the Xon signal (clock signal), transistors in pixel driving circuits of all rows are opened through the gate lines, charges stored in the transistors are released, and shutdown ghost shadow is avoided. In the related art, the output time of the Xon signal is about 100 ms. In the related art, on one hand, the control module can start the Xon function only when the second voltage is powered down to the threshold voltage of the control module, and the time for turning on the transistor is short and the charge in the transistor is not completely released if the Xon function is turned on later; on the other hand, when the Xon function is turned on, the control module still outputs a display control signal to the source driver, so that the source driver continuously outputs data voltage to the data line, and the data line is used as the maximum load in the display screen, so that the second voltage is quickly powered off, and the faster the second voltage is powered off, the shorter the time for turning on the Xon function can be; the shorter the time the Xon function is on, the less the charge in the transistors in the pixel driving circuit is discharged sufficiently. Therefore, in the related art, since the time for turning on the Xon function is short, the charge remains in the display device much, and the probability of occurrence of the picture flash problem is high.

In the present application, the display control circuit 1 includes a voltage conversion sub-circuit 11, a system-side control sub-circuit 12, and a display-side control sub-circuit 13. Wherein the voltage converting sub-circuit 11 may convert the input voltage into a first voltage and a second voltage; when the system-side control sub-circuit 12 receives the first voltage, the third voltage is output to the display-side control sub-circuit 13, and after the system-side control sub-circuit 12 receives a voltage smaller than the first voltage, the fourth voltage is output to the display-side control sub-circuit 13; the display terminal control sub-circuit 13 may output the display control signal and the first clock signal according to the received third voltage, and may stop outputting the display control signal and outputting the second clock signal according to the received fourth voltage. When the display device is shut down, the system-end control sub-circuit receives a voltage smaller than the first voltage, and the display-end control sub-circuit 13 can stop outputting the display control signal to the source driver 3, so that the load of the display control circuit is reduced, the power-down time of the first voltage is delayed, the longer the power-down time of the first voltage is, the longer the time that the second voltage can be maintained is, and the longer the time for subsequently starting the Xon function is; meanwhile, the display terminal control sub-circuit 13 stops outputting the display control signal and simultaneously opens the Xon function, so that compared with the prior art, the Xon function can be opened only when the second voltage is powered off to the threshold voltage, the Xon function is opened earlier in the application, the time for outputting the second clock signal is longer, charges in the transistor can be fully released, the probability of picture flash of the display device during startup and shutdown is lower, and the display effect is better.

It can be understood by those skilled in the art that the second clock signal in this application is an Xon signal, and the display terminal control sub-circuit 13 outputs the second clock signal after the Xon function is turned on.

Optionally, as shown in fig. 2a, the system-side control sub-circuit 12 includes: a first control unit 121 and a second control unit 122.

The first control unit 121 is coupled to the first voltage terminal V1 and the fourth voltage terminal V4; the second control unit 122 is coupled to the third voltage terminal V3 and the fourth voltage terminal V4.

Illustratively, the fourth voltage is less than the third voltage, e.g., 3.3V, and the fourth voltage is, e.g., 1V.

Illustratively, the fourth voltage terminal V4 is a ground terminal, and the fourth voltage is 0V.

The first control unit 121 is configured to control the second control unit 122 to output the third voltage provided by the third voltage terminal V3 from the first output terminal Out1 when the first voltage terminal V1 outputs the first voltage.

The first control unit 121 is further configured to control the second control unit 122 to output the fourth voltage provided by the fourth voltage terminal V4 from the first output terminal Out1 when the voltage output from the first voltage terminal V1 is less than the first voltage.

For example, when the first control unit 121 receives the 19V first voltage output from the first voltage terminal V1, the second control unit 122 is controlled to output the third voltage of 3.3V; when the first control unit 121 receives a voltage output by the first voltage terminal V1, which is smaller than the first voltage, for example, 18V, which indicates that the first voltage starts to decrease, the second control unit 122 outputs a fourth voltage of 0V.

The first control unit 121 can control the output of the second control unit 122 according to the signal output by the first voltage terminal V1, and has a simple structure and simple control.

Optionally, as shown in fig. 2b, the system-side control sub-circuit 12 is further coupled to the fifth voltage terminal V5.

The system-side control sub-circuit 12 includes: a first control unit 121 and a second control unit 122.

The first control unit 121 is coupled to the first voltage terminal V1 and the fifth voltage terminal V5; the second control unit 122 is coupled to the third voltage terminal V3 and the fourth voltage terminal V4.

For example, the magnitude of the fifth voltage provided by the fifth voltage terminal V5 is different from the magnitude of the fourth voltage provided by the fourth voltage terminal V4; the fifth voltage is, for example, 2V; the fourth voltage is, for example, 0V, i.e., the fourth voltage terminal V4 is grounded.

The voltage of the fifth voltage terminal V5 is different from the voltage of the fourth voltage terminal V4, so that the first control unit 121 and the second control unit 122 are connected in an overlapping manner according to their respective circuit structures, and the connected voltage terminal of the first control unit 121 is relatively independent from the connected voltage terminal of the second control unit 122, so that the connection is facilitated.

Alternatively, as shown in fig. 3, the first control unit 121 includes: the circuit comprises a first resistor R1, a second resistor R2, a diode D2, a first capacitor C1 and a first triode TR 1; the second control unit 122 includes: a third resistor R3 and a second transistor TR 2.

One end of the first resistor R1 is coupled to the first voltage terminal V1, and the other end of the first resistor R1 is coupled to the base of the first transistor TR 1. One pole of the diode D2 is coupled to the first voltage terminal V1, and the other pole is coupled to one end of the second resistor R2. The other end of the second resistor R2 is coupled to the emitter of the first transistor TR 1. One end of the first capacitor C1 is coupled to the fourth voltage terminal V4, and the other end is coupled to the emitter of the first transistor TR 1. The collector of the first transistor TR1 is coupled to the base of the second transistor TR 2. An emitter of the second transistor TR2 is coupled to the fourth voltage signal terminal, a collector of the second transistor TR2 is coupled to one terminal of the third resistor R3, and the other terminal of the third resistor R3 is coupled to the third voltage terminal V3. The diode D2 is used to prevent the charge from flowing back to the first voltage terminal when the first voltage starts to decrease and the first capacitor C1 starts to discharge, wherein the current in the diode D2 flows in a direction from the first voltage terminal V1 to the second resistor R2.

Illustratively, the resistance of the second voltage is equal to or greater than the resistance of the first resistor R1.

Optionally, the resistance of the first resistor R1 is equal to the resistance of the second resistor R2.

Optionally, the first transistor TR1 is a PNP transistor; the second transistor TR2 is an NPN transistor, and has a threshold voltage of, for example, 0.6V.

Optionally, the first capacitor C1 is an MLCC (Multi-layer Ceramic Capacitors) capacitor.

When the first voltage is output from the first voltage terminal V1, since the total resistance of the second resistor R2 and the diode D2 is greater than the resistance of the first resistor R1, the base voltage of the first transistor TR1 is greater than the emitter voltage thereof, and the first transistor TR1 is in a cut-off state; the first capacitor C1 is in a charged state. Illustratively, the first voltage is, for example, 19V, the emitter voltage of the first transistor TR1 is, for example, 18.8V, and the base voltage of the first transistor TR1 is, for example, 18.5V.

When the first transistor TR1 is in a cut-off state, the base voltage of the second transistor TR2 is equal to 0V, the emitter of the second transistor TR2 is electrically connected to the fourth voltage terminal V4, and the second transistor TR2 is also in a cut-off state, so that the third voltage terminal V3 outputs the third voltage from the first output terminal Out 1.

When the first voltage terminal V1 outputs a voltage smaller than the first voltage, since the emitter of the first transistor TR1 is electrically connected to the first capacitor C1, the first capacitor C1 starts to discharge to maintain the emitter voltage of the first transistor TR1, so that the base voltage of the first transistor TR1 is smaller than the emitter voltage thereof, the first transistor TR1 is turned on, and at this time, the collector voltage of the first transistor TR1 is equal to the emitter voltage thereof.

Since the base of the second transistor TR2 is electrically connected to the collector of the first transistor TR1, the base voltage of the second transistor TR2 is equal to the collector voltage of the first transistor TR1, for example, 18.8V; the emitter of the second transistor TR2 is electrically connected to a fourth voltage terminal V4, the voltage of the fourth voltage terminal V4 is 0V, for example, so that the second transistor TR2 will be in a conducting state, when the second transistor TR2 is in a conducting state, i.e., in a saturation state, the voltage of the collector thereof will be equal to the voltage of the emitter thereof, while the emitter of the second transistor TR2 is grounded, and the voltage of the emitter is 0V, so that the first output terminal Out1 will output a low level signal of 0V.

The first control unit 121 and the second control unit 122 are simple in structure, and the whole system-side control sub-circuit 12 includes only one MLCC capacitor, and the height of the MLCC capacitor is low, so that the requirement of the display control circuit 1 on the height is met, and the miniaturization design is met.

Alternatively, as shown in fig. 4a, the display terminal control sub-circuit 13 includes a timing controller 131 and a power manager 132.

The Power manager 132 is, for example, a PMIC (Power Management IC), and the Power manager 132 has an Xon function.

The timing controller 131 is coupled to the first output terminal Out1, the second voltage terminal V2, and the power manager 132. The timing controller 131 is configured to output a display control signal to the source driver 3 and output a first control signal to the power manager 132 when the first output terminal Out1 outputs the third voltage.

When receiving the third voltage, the timing controller 131 outputs a display control signal to the source driver 3, the source driver 3 outputs a data voltage to the data line, and the pixel driving circuit receives the data voltage and performs display; meanwhile, the timing controller 131 outputs a first control signal to the power manager 132.

The timing controller 131 is also configured to output no output to the source driver 3 and output a second control signal to the power manager 132 when the first output terminal Out1 outputs the fourth voltage.

When the timing controller 131 receives the fourth voltage, it stops outputting the display control signal, i.e., no output, to the source driver 3, while the timing controller 131 outputs the second control signal to the power manager 132.

In some embodiments, the third voltage is a high level of 3.3V, and the fourth voltage is a low level of 0V, that is, when the timing control receives the high level, the display control signal is normally output to the source driver 3, and the first control signal is output to the power manager 132 at the same time; when the timing controller 131 receives the low level, it stops outputting the display control signal to the source driver 3 to reduce the load, and simultaneously outputs the second control signal to the power manager 132.

The power manager 132 is coupled to the second voltage terminal V2. The power manager 132 is configured to output a first clock signal to the gate driver 2 when receiving the first control signal, and output a second clock signal to the gate driver 2 when receiving the second control signal.

The second control signal is a control signal that can turn on the Xon function in the power manager 132, and the second clock signal is an Xon signal, that is, the power manager 132 turns on the Xon function when receiving the second control signal.

The first clock signal is different from the second clock signal; the first clock signal comprises continuous high level and low level, and after the first clock signal is transmitted by the gate driver 2, the pixel driving circuit in the display screen can be turned on and off line by line so as to enable the pixel driving circuit to work normally; and the second clock signal only comprises a high level, and the second clock signal can turn on all the transistors in the pixel driving circuit after being transmitted by the gate driving circuit, so as to release the charges existing in the transistors.

The timing controller 131 controls the source driver 3 and the power manager 132 to operate according to different signals received by the timing controller, and particularly, when a voltage smaller than the first voltage is received, the output of the display control signal to the source driver 3 may be stopped to reduce the load, and the power-down time of the first voltage and the second voltage may be prolonged, and meanwhile, the Xon function of the power manager 132 is turned on by the second control signal, and compared with the related art in which the Xon function is turned on only when the second voltage is powered down to the threshold voltage, the Xon function is turned on earlier in the present application, the time for the gate driver 2 to provide the high-level signal to the gate line is longer, the time for releasing the charges in the pixel driving circuit is longer, and the effect for releasing the charges is better.

Optionally, as shown in fig. 4b, the display terminal control sub-circuit 13 further includes a connector 133, wherein one end of the connector 133 is coupled to the first output terminal Out1 and the second voltage terminal V2, and the other end is coupled to the timing controller 131 and the power manager 132.

The line connection between the timing controller 131, the power manager 132, and the first output terminal Out1 and the second voltage terminal V2 can be simplified by the connector 133, and the assembly efficiency between the modules can be improved.

Optionally, the voltage converting sub-circuit 11 is further coupled to the fourth voltage terminal V4.

On this basis, optionally, as shown in fig. 5, the voltage converting sub-circuit 11 includes a first transformer 111, a second transformer 112 and a second capacitor C2.

The first transformer 111 is coupled to the input voltage and the first voltage terminal V1, and the first transformer 111 is configured to convert the input voltage into a first voltage and output the first voltage from the first voltage terminal V1.

The second transformer 112 is coupled to the first voltage terminal V1 and the second voltage terminal V2, and the second transformer 112 is configured to convert the first voltage into a second voltage and output the second voltage from the second voltage terminal V2.

One end of the second capacitor C2 is coupled to the first voltage terminal V1, and the other end is coupled to the fourth voltage terminal V4. The second capacitor C2 is used to reduce the power-down speed of the first voltage by discharging when the first voltage starts to decrease.

Illustratively, the input voltage is 220V, and the input voltage is converted into a first voltage of 19V after passing through the first transformer 111, and the first voltage is converted into a second voltage of 12 after passing through the second transformer 112.

Optionally, the first transformer 111 is an ac-to-dc transformer; the second transformer 112 is a dc-to-dc transformer.

The display control circuit 1 of the present application is explained and explained in its entirety below.

As shown in fig. 6, the display control circuit 1 includes: a voltage conversion sub-circuit 11, a system-side control sub-circuit 12, and a display-side control sub-circuit 13.

The voltage converting sub-circuit 11 includes a first transformer 111, a second transformer 112 and a second capacitor C2. The first transformer 111 has one end electrically connected to the input voltage and the other end electrically connected to the first voltage terminal V1.

The second transformer 112 has one end electrically connected to the first voltage terminal V1 and the other end electrically connected to the second voltage terminal V2.

One end of the second capacitor C2 is electrically connected to the first voltage terminal V1, and the other end is electrically connected to the fourth voltage terminal V4.

The system-side control sub-circuit 12 includes: a first control unit 121 and a second control unit 122; the first control unit 121 includes a first resistor R1, a second resistor R2, a diode D2, a first capacitor C1, and a first transistor TR 1; the second control unit 122 includes a third resistor R3 and a second transistor TR 2.

One end of the first resistor R1 is electrically connected to the first voltage terminal V1, and the other end is electrically connected to the base of the first transistor TR 1.

One end of the diode D2 is electrically connected to the first voltage terminal V1, and the other end is electrically connected to one end of the second resistor R2.

The other end of the second resistor R2 is electrically connected to the emitter of the first transistor TR 1.

One end of the first capacitor C1 is electrically connected to the emitter of the first transistor TR1, and the other end is electrically connected to the fourth voltage terminal V4.

The collector of the first transistor TR1 is electrically connected to the base of the second transistor TR 2.

One end of the third resistor R3 is electrically connected to the third voltage terminal V3, and the other end is electrically connected to the collector of the second transistor TR 2.

The emitter of the second transistor TR2 is electrically connected to the fourth voltage terminal V4, and the collector is electrically connected to the first output terminal Out 1.

The display-side control sub-circuit 13 includes: a connector 133, a timing controller 131, and a power manager 132.

One end of the connector 133 is electrically connected to the first output terminal Out1 and the second voltage terminal V2; and the other end is electrically connected to the timing controller 131 and the power manager 132.

The timing controller 131 is electrically connected to the power manager 132.

Optionally, the display control circuit 1 may further include a source driver 3 and a gate driver 2. The source driver 3 is electrically connected to the timing controller 131, and the gate driving circuit is electrically connected to the power manager 132.

Display control circuit 1 simple structure in this application can prolong the time that the Xon function was opened in the power manager to make the interior electric charge of transistor fully release in the display screen, reduce display device and take place to draw the probability of dodging.

As shown in fig. 7, an embodiment of the present application further provides a control method of a display control circuit 1, including:

s1, the voltage converting sub-circuit 11 converts the input voltage into a first voltage and a second voltage, and outputs the first voltage from the first voltage terminal V1 and the second voltage from the second voltage terminal V2.

Illustratively, the first voltage is 19V and the second voltage is 12V.

S2, the system side control sub-circuit 12 outputs the third voltage provided by the third voltage terminal V3 from the first output terminal Out1 when receiving the first voltage output by the first voltage terminal V1.

When the display device is in normal display, the first voltage terminal V1 outputs a first voltage.

Illustratively, the third voltage is equal to 3.3V, and the system-side control sub-circuit 12 outputs the third voltage of 3.3V from the first output terminal Out1 and the first output terminal Out1 is high when receiving the first voltage equal to 19V. That is, the system-side control sub-circuit 12 outputs a high level when the display device normally displays.

S3, when receiving the voltage output by the first voltage terminal V1 and smaller than the first voltage, the system terminal control sub-circuit 12 outputs a fourth voltage provided by the fourth voltage terminal V4 from the first output terminal Out1, where the fourth voltage is smaller than the third voltage.

After the display device is turned off, the voltage output from the first voltage terminal V1 starts to decrease gradually from the first voltage, instead of directly changing to 0V, due to the discharge of the capacitor C2 in the voltage conversion sub-circuit 11. Illustratively, the voltage output by the first voltage output terminal decreases from 19V.

For example, the power-down time of the first voltage is about 400ms, and the time for which the normal output of the second voltage can be maintained is about 200 ms.

The system-side control sub-circuit 12 outputs a fourth voltage from the first output terminal Out1 when receiving a voltage smaller than the first voltage, and outputs a low level from the first output terminal Out1 when the fourth voltage terminal V4 is grounded. That is, when the display device is turned off, the system-side control sub-circuit 12 outputs a low level.

S4, when receiving the third voltage, the display terminal control sub-circuit 13 outputs a display control signal to the source driver 3 in the display panel, and after receiving the display control signal, the source driver 3 outputs a data voltage to the data line in the display panel; and outputting a first clock signal to the gate driver 2 in the display screen, wherein the gate driver 2 outputs a gate driving signal to the gate line in the display screen after receiving the first clock signal.

When the display terminal control sub-circuit 13 receives the third voltage, it proves that the display device is in a normal display state, and therefore, the display terminal control sub-circuit 13 needs to output a display control signal to the source driver 3 to ensure that the source driver 3 can normally output the data voltage to the data line.

During displaying, the gate driving signal output by the gate driver 2 firstly turns on the transistor in the pixel driving circuit, and then the data line writes the data voltage into the transistor, so that the gate driver 2 needs to output the gate driving signal to the gate line after receiving the first clock signal to turn on the transistor in the pixel driving circuit.

S5, the display terminal control sub-circuit 13 outputs no output signal to the source driver 3 and outputs the second clock signal to the gate driver 2 when receiving the fourth voltage, and the gate driver 2 outputs a transistor-on signal to the gate line after receiving the second clock signal to release the charge in the transistor.

When the display terminal control sub-circuit 13 receives the fourth voltage, it indicates that the display device is in the power-off state, the display terminal control sub-circuit 13 stops transmitting the input voltage to the voltage converting sub-circuit 11, and the voltage output by the first voltage terminal V1 starts to decrease from the first voltage.

For example, when the holding time of the second voltage is about 200ms, the time for which the power manager 132 can normally output the second clock signal is also 200 ms.

It should be understood by those skilled in the art that the second voltage is used to maintain the power manager 132 to operate normally, and thus the longer the second voltage is maintained, the longer the power manager 132 can output the second clock signal.

After receiving the fourth voltage, the display terminal control sub-circuit 13 stops outputting the display control signal to the source driver 3, and then the source driver 3 does not output the data voltage to the data line any more, so that the load of the display control circuit 1 is reduced, and the power-down speed of the voltage output by the first voltage terminal V1 can be slowed down. Meanwhile, the display terminal control sub-circuit 13 outputs a second clock signal to the gate driver 2, the gate driver 2 outputs the second clock signal to the gate line after receiving the second clock signal, the gate line transmits the second clock signal to the transistor in the pixel driving circuit, and the transistor in the pixel driving circuit is an N-type transistor, and the second clock signal is at a high level, so that the transistor in the pixel driving circuit can be controlled to be turned on by the second clock signal, and charges in the transistor can be released.

On one hand, the power-down time of the first voltage is prolonged by reducing the load of the display control circuit 1, the longer the power-down time of the first voltage is, the longer the time for maintaining the second voltage is, and the longer the time for starting the Xon function of the display terminal control sub-circuit 13 is; on the other hand, when the system-side control sub-circuit 12 stops outputting the display control signal to the source driver 3, the Xon function in the display-side control sub-circuit 13 is turned on, and the time for turning on the Xon function is earlier, so that the present application can make the time for the display-side control sub-circuit 13 to output the second clock signal longer, and the longer the time for maintaining the second clock signal is, the more sufficient the charge in the transistor in the pixel driving circuit is released, so that the present application can solve the problem that the display device has the picture flash.

Alternatively, in the case that the system-side control sub-circuit 12 includes the first control unit 121 and the second control unit 122, and wherein the first control unit 121 is coupled to the first voltage terminal V1 and the fourth voltage terminal V4; the second control unit 122 is coupled to the third voltage terminal V3 and the fourth voltage terminal V4.

The control method of the system-side control sub-circuit 12 includes:

s30, when the first voltage terminal V1 outputs the first voltage, the first control unit 121 controls the second control unit 122 to output the third voltage provided by the third voltage terminal V3 from the first output terminal Out 1.

As shown in fig. 6, when the first voltage is output from the first voltage terminal V1, the first transistor TR1 of the first control unit 121 is turned off, and the second transistor TR2 of the second control unit 122 is also turned off, so that the second control unit 122 outputs the third voltage, i.e., the third voltage is output from the first output terminal Out 1.

S31, when the voltage outputted from the first voltage terminal V1 is less than the first voltage, the first control unit 121 controls the second control unit 122 to output the fourth voltage provided from the fourth voltage terminal V4 from the first output terminal Out 1.

As shown in fig. 6, when the voltage output from the first voltage terminal V1 is less than the first voltage, the first transistor TR1 in the first control unit 121 is turned on, and after the first transistor TR1 is turned on, the second transistor TR2 in the second control unit 122 can be controlled to be turned on, so that the second control unit 122 outputs a fourth voltage, i.e., the fourth voltage is output from the first output terminal Out 1.

The first control unit 121 controls the operating state of the second control unit 122, so that the signals output by the first output terminal Out1 are different, and the control method of the whole system-side control sub-circuit 12 is simple and accurate.

Optionally, the first control unit 121 includes: the circuit comprises a first resistor R1, a second resistor R2, a diode, a first capacitor C1 and a first triode TR 1; the second control unit 122 includes: a third resistor R3 and a second transistor TR 2.

One end of the first resistor R1 is coupled to the first voltage end V1, and the other end of the first resistor R1 is coupled to the base of the first transistor TR 1; one pole of the diode is coupled with the first voltage end V1, and the other pole of the diode is coupled with one end of the second resistor R2; the other end of the second resistor R2 is coupled with the emitter of the first triode TR 1; a first end of the first capacitor C1 is coupled to the fourth voltage terminal V4, and the other end is coupled to the emitter of the first transistor TR 1; the collector of the first triode TR1 is coupled to the base of the second triode TR2, the emitter of the second triode TR2 is coupled to the fourth voltage signal terminal, the collector of the second triode TR2 is coupled to one terminal of the third resistor R3, and the other terminal of the third resistor R3 is coupled to the third voltage terminal V3.

The control method of the system-side control sub-circuit 12 includes:

s300, when the first voltage is output by the first voltage end V1, the first voltage charges the first capacitor C1 through the diode and the second resistor R2, so that the base voltage of the first triode TR1 is larger than the emitter voltage of the first triode TR1, the first triode TR1 is cut off, the second triode TR2 is cut off, and the third voltage end V3 outputs a third voltage to the first output end Out 1.

As shown in fig. 6, when the display apparatus normally displays, the first voltage terminal V1 outputs the first voltage, the emitter voltage of the first transistor TR1 is greater than the base voltage thereof, the first transistor TR1 is in an off state, the base of the second transistor TR2 is electrically connected to the collector of the first transistor TR1, so that the base voltage of the second transistor TR2 is 0V, and the emitter voltage of the second transistor TR2 is also 0V, so that the second transistor TR2 is also in an off state, and thus the third voltage of the third voltage terminal V3 is output via the first output terminal Out 1.

S310, when the first voltage end V1 outputs a voltage smaller than the first voltage, the first capacitor C1 discharges, so that the voltage of an emitter of the first triode TR1 is larger than the base voltage of the emitter, the first triode TR1 is turned on, after the first triode TR1 is turned on, the base voltage of the second triode TR2 is higher than the emitter voltage of the second triode TR2, and the fourth voltage provided by the fourth voltage end V4 is transmitted to the first output end Out 1.

When the display device is turned off, the first voltage starts to be powered down (lowered), and the first capacitor C1 is discharged, thereby making the emitter voltage of the first transistor TR1 greater than the base voltage thereof, the first transistor TR1 is turned on, the collector of the first transistor TR1 outputs a high voltage, and thus the base voltage of the second transistor TR2 is a high voltage greater than the emitter voltage 0V of the second transistor TR2, and thus the second transistor TR2 is also turned on. After the second transistor TR2 is turned on, the voltage output by the collector thereof is approximately equal to the voltage of the emitter thereof, so the first output terminal Out1 outputs a voltage of 0V.

The operating state of the second transistor TR2 in the second control unit 122 is controlled by the operating state of the first transistor TR1 in the first control unit 121, so that the signals output by the first output terminal Out1 are different, and the control method of the whole system terminal control sub-circuit 12 is simple and accurate.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. The display control circuit is characterized in that the display control circuit is used for controlling a display screen to display;

the display control circuit includes:

a voltage conversion sub-circuit coupled to the first voltage terminal and the second voltage terminal; the voltage conversion sub-circuit is used for converting an input voltage into a first voltage and a second voltage, outputting the first voltage from the first voltage end and outputting the second voltage from the second voltage end; wherein the second voltage is less than the first voltage;

a system terminal control sub-circuit coupled to the first voltage terminal, the third voltage terminal, the fourth voltage terminal and the first output terminal; the system end control sub-circuit is used for outputting a third voltage provided by the third voltage end from the first output end when the first voltage end outputs the first voltage; the system end control sub-circuit is further used for outputting a fourth voltage provided by the fourth voltage end from the first output end when the voltage output by the first voltage end is smaller than the first voltage; wherein the fourth voltage is less than the third voltage;

a display terminal control sub-circuit coupled to the first output terminal, the second voltage terminal, and a gate driver and a source driver of the display screen; the display terminal control sub-circuit is used for outputting a display control signal to the source driver under the control of the third voltage, and the display control signal is used for controlling the source driver to output a data voltage to a data line of the display screen; the display terminal control sub-circuit is further used for outputting a first clock signal to the gate driver under the control of the third voltage; the first clock signal is used for controlling the grid driver to output a grid driving signal to a grid line of the display screen; the display terminal control sub-circuit is also used for outputting no output to the source driver under the control of the fourth voltage; the display terminal control sub-circuit is further used for outputting a second clock signal to the gate driver under the control of the fourth voltage; the second clock signal is used for controlling the gate driver to output a transistor starting signal to the grid line so as to release charges in the transistor;

the system-side control sub-circuit includes: a first control unit and a second control unit;

the first control unit is coupled with the first voltage end and the fourth voltage end; the second control unit is coupled with the third voltage end and the fourth voltage end;

the first control unit is used for controlling the second control unit to output the third voltage provided by the third voltage end from the first output end when the first voltage end outputs the first voltage;

2. The display control circuit of claim 1, wherein the system-side control sub-circuit is further coupled to a fifth voltage side;

the first control unit is coupled with the first voltage end and the fifth voltage end; the second control unit is coupled with the third voltage end and the fourth voltage end;

3. The display control circuit according to claim 1, wherein the first control unit includes: the circuit comprises a first resistor, a second resistor, a diode, a first capacitor and a first triode; the second control unit includes: a third resistor and a second triode;

4. The display control circuit according to claim 1, wherein the display terminal control sub-circuit includes a timing controller and a power manager;

the time schedule controller is coupled with the first output end, the second voltage end and the power manager; the time schedule controller is used for outputting a display control signal to the source driver and outputting a first control signal to the power manager when the first output end outputs the third voltage; the time schedule controller is further used for outputting no output to the source driver and outputting a second control signal to the power manager when the first output end outputs the fourth voltage;

5. The display control circuit of claim 1, wherein the voltage conversion sub-circuit comprises a first transformer, a second transformer, and a second capacitor;

the first transformer is coupled with the input voltage and the first voltage end, and is used for converting the input voltage into the first voltage and outputting the first voltage from the first voltage end;

the second transformer is coupled with the first voltage end and the second voltage end, and is used for converting the first voltage into the second voltage and outputting the second voltage from the second voltage end;

6. A display device characterized by comprising the display control circuit according to any one of claims 1 to 5.

7. A control method of a display control circuit according to any one of claims 1 to 5, comprising:

the voltage conversion sub-circuit converts an input voltage into a first voltage and a second voltage, outputs the first voltage from a first voltage end, and outputs the second voltage from a second voltage end;

when the system end control sub-circuit receives the first voltage output by the first voltage end, the third voltage provided by the third voltage end is output by the first output end;

when receiving the voltage which is output by the first voltage end and is smaller than the first voltage, the system end control sub-circuit outputs a fourth voltage which is provided by a fourth voltage end and is smaller than the third voltage from the first output end;

when receiving the third voltage, the display terminal control sub-circuit outputs a display control signal to a source driver in a display screen, and the source driver outputs a data voltage to a data line in the display screen after receiving the display control signal; outputting a first clock signal to a gate driver in the display screen, wherein the gate driver outputs a gate driving signal to a gate line in the display screen after receiving the first clock signal;

when receiving a fourth voltage, the display terminal control sub-circuit outputs no output signal to the source driver and outputs a second clock signal to the gate driver, and the gate driver controls the transistor in the gate driver to be turned on after receiving the second clock signal so as to release charges in the transistor;

in a case where the system-side control sub-circuit includes a first control unit and a second control unit, and wherein the first control unit is coupled to the first voltage terminal and the fourth voltage terminal; the second control unit is coupled with the third voltage end and the fourth voltage end:

when the first voltage end outputs a first voltage, the first control unit controls the second control unit to output the third voltage provided by the third voltage end from the first output end;

8. The control method of a display control circuit according to claim 7,

the first control unit includes: the circuit comprises a first resistor, a second resistor, a diode, a first capacitor and a first triode; the second control unit includes: a third resistor and a second triode;

when the first voltage end outputs the first voltage, the first voltage charges the first capacitor through the diode and the second resistor, the base voltage of the first triode is greater than the emitter voltage of the first triode, the first triode is cut off, the second triode is cut off, and the third voltage end outputs a third voltage to the first output end;